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* Add the variant of __sparc_v9__ with five underscores, not just four.Joerg Sonnenberger2015-11-101-0/+3
| | | | llvm-svn: 252640
* Reorganise CPU handling for Sparc. When using -mcpu=v9 and co, __sparcv8Joerg Sonnenberger2015-11-091-0/+9
| | | | | | | | | is not defined for 32bit mode, but __sparcv9 is. Pass down the correct -target-cpu flags to the backend, so that instruction restrictions are applied correctly. Pass down the correct -A flag when not using IAS. The latter is limited to NetBSD targets in this commit. llvm-svn: 252545
* [X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro ↵Craig Topper2015-10-151-0/+44
| | | | | | defines for the same. And add the flags to correct CPU names. llvm-svn: 250368
* [PowerPC] Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_* macros on all PPC coresHal Finkel2015-10-011-0/+3
| | | | | | | | | | | | We support all __sync_val_compare_and_swap_* builtins (only 64-bit on 64-bit targets) on all cores, and should define the corresponding __GCC_HAVE_SYNC_COMPARE_AND_SWAP_* macros, just as GCC does. As it turns out, this is really important because they're needed to prevent a bad ODR violation with libstdc++'s std::shared_ptr (this is well explained in PR12730). We were doing this only for P8, but this is necessary on all PPC systems. llvm-svn: 249009
* Add support for System z vector language extensionsUlrich Weigand2015-07-301-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The z13 vector facility has an associated language extension, closely modeled on AltiVec/VSX. The main differences are: - vector long, vector float and vector pixel are not supported - vector long long and vector double are supported (like VSX) - comparison operators return a vector rather than a scalar integer - shift operators behave like the OpenCL shift operators - vector bool is only supported as argument to certain operators; some operators allow mixing a bool with a non-bool vector This patch adds clang support for the extension. It is closely modelled on the AltiVec support. Similarly to the -faltivec option, there's a new -fzvector option to enable the extensions (as well as an -mzvector alias for compatibility with GCC). There's also a separate LangOpt. The extension as implemented here is intended to be compatible with the -mzvector extension recently implemented by GCC. Based on a patch by Richard Sandiford. Differential Revision: http://reviews.llvm.org/D11001 llvm-svn: 243642
* Testing for the fix for bug 23429.Nemanja Ivanovic2015-05-141-0/+13
| | | | | | | | | Follow-up to commit for revision 236848. Just a test case for the macro definition under the right CPU/Arch. One combination was actually missed in the initial fix: - powerpc64-unknown-unknown -mcpu=pwr8 (rather than -mcpu=power8). llvm-svn: 237386
* [Sparc] Add support for 'sparcel' to clang.Douglas Katzman2015-05-111-0/+33
| | | | | | Differential Revision: http://reviews.llvm.org/D8784 llvm-svn: 237001
* [SystemZ] Support transactional execution on zEC12Ulrich Weigand2015-04-011-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The zEC12 provides the transactional-execution facility. This is exposed to users via a set of builtin routines on other compilers. This patch adds clang support to enable those builtins. In partciular, the patch: - enables the transactional-execution feature by default on zEC12 - allows to override presence of that feature via the -mhtm/-mno-htm options - adds a predefined macro __HTM__ if the feature is enabled - adds support for the transactional-execution GCC builtins - adds Sema checking to verify the __builtin_tabort abort code - adds the s390intrin.h header file (for GCC compatibility) - adds s390 sections to the htmintrin.h and htmxlintrin.h header files Since this is first use of target-specific intrinsics on the platform, the patch creates the include/clang/Basic/BuiltinsSystemZ.def file and hooks it up in TargetBuiltins.h and lib/Basic/Targets.cpp. An associated LLVM patch adds the required LLVM IR intrinsics. For reference, the transactional-execution instructions are documented in the z/Architecture Principles of Operation for the zEC12: http://publibfp.boulder.ibm.com/cgi-bin/bookmgr/download/DZ9ZR009.pdf The associated builtins are documented in the GCC manual: http://gcc.gnu.org/onlinedocs/gcc/S_002f390-System-z-Built-in-Functions.html The htmxlintrin.h intrinsics provided for compatibility with the IBM XL compiler are documented in the "z/OS XL C/C++ Programming Guide". llvm-svn: 233804
* Add Clang support for PPC cryptography builtinsNemanja Ivanovic2015-03-041-0/+6
| | | | | | Review: http://reviews.llvm.org/D7951 llvm-svn: 231291
* [X86] Slightly refactor default features for AMD bdver cpus (NFC). Also add ↵Andrea Di Biagio2014-11-061-0/+10
| | | | | | | | | | | | | | | | | | | missing checks to test for target features. This patch simplifies how default target features are set for AMD bdver2 and bdver1. In particular, method 'getDefaultFeatures' now implements a fallthrough from case 'CK_BDVER2' to case 'CK_BDVER1'. That is because 'bdver2' has the same features available in bdver1 plus BMI, FMA, F16C and TBM. This patch also adds missing checks for predefined macros in test predefined-arch-macros.c. In the case of BTVER2, the test now also checks for F16C, BMI and PCLMUL. In the case of BDVER3 and BDVER4, the test now also checks for the presence of FSGSBASE. Differential Revision: http://reviews.llvm.org/D6134 llvm-svn: 221449
* [PowerPC] Add feature for Power8 vector extensionsBill Schmidt2014-10-101-0/+7
| | | | | | | | | | | | | | | | | | The current VSX feature for PowerPC specifies availability of the VSX instructions added with the 2.06 architecture version. With 2.07, the architecture adds new instructions to both the Category:Vector and Category:VSX instruction sets. Additionally, unaligned vector storage operations have improved performance. This patch adds a feature to provide access to the new instructions and performance capabilities of Power8. For compatibility with GCC, the feature is controlled via a new -mpower8-vector switch, and the feature causes the __POWER8_VECTOR__ builtin define to be generated by the preprocessor. There is a companion patch for llvm being committed at the same time. llvm-svn: 219502
* [x86] Enable broadwell target in clang.Robert Khasanov2014-09-191-0/+64
| | | | | | Added -madx option llvm-svn: 218116
* [SKX] Enabling SKX target (Skylake server chip) Robert Khasanov2014-07-301-0/+72
| | | | | | | | | a) add SKX support to Clang driver; b) add tests for SKX target and AVX512BW, AVX512DQ, AVX512VL features into clang driver tests Patch by Zinovy Nis <zinovy.y.nis@intel.com> llvm-svn: 214306
* Add support for -march=bdver4.Benjamin Kramer2014-05-021-0/+70
| | | | llvm-svn: 207848
* Driver: Add support for -march=bdver3 on x86.Benjamin Kramer2013-11-041-0/+66
| | | | llvm-svn: 193985
* Add preprocessor support for powerpc vsx.Eric Christopher2013-10-161-0/+7
| | | | | | The test should be expanded upon for more powerpc checking. llvm-svn: 192849
* Remove an old, seemingly out of date, comment.Eric Christopher2013-10-161-3/+0
| | | | | | The referenced script no longer seems to exist. llvm-svn: 192848
* Enabling 3DNow! prefetch instruction support for a few AMD processors in theYunzhong Gao2013-10-161-0/+8
| | | | | | | | | | clang front end. This change will allow the __PRFCHW__ macro to be set on these processors and hence include prfchwintrin.h in x86intrin.h header. Support for the intrinsic itself seems to have already been added in r178041. Differential Revision: http://llvm-reviews.chandlerc.com/D1934 llvm-svn: 192829
* Adding -mtbm and -mno-tbm command line options to the clang front end for theYunzhong Gao2013-09-241-0/+2
| | | | | | | | | x86 TBM instruction set. Also adding a __TBM__ macro if the TBM feature is enabled. Otherwise there should be no functionality change to existing features. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1693 llvm-svn: 191326
* Add support for -march=slm, aka Intel Atom Silvermont.Benjamin Kramer2013-08-301-0/+36
| | | | llvm-svn: 189670
* Add avx512cd, avx512er, avx512pf feature flags and enable them on KNL CPU.Craig Topper2013-08-211-0/+6
| | | | llvm-svn: 188867
* Rename __AVX512__ to __AVX512F__Craig Topper2013-08-201-2/+2
| | | | llvm-svn: 188764
* Add AVX-512 feature flag and knl cpu to clang.Craig Topper2013-08-201-0/+64
| | | | llvm-svn: 188758
* Revert r188756 because some other changes snuck in with it.Craig Topper2013-08-201-64/+0
| | | | llvm-svn: 188757
* Add AVX-512 feature flag and knl cpu to clang.Craig Topper2013-08-201-0/+64
| | | | llvm-svn: 188756
* Add 'not' to commands that are expected to fail.Rafael Espindola2013-07-041-27/+27
| | | | | | | This is at least good documentation, but also opens the possibility of using pipefail. llvm-svn: 185652
* Add support for -march=btver2.Benjamin Kramer2013-05-031-0/+46
| | | | llvm-svn: 181006
* Add missing features for misc x86 CPUs to CPU feature translation. Patch by ↵Eli Friedman2012-11-171-1/+160
| | | | | | Jung-uk Kim. llvm-svn: 168239
* Add clang support of RTM from TSXMichael Liao2012-11-101-0/+2
| | | | | | | | | | | | - New options '-mrtm'/'-mno-rtm' are added to enable/disable RTM feature - Builtin macro '__RTM__' is defined if RTM feature is enabled - RTM intrinsic header is added and introduces 3 new intrinsics, namely '_xbegin', '_xend', and '_xabort'. - 3 new builtins are added to keep compatible with gcc, namely '__builtin_ia32_xbegin', '__builtin_ia32_xend', and '__builtin_ia32_xabort'. - Test cases for pre-defined macro and new intrinsic codegen are added. llvm-svn: 167665
* Wire up -mrdrnd for X86.Benjamin Kramer2012-07-071-0/+6
| | | | | | | For some reason GCC decided to call the feature rdrnd instead of rdrand, which requires translating it for LLVM. llvm-svn: 159897
* Add XOP feature flag.Craig Topper2012-06-091-0/+3
| | | | llvm-svn: 158284
* Add __POPCNT__ to test cases for corei7 and corei7-avxCraig Topper2012-06-031-0/+4
| | | | llvm-svn: 157905
* Add fma feature flag for Intel FMA instructions.Craig Topper2012-06-031-0/+56
| | | | llvm-svn: 157904
* Define __SSE4A__ when targeting new AMD CPUs.Benjamin Kramer2012-05-291-0/+42
| | | | | | This doesn't really fit the existing SSELevel so it gets an extra flag. llvm-svn: 157630
* Pass a target triple explicitly to check platform specific macros definitions.Simon Atanasyan2012-05-091-0/+82
| | | | | | That allows to run the tests on all platforms successfully. llvm-svn: 156500
* Enable AVX/AVX2 for Sandy Bridge, Ivy Bridge, and Haswell CPUs.Craig Topper2012-04-261-8/+4
| | | | llvm-svn: 155624
* Generate tests for all of the x86 SIMD instruction feature setChandler Carruth2011-09-281-0/+244
| | | | | | | | | | | | | | predefines based on the output of GCC as well as the CPU predefines. Invert tests for __AVX__, Clang's AVX feature is hard coded off still. Switch Atom from 'SSE3' to 'SSSE3'. This matches GCC's behavior, Intel's documentation, and ICC's documentation (such as I could dig up). Switch Athlon and Geode to enable 3dnowa rather than just 3dnow and nothing (resp.). llvm-svn: 140692
* Add a little banner to this test. This lets my scripts more easilyChandler Carruth2011-09-281-0/+4
| | | | | | | | | | automate the process of updating and generating these tests. If anyone is really interested, I can check my scripts for generating this test in, but its a horrible pile of shell... Not sure its really worth it. llvm-svn: 140691
* Fix a think-o on my part that got enshrined in a FIXME by setting up theChandler Carruth2011-09-281-6/+3
| | | | | | __tune_...__ define as well. llvm-svn: 140690
* Teach Clang to reject 32-bit only CPUs when compiling in 64-bit mode.Chandler Carruth2011-09-281-0/+206
| | | | | | Add 64-bit preprocessor macro tests. llvm-svn: 140688
* Begin fixing Clang's predefined macros for various architectures. ThisChandler Carruth2011-09-281-0/+415
is *very* much a WIP that I'll be refining over the next several commits, but I need to get this checkpoint in place for sanity. This also adds a much more comprehensive test for architecture macros, which is roughly generated by inspecting the behavior of a trunk build of GCC. It still requires some massaging, but eventually I'll even check in the script that generates these so that others can use it to append more tests for more architectures, etc. Next up is a bunch of simplification of the Targets.cpp code, followed by a lot more test cases once we can reject invalid architectures. llvm-svn: 140673
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