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* IRGen: Add optnone attribute on function during O0Mehdi Amini2017-05-291-3/+2
| | | | | | | | | | | Amongst other, this will help LTO to correctly handle/honor files compiled with O0, helping debugging failures. It also seems in line with how we handle other options, like how -fnoinline adds the appropriate attribute as well. Differential Revision: https://reviews.llvm.org/D28404 llvm-svn: 304127
* ARM & AArch64: convert asm tests to LLVM IR and restrict optimizations.Tim Northover2016-03-091-105/+149
| | | | | | | | | | | | | | | This is mostly a one-time autoconversion of tests that checked assembly after "-Owhatever" compiles to only run "opt -mem2reg" and check the assembly. This should make them much more stable to changes in LLVM so they won't break on unrelated changes. "opt -mem2reg" is a compromise designed to increase the readability of tests that check dataflow, while minimizing dependency on LLVM. Hopefully mem2reg is stable enough that no surpises will come along. Should address http://llvm.org/PR26815. llvm-svn: 263048
* Revert "[Reassociate] Update test cases due to r222142."Chad Rosier2014-11-191-4/+4
| | | | | | | | | This reverts commit r222144. Commit r222142 is being reverted due to a spec2006/gcc execution-time regression. Update mips-varargs test as well. llvm-svn: 222397
* [Reassociate] Update test cases due to r222142.Chad Rosier2014-11-171-4/+4
| | | | llvm-svn: 222144
* ARM: add support for v8 ldaex/stlex builtins.Tim Northover2014-07-021-1/+162
| | | | | | | | | | | | | | ARMv8 adds (to both AArch32 and AArch64) acquiring and releasing variants of the exclusive operations, in line with the C++11 memory model. This adds support for two new intrinsics to expose them to C & C++ developers directly: __builtin_arm_ldaex and __builtin_arm_stlex, in direct analogy with the versions with no implicit barrier. rdar://problem/15885451 llvm-svn: 212175
* AArch64/ARM64: rename ARM64 components to AArch64Tim Northover2014-05-241-21/+21
| | | | | | This keeps Clang consistent with backend naming conventions. llvm-svn: 209579
* ARM64: initial clang support commit.Tim Northover2014-03-291-4/+98
| | | | | | | | | | | This adds Clang support for the ARM64 backend. There are definitely still some rough edges, so please bring up any issues you see with this patch. As with the LLVM commit though, we think it'll be more useful for merging with AArch64 from within the tree. llvm-svn: 205100
* Fix test on release builds.Tim Northover2013-07-161-2/+1
| | | | | | | | Unfortunately I don't think there's a good way to validate branch targets on release builds. Fortunately it's a minor part of this test (and based on generic code) so I don't mind dropping it. llvm-svn: 186398
* ARM: implement low-level intrinsics for the atomic exclusive operations.Tim Northover2013-07-161-0/+113
This adds three overloaded intrinsics to Clang: T __builtin_arm_ldrex(const volatile T *addr) int __builtin_arm_strex(T val, volatile T *addr) void __builtin_arm_clrex() The intent is that these do what users would expect when given most sensible types. Currently, "sensible" translates to ints, floats and pointers. llvm-svn: 186394
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