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* [Headers] Fix compatibility between arm_acle.h and intrin.hEli Friedman2019-10-291-0/+2
| | | | | | Make sure they don't both define __nop. Differential Revision: https://reviews.llvm.org/D69012
* [ARM][AArch64] Implement __cls, __clsl and __clsll intrinsics from ACLEvhscampos2019-10-281-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Writing support for three ACLE functions: unsigned int __cls(uint32_t x) unsigned int __clsl(unsigned long x) unsigned int __clsll(uint64_t x) CLS stands for "Count number of leading sign bits". In AArch64, these two intrinsics can be translated into the 'cls' instruction directly. In AArch32, on the other hand, this functionality is achieved by implementing it in terms of clz (count number of leading zeros). Reviewers: compnerd Reviewed By: compnerd Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D69250
* [ARM][AArch64] Implement __arm_rsrf, __arm_rsrf64, __arm_wsrf & __arm_wsrf64vhscampos2019-10-281-0/+4
| | | | | | | | | | | | | | | | | Summary: Adding support for ACLE intrinsics. Patch by Michael Platings. Reviewers: chill, t.p.northover, efriedma Reviewed By: chill Subscribers: kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D69297
* [AArch64] Add support for Transactional Memory Extension (TME)Momchil Velikov2019-07-311-1/+23
| | | | | | | | | | | | | | | | | | | | | | | | | Re-commit r366322 after some fixes TME is a future architecture technology, documented in https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools https://developer.arm.com/docs/ddi0601/a More about the future architectures: https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/new-technologies-for-the-arm-a-profile-architecture This patch adds support for the TME instructions TSTART, TTEST, TCOMMIT, and TCANCEL and the target feature/arch extension "tme". It also implements TME builtin functions, defined in ACLE Q2 2019 (https://developer.arm.com/docs/101028/latest) Differential Revision: https://reviews.llvm.org/D64416 Patch by Javed Absar and Momchil Velikov llvm-svn: 367428
* Revert [AArch64] Add support for Transactional Memory Extension (TME)Momchil Velikov2019-07-171-23/+1
| | | | | | This reverts r366322 (git commit 4b8da3a503e434ddbc08ecf66582475765f449bc) llvm-svn: 366355
* [AArch64] Add support for Transactional Memory Extension (TME)Momchil Velikov2019-07-171-1/+23
| | | | | | | | | | | | | | | | | | | | | | | TME is a future architecture technology, documented in https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools https://developer.arm.com/docs/ddi0601/a More about the future architectures: https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/new-technologies-for-the-arm-a-profile-architecture This patch adds support for the TME instructions TSTART, TTEST, TCOMMIT, and TCANCEL and the target feature/arch extension "tme". It also implements TME builtin functions, defined in ACLE Q2 2019 (https://developer.arm.com/docs/101028/latest) Patch by Javed Absar and Momchil Velikov Differential Revision: https://reviews.llvm.org/D64416 llvm-svn: 366322
* [AArch64] Implement __jcvt intrinsic from Armv8.3-AKyrylo Tkachov2019-07-161-0/+8
| | | | | | | | | | | | | | | | The jcvt intrinsic defined in ACLE [1] is available when ARM_FEATURE_JCVT is defined. This change introduces the AArch64 intrinsic, wires it up to the instruction and a new clang builtin function. The __ARM_FEATURE_JCVT macro is now defined when an Armv8.3-A or higher target is used. I've implemented the target detection logic in Clang so that this feature is enabled for architectures from armv8.3-a onwards (so -march=armv8.4-a also enables this, for example). make check-all didn't show any new failures. [1] https://developer.arm.com/docs/101028/latest/data-processing-intrinsics Differential Revision: https://reviews.llvm.org/D64495 llvm-svn: 366197
* [AArch64] Add support for MTE intrinsicsJaved Absar2019-04-261-0/+10
| | | | | | | | | | | | This provides intrinsics support for Memory Tagging Extension (MTE), which was introduced with the Armv8.5-a architecture. These intrinsics are available when __ARM_FEATURE_MEMORY_TAGGING is defined. Each intrinsic is described in detail in the ACLE Q1 2019 documentation: https://developer.arm.com/docs/101028/latest Reviewed By: Tim Nortover, David Spickett Differential Revision: https://reviews.llvm.org/D60485 llvm-svn: 359348
* Move the builtin headers to use the new license file header.Chandler Carruth2019-04-081-17/+3
| | | | | | | | | | | | | | | | | | Summary: These all had somewhat custom file headers with different text from the ones I searched for previously, and so I missed them. Thanks to Hal and Kristina and others who prompted me to fix this, and sorry it took so long. Reviewers: hfinkel Subscribers: mcrosier, javed.absar, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D60406 llvm-svn: 357941
* [ARM] ACLE Chapter 9 intrinsicsSam Parker2017-05-041-2/+316
| | | | | | | | | | Implemented the remaining integer data processing intrinsics from the ARM ACLE v2.1 spec, such as parallel arithemtic and DSP style multiplications. Differential Revision: https://reviews.llvm.org/D32282 llvm-svn: 302131
* Update functions in clang supplied headers to use the compiler reservedEric Christopher2016-02-121-66/+70
| | | | | | namespace for arguments. llvm-svn: 260647
* [ARM,AArch64] Fix __rev16l and __rev16ll intrinsicsOliver Stannard2015-11-161-6/+10
| | | | | | | | | | | | | | | | | | | | These two intrinsics are defined in arm_acle.h. __rev16l needs to rotate by 16 bits, bit it was actually rotating by 2 bits. For AArch64, where long is 64 bits, this would still be wrong. __rev16ll was incorrect, it reversed the bytes in each 32-bit word, rather than each 16-bit halfword. The correct implementation is to apply __rev16 to the top and bottom words of the 64-bit value. For AArch32 targets, these get compiled down to the hardware rev16 instruction at -O1 and above. For AArch64 targets, the 64-bit ones get compiled to two 32-bit rev16 instructions, because there is not currently a pattern for the 64-bit rev16 instruction. Differential Revision: http://reviews.llvm.org/D14609 llvm-svn: 253211
* This patch implements clang support for the ACLE special register intrinsicsLuke Cheeseman2015-06-151-0/+8
| | | | | | | | | | | | | in section 10.1, __arm_{w,r}sr{,p,64}. This includes arm_acle.h definitions with builtins and codegen to support these, the intrinsics are implemented by generating read/write_register calls which get appropriately lowered in the backend based on the register string provided. SemaChecking is also implemented to fault invalid parameters. Differential Revision: http://reviews.llvm.org/D9697 llvm-svn: 239737
* Headers: Don't use attribute keywords which aren't reservedDavid Majnemer2015-02-041-34/+34
| | | | | | Instead of using 'unavailable', use '__unavailable__' llvm-svn: 228087
* arm_acle: Fix error in ROR implementationYi Kong2014-08-281-4/+4
| | | | | | | | The logic in calculating the rotate amount was flawed. Thanks Pasi Parviainen for pointing out! llvm-svn: 216669
* arm_acle: Implement data processing intrinsicsYi Kong2014-08-281-0/+74
| | | | | | | | | | | | | | | | | Summary: ACLE 2.0 section 9.2 defines the following "miscellaneous data processing intrinsics": `__clz`, `__cls`, `__ror`, `__rev`, `__rev16`, `__revsh` and `__rbit`. `__clz` has already been implemented in the arm_acle.h header file. The rest are not supported yet. This patch completes ACLE data processing intrinsics. Reviewers: t.p.northover, rengolin Reviewed By: rengolin Subscribers: aemerson, mroth, llvm-commits Differential Revision: http://reviews.llvm.org/D4983 llvm-svn: 216658
* arm_acle: Add mappings for dbg intrinsicYi Kong2014-08-261-0/+4
| | | | | | This completes all ACLE hint intrinsics. llvm-svn: 216453
* arm_acle: Implement swap intrinsicYi Kong2014-08-261-0/+8
| | | | | | | Insert the LDREX/STREX instruction sequence specified in ARM ACLE 2.0, as SWP instruction is deprecated since ARMv6. llvm-svn: 216446
* arm_acle.h: Small cleanupYi Kong2014-08-151-4/+0
| | | | | | | | | Since __SIZEOF_LONG_LONG__ is always defined as 8 on ARM targets, there's no point in checking this. NFC. Patch by Moritz Roth. llvm-svn: 215697
* ARM: Add mappings for ACLE prefetch intrinsicsYi Kong2014-08-131-0/+23
| | | | | | | Implement __pld, __pldx, __pli and __plix builtin intrinsics as specified in ARM ACLE 2.0. llvm-svn: 215599
* ARM: Add ACLE memory barrier intrinsic mappingYi Kong2014-07-171-1/+8
| | | | llvm-svn: 213261
* ARM: Add NOP intrinsic mapping in arm_acle.hYi Kong2014-07-141-2/+8
| | | | llvm-svn: 212950
* Headers: add hint intrinsics to arm_acle.hSaleem Abdulrasool2014-07-121-0/+24
| | | | | | | | This adds the ARM ACLE hint intrinsic wrappers to arm_acle.h. These need to be protected with a !defined(_MSC_VER) since MSVC (and thus clang in compatibility mode) provide these wrappers as proper builtin intrinsics. llvm-svn: 212891
* Improve comments of ARM ACLE header file and testsYi Kong2014-07-121-5/+8
| | | | | | Include section number in ARM ACLE specification for easier navigation. llvm-svn: 212887
* Headers: mark arm_acle.h with extern "C"Saleem Abdulrasool2014-07-081-0/+8
| | | | | | | | | Although the functions are marked as always_inline, the compiler with which they are used may not honour the extended attributes and emit them as functions. In such a case, indicate that they should have extern "C" linkage and should not be mangled in C++ style if used within C++. llvm-svn: 212511
* Add the __qdbl intrinsic to the arm_acle.h headerRenato Golin2014-07-031-0/+5
| | | | | | Patch by: Moritz Roth llvm-svn: 212264
* Introduce arm_acle.h supporting existing LLVM builtin intrinsicsYi Kong2014-06-271-0/+138
Summary: This patch introduces ACLE header file, implementing extensions that can be directly mapped to existing Clang intrinsics. It implements for both AArch32 and AArch64. Reviewers: t.p.northover, compnerd, rengolin Reviewed By: compnerd, rengolin Subscribers: rnk, echristo, compnerd, aemerson, mroth, cfe-commits Differential Revision: http://reviews.llvm.org/D4296 llvm-svn: 211962
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