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* [X86] Support -march=tigerlakePengfei Wang2019-08-121-0/+10
| | | | | | | | | | | | Support -march=tigerlake for x86. Compare with Icelake Client, It include 4 more new features ,they are avx512vp2intersect, movdiri, movdir64b, shstk. Patch by Xiang Zhang (xiangzhangllvm) Differential Revision: https://reviews.llvm.org/D65840 llvm-svn: 368543
* Add SVE opaque built-in typesRichard Sandiford2019-08-091-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the SVE built-in types defined by the Procedure Call Standard for the Arm Architecture: https://developer.arm.com/docs/100986/0000 It handles the types in all relevant places that deal with built-in types. At the moment, some of these places bail out with an error, including: (1) trying to generate LLVM IR for the types (2) trying to generate debug info for the types (3) trying to mangle the types using the Microsoft C++ ABI (4) trying to @encode the types in Objective C (1) and (2) are fixed by follow-on patches but (unlike this patch) they deal mostly with target-specific LLVM details, so seemed like a logically separate change. There is currently no spec for (3) and (4), so reporting an error seems like the correct behaviour for now. The intention is that the types will become sizeless types: http://lists.llvm.org/pipermail/cfe-dev/2019-June/062523.html The main purpose of the sizeless type extension is to diagnose impossible or dangerous uses of the types, such as any that would require sizeof to have a meaningful defined value. Until then, the patch sets the alignments of the types to the values specified in the link above. It also sets the sizes of the types to zero, which is chosen to be consistently wrong and shouldn't affect correctly-written code (i.e. code that would compile even with the sizeless type extension). The patch adds the common subset of functionality needed to test the sizeless type extension on the one hand and to provide SVE intrinsic functions on the other. After this patch, the two pieces of work are essentially independent. The patch is based on one by Graham Hunter: https://reviews.llvm.org/D59245 Differential Revision: https://reviews.llvm.org/D62960 llvm-svn: 368413
* [ARM] Set default alignment to 64bitsDiogo N. Sampaio2019-08-081-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Summary: The maximum alignment used by ARM arch is 64bits, not 128. This could cause overaligned memory access for 128 bit neon vector that have unpredictable behaviour. This fixes: https://bugs.llvm.org/show_bug.cgi?id=42668 Reviewers: ostannard, dmgreen, srhines, danalbert, pirama, peter.smith Reviewed By: pirama, peter.smith Subscribers: phosek, thegameg, thakis, llvm-commits, carwil, peter.smith, javed.absar, kristof.beyls, cfe-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D65000 llvm-svn: 368288
* [AArch64] Add support for Transactional Memory Extension (TME)Momchil Velikov2019-07-312-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | Re-commit r366322 after some fixes TME is a future architecture technology, documented in https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools https://developer.arm.com/docs/ddi0601/a More about the future architectures: https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/new-technologies-for-the-arm-a-profile-architecture This patch adds support for the TME instructions TSTART, TTEST, TCOMMIT, and TCANCEL and the target feature/arch extension "tme". It also implements TME builtin functions, defined in ACLE Q2 2019 (https://developer.arm.com/docs/101028/latest) Differential Revision: https://reviews.llvm.org/D64416 Patch by Javed Absar and Momchil Velikov llvm-svn: 367428
* [RISCV] Support 'f' Inline Assembly ConstraintSam Elliott2019-07-311-0/+4
| | | | | | | | | | | | | | | | | | | | | | | Summary: This adds the 'f' inline assembly constraint, as supported by GCC. An 'f'-constrained operand is passed in a floating point register. Exactly which kind of floating-point register (32-bit or 64-bit) is decided based on the operand type and the available standard extensions (-f and -d, respectively). This patch adds support in both the clang frontend, and LLVM itself. Reviewers: asb, lewis-revill Reviewed By: asb Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D65500 llvm-svn: 367403
* [RISCV] Add support for floating point registers in inlineasmSimon Cook2019-07-311-9/+24
| | | | | | | | | This adds support for parsing/emitting in IR the floating-point RISC-V registers in inline assembly clobber lists. Differential Revision: https://reviews.llvm.org/D64737 llvm-svn: 367399
* [Driver] Define _FILE_OFFSET_BITS=64 on SolarisRainer Orth2019-07-301-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | make check-all currently fails on x86_64-pc-solaris2.11 when building with GCC 9: Undefined first referenced symbol in file _ZN11__sanitizer14internal_lseekEimi SANITIZER_TEST_OBJECTS.sanitizer_libc_test.cc.i386.o _ZN11__sanitizer23MapWritableFileToMemoryEPvmim SANITIZER_TEST_OBJECTS.sanitizer_libc_test.cc.i386.o ld: fatal: symbol referencing errors clang-9: error: linker command failed with exit code 1 (use -v to see invocation) make[3]: *** [projects/compiler-rt/lib/sanitizer_common/tests/CMakeFiles/TSanitizer-i386-Test.dir/build.make:92: projects/compiler-rt/lib/sanitizer_common/tests/Sanitizer-i386-Test] Error 1 While e.g. __sanitizer::internal_lseek is defined in sanitizer_solaris.cc, g++ 9 predefines _FILE_OFFSET_BITS=64 while clang++ currently does not. This patch resolves this inconsistency by following the gcc lead, which allows make check-all to finish successfully. There's one caveat: gcc defines _LARGEFILE_SOURCE and _LARGEFILE64_SOURCE for C++ only, while clang has long been doing it for all languages. I'd like to keep it this way because those macros do is to make declarations of fseek/ftello (_LARGEFILE_SOURCE) resp. the 64-bit versions of largefile functions (*64 with _LARGEFILE64_SOURCE) visible additionally. However, _FILE_OFFSET_BITS=64 changes all affected functions to be largefile-aware. I'd like to restrict this to C++, just like gcc does. To avoid a similar inconsistence with host compilers that don't predefine _FILE_OFFSET_BITS=64 (e.g. clang < 9, gcc < 9), this needs a compantion patch https://reviews.llvm.org/D64483. Tested on x86_64-pc-solaris2.11. Differential Revision: https://reviews.llvm.org/D64482 llvm-svn: 367305
* [AArch64] Disable __ARM_FEATURE_SVE without ACLE.Sander de Smalen2019-07-301-3/+0
| | | | | | | | | | | | | | | | | The Arm C Language Extensions for SVE document specifies that __ARM_FEATURE_SVE should be set when the compiler supports SVE and implements all the extensions described in the document. This is currently not yet the case, so the feature should be disabled until the compiler can provide all the extensions as described. Reviewers: c-rhodes, rengolin, rovka, ktkachov Reviewed By: rengolin Differential Revision: https://reviews.llvm.org/D65404 llvm-svn: 367301
* Revert "[ARM] Set default alignment to 64bits"Petr Hosek2019-07-271-2/+1
| | | | | | | | | | | This reverts commit r367119. This broke several bots: http://lab.llvm.org:8011/builders/clang-atom-d525-fedora-rel/builds/26891/steps/ninja%20check%201/logs/FAIL%3A%20Clang%3A%3Aexception-alignment.cpp http://green.lab.llvm.org/green/job/clang-stage1-cmake-RA-incremental/245/consoleFull llvm-svn: 367166
* [ARM] Set default alignment to 64bitsSimi Pallipurath2019-07-261-1/+2
| | | | | | | | | | | | | | | | | | The maximum alignment used by ARM arch is 64bits, not 128. This could cause overaligned memory access for 128 bit neon vector that have unpredictable behaviour. This fixes: https://bugs.llvm.org/show_bug.cgi?id=42668 Patch by: Diogo Sampaio(diogo.sampaio@arm.com) Differential Revision: https://reviews.llvm.org/D65000 Change-Id: I5a62b766491f15dd51e4cfe6625929db897f67e3 llvm-svn: 367119
* Remove CallingConvMethodTypeErich Keane2019-07-252-4/+4
| | | | | | | | | This seems to be an old vestage of a previous implementation of getting the default calling convention, and everything is now using CXXABI/ASTContext's getDefaultCallingConvention. Remove it, since it isn't doing anything. llvm-svn: 367039
* Test commit. NFC.Sjoerd Meijer2019-07-241-1/+1
| | | | | | | Removed 2 trailing whitespaces in 2 files that used to be in different repos to test my new github monorepo workflow. llvm-svn: 366904
* [SVE][Inline-Asm] Add support to specify SVE registers in the clobber listSander de Smalen2019-07-241-2/+11
| | | | | | | | | | | | | | Adds the SVE vector and predicate registers to the list of known registers. Patch by Kerry McLaughlin. Reviewers: erichkeane, sdesmalen, rengolin Reviewed By: sdesmalen Differential Revision: https://reviews.llvm.org/D64739 llvm-svn: 366878
* [clang, test] Fix Clang :: Headers/max_align.c on 64-bit SPARCRainer Orth2019-07-231-0/+1
| | | | | | | | | | | | | | | | | | | | | Clang :: Headers/max_align.c currently FAILs on 64-bit SPARC: error: 'error' diagnostics seen but not expected: File /vol/llvm/src/clang/dist/test/Headers/max_align.c Line 12: static_assert failed due to requirement '8 == _Alignof(max_align_t)' "" 1 error generated. This happens because SuitableAlign isn't defined for SPARCv9 unlike SPARCv8 (which uses the default of 64 bits). gcc's sparc/sparc.h has #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64) This patch sets SuitableAlign to match and updates the corresponding testcase. Tested on sparcv9-sun-solaris2.11. Differential Revision: https://reviews.llvm.org/D64487 llvm-svn: 366820
* Disallow most calling convention attributes on PS4Sunil Srivastava2019-07-191-0/+4
| | | | | | | | PS4 now only allows "cdecl", and its equivalent on PS4, "sysv_abi". Differential Revision: https://reviews.llvm.org/D64780 llvm-svn: 366617
* [RISCV] Hard float ABI supportAlex Bradbury2019-07-182-6/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The RISC-V hard float calling convention requires the frontend to: * Detect cases where, once "flattened", a struct can be passed using int+fp or fp+fp registers under the hard float ABI and coerce to the appropriate type(s) * Track usage of GPRs and FPRs in order to gate the above, and to determine when signext/zeroext attributes must be added to integer scalars This patch attempts to do this in compliance with the documented ABI, and uses ABIArgInfo::CoerceAndExpand in order to do this. @rjmccall, as author of that code I've tagged you as reviewer for initial feedback on my usage. Note that a previous version of the ABI indicated that when passing an int+fp struct using a GPR+FPR, the int would need to be sign or zero-extended appropriately. GCC never did this and the ABI was changed, which makes life easier as ABIArgInfo::CoerceAndExpand can't currently handle sign/zero-extension attributes. Re-landed after backing out 366450 due to missed hunks. Differential Revision: https://reviews.llvm.org/D60456 llvm-svn: 366480
* Revert "[RISCV] Hard float ABI support" r366450Alex Bradbury2019-07-182-13/+6
| | | | | | The commit was missing a few hunks. Will fix and recommit. llvm-svn: 366454
* [RISCV] Hard float ABI supportAlex Bradbury2019-07-182-6/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | The RISC-V hard float calling convention requires the frontend to: * Detect cases where, once "flattened", a struct can be passed using int+fp or fp+fp registers under the hard float ABI and coerce to the appropriate type(s) * Track usage of GPRs and FPRs in order to gate the above, and to determine when signext/zeroext attributes must be added to integer scalars This patch attempts to do this in compliance with the documented ABI, and uses ABIArgInfo::CoerceAndExpand in order to do this. @rjmccall, as author of that code I've tagged you as reviewer for initial feedback on my usage. Note that a previous version of the ABI indicated that when passing an int+fp struct using a GPR+FPR, the int would need to be sign or zero-extended appropriately. GCC never did this and the ABI was changed, which makes life easier as ABIArgInfo::CoerceAndExpand can't currently handle sign/zero-extension attributes. Differential Revision: https://reviews.llvm.org/D60456 llvm-svn: 366450
* Revert [AArch64] Add support for Transactional Memory Extension (TME)Momchil Velikov2019-07-172-7/+0
| | | | | | This reverts r366322 (git commit 4b8da3a503e434ddbc08ecf66582475765f449bc) llvm-svn: 366355
* [AArch64] Add support for Transactional Memory Extension (TME)Momchil Velikov2019-07-172-0/+7
| | | | | | | | | | | | | | | | | | | | | | | TME is a future architecture technology, documented in https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools https://developer.arm.com/docs/ddi0601/a More about the future architectures: https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/new-technologies-for-the-arm-a-profile-architecture This patch adds support for the TME instructions TSTART, TTEST, TCOMMIT, and TCANCEL and the target feature/arch extension "tme". It also implements TME builtin functions, defined in ACLE Q2 2019 (https://developer.arm.com/docs/101028/latest) Patch by Javed Absar and Momchil Velikov Differential Revision: https://reviews.llvm.org/D64416 llvm-svn: 366322
* [AArch64] Consistent types and naming for AArch64 target features (NFC)Momchil Velikov2019-07-172-24/+25
| | | | | | | | Differential Revision: https://reviews.llvm.org/D64415 Committed as obvious. llvm-svn: 366315
* [AArch64] Implement __jcvt intrinsic from Armv8.3-AKyrylo Tkachov2019-07-162-0/+43
| | | | | | | | | | | | | | | | The jcvt intrinsic defined in ACLE [1] is available when ARM_FEATURE_JCVT is defined. This change introduces the AArch64 intrinsic, wires it up to the instruction and a new clang builtin function. The __ARM_FEATURE_JCVT macro is now defined when an Armv8.3-A or higher target is used. I've implemented the target detection logic in Clang so that this feature is enabled for architectures from armv8.3-a onwards (so -march=armv8.4-a also enables this, for example). make check-all didn't show any new failures. [1] https://developer.arm.com/docs/101028/latest/data-processing-intrinsics Differential Revision: https://reviews.llvm.org/D64495 llvm-svn: 366197
* [PowerPC] Support -mabi=ieeelongdouble and -mabi=ibmlongdoubleFangrui Song2019-07-151-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc PowerPC supports 3 representations of long double: * -mlong-double-64 long double has the same representation of double but is mangled as `e`. In clang, this is the default on AIX, FreeBSD and Linux musl. * -mlong-double-128 2 possible 128-bit floating point representations: + -mabi=ibmlongdouble IBM extended double format. Mangled as `g` In clang, this is the default on Linux glibc. + -mabi=ieeelongdouble IEEE 754 quadruple-precision format. Mangled as `u9__ieee128` (`U10__float128` before gcc 8.2) This is currently unavailable. This patch adds -mabi=ibmlongdouble and -mabi=ieeelongdouble, and thus makes the IEEE 754 quadruple-precision long double available for languages supported by clang. Reviewed By: hfinkel Differential Revision: https://reviews.llvm.org/D64283 llvm-svn: 366044
* Support __seg_fs and __seg_gs on x86JF Bastien2019-07-141-0/+5
| | | | | | | | | | | | | | | | | | | | | Summary: GCC supports named address spaces macros: https://gcc.gnu.org/onlinedocs/gcc/Named-Address-Spaces.html clang does as well with address spaces: https://clang.llvm.org/docs/LanguageExtensions.html#memory-references-to-specified-segments Add the __seg_fs and __seg_gs macros for compatibility with GCC. <rdar://problem/52944935> Subscribers: jkorous, dexonsmith, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D64676 llvm-svn: 366028
* [SystemZ] Add support for new cpu architecture - arch13Ulrich Weigand2019-07-122-2/+6
| | | | | | | | | | | | | | | | | This patch series adds support for the next-generation arch13 CPU architecture to the SystemZ backend. This includes: - Basic support for the new processor and its features. - Support for low-level builtins mapped to new LLVM intrinsics. - New high-level intrinsics in vecintrin.h. - Indicate support by defining __VEC__ == 10303. Note: No currently available Z system supports the arch13 architecture. Once new systems become available, the official system name will be added as supported -march name. llvm-svn: 365933
* [X86][PowerPC] Support -mlong-double-128Fangrui Song2019-07-122-2/+6
| | | | | | | | | | | | | | | This patch makes the driver option -mlong-double-128 available for X86 and PowerPC. The CC1 option -mlong-double-128 is available on all targets for users to test on unsupported targets. On PowerPC, -mlong-double-128 uses the IBM extended double format because we don't support -mabi=ieeelongdouble yet (D64283). Reviewed By: rnk Differential Revision: https://reviews.llvm.org/D64277 llvm-svn: 365866
* [HIP] Add GPU arch gfx1010, gfx1011, and gfx1012Yaxun Liu2019-07-111-0/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D64364 llvm-svn: 365799
* De-templatize non-dependent VS macro logic, NFCReid Kleckner2019-07-096-73/+85
| | | | | | | These macro definitions don't depend on the template parameter, so they don't need to be part of the template. Move them to a .cpp file. llvm-svn: 365556
* [AMDGPU] gfx908 clang targetStanislav Mekhanoshin2019-07-092-0/+7
| | | | | | Differential Revision: https://reviews.llvm.org/D64430 llvm-svn: 365528
* [ItaniumMangle] Refactor long double/__float128 mangling and fix the mangled ↵Fangrui Song2019-07-093-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | code In gcc PowerPC, long double has 3 mangling schemes: -mlong-double-64: `e` -mlong-double-128 -mabi=ibmlongdouble: `g` -mlong-double-128 -mabi=ieeelongdouble: `u9__ieee128` (gcc <= 8.1: `U10__float128`) The current useFloat128ManglingForLongDouble() bisection is not suitable when we support -mlong-double-128 in clang (D64277). Replace useFloat128ManglingForLongDouble() with getLongDoubleMangling() and getFloat128Mangling() to allow 3 mangling schemes. I also deleted the `getTriple().isOSBinFormatELF()` check (the Darwin support has gone: https://reviews.llvm.org/D50988). For x86, change the mangled code of __float128 from `U10__float128` to `g`. `U10__float128` was wrongly copied from PowerPC. The test will be added to `test/CodeGen/x86-long-double.cpp` in D64277. Reviewed By: erichkeane Differential Revision: https://reviews.llvm.org/D64276 llvm-svn: 365480
* [X86][PPC] Support -mlong-double-64Fangrui Song2019-07-091-20/+7
| | | | | | | | | | | | | | | | | | | | | | | | -mlong-double-64 is supported on some ports of gcc (i386, x86_64, and ppc{32,64}). On many other targets, there will be an error: error: unrecognized command line option '-mlong-double-64' This patch makes the driver option -mlong-double-64 available for x86 and ppc. The CC1 option -mlong-double-64 is available on all targets for users to test on unsupported targets. LongDoubleSize is added as a VALUE_LANGOPT so that the option can be shared with -mlong-double-128 when we support it in clang. Also, make powerpc*-linux-musl default to use 64-bit long double. It is currently the only supported ABI on musl and is also how people configure powerpc*-linux-musl-gcc. Reviewed By: rnk Differential Revision: https://reviews.llvm.org/D64067 llvm-svn: 365412
* [RISCV] Specify registers used for exception handlingAlex Bradbury2019-07-081-0/+9
| | | | | | | | | Implements the handling of __builtin_eh_return_regno(). Differential Revision: https://reviews.llvm.org/D63417 Patch by Edward Jones. llvm-svn: 365305
* [PowerPC] Support constraint code "ww"Fangrui Song2019-07-041-1/+2
| | | | | | | | | | | | | Summary: "ww" and "ws" are both constraint codes for VSX vector registers that hold scalar double data. "ww" is preferred for float while "ws" is preferred for double. Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D64119 llvm-svn: 365106
* Fix build failure due to missing breakYaxun Liu2019-06-261-0/+2
| | | | llvm-svn: 364380
* [ARM] Support inline assembler constraints for MVE.Simon Tatham2019-06-251-0/+11
| | | | | | | | | | | | | | | | | | | | | "To" selects an odd-numbered GPR, and "Te" an even one. There are some 8.1-M instructions that have one too few bits in their register fields and require registers of particular parity, without necessarily using a consecutive even/odd pair. Also, the constraint letter "t" should select an MVE q-register, when MVE is present. This didn't need any source changes, but some extra tests have been added. Reviewers: dmgreen, samparker, SjoerdMeijer Subscribers: javed.absar, eraman, kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D60709 llvm-svn: 364331
* AMDGPU: Fix target builtins for gfx10Matt Arsenault2019-06-221-0/+2
| | | | | | This wasn't setting some of the features from older generations. llvm-svn: 364123
* [RISCV] Mark TLS as supportedLewis Revill2019-06-191-1/+0
| | | | | | | | Inform Clang that TLS is implemented by LLVM for RISC-V Differential Revision: https://reviews.llvm.org/D57055 llvm-svn: 363776
* Clang :: Sema/wchar.c has long been failing on Solaris:Rainer Orth2019-06-171-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | error: 'error' diagnostics expected but not seen: File /vol/llvm/src/clang/local/test/Sema/wchar.c Line 22: initializing wide char array with non-wide string literal error: 'error' diagnostics seen but not expected: File /vol/llvm/src/clang/local/test/Sema/wchar.c Line 20: array initializer must be an initializer list File /vol/llvm/src/clang/local/test/Sema/wchar.c Line 22: array initializer must be an initializer list It turns out the definition is wrong, as can be seen in GCC's gcc/config/sol2.h: /* wchar_t is called differently in <wchar.h> for 32 and 64-bit compilations. This is called for by SCD 2.4.1, p. 6-83, Figure 6-65 (32-bit) and p. 6P-10, Figure 6.38 (64-bit). */ #undef WCHAR_TYPE #define WCHAR_TYPE (TARGET_64BIT ? "int" : "long int") The following patch implements this, and at the same time corrects the wint_t definition which is the same: /* Same for wint_t. See SCD 2.4.1, p. 6-83, Figure 6-66 (32-bit). There's no corresponding 64-bit definition, but this is what Solaris 8 <iso/wchar_iso.h> uses. */ #undef WINT_TYPE #define WINT_TYPE (TARGET_64BIT ? "int" : "long int") Clang :: Preprocessor/wchar_t.c and Clang :: Sema/format-strings.c need to be adjusted to account for that. Tested on i386-pc-solaris2.11, x86_64-pc-solaris2.11, and x86_64-pc-linux-gnu. Differential Revision: https://reviews.llvm.org/D62944 llvm-svn: 363612
* [Targets] Move soft-float-abi filtering to `initFeatureMap`George Burgess IV2019-06-142-14/+25
| | | | | | | | | | | | | | | | | | ARM has a special target feature called soft-float-abi. This feature is special, since we get it passed to us explicitly in the frontend, but filter it out before it can land in any target feature strings in LLVM IR. __attribute__((target(""))) doesn't quite filter these features out properly, so today, we get warnings about soft-float-abi being an unknown feature from the backend. This CL has us filter soft-float-abi out at a slightly different point, so we don't end up passing these invalid features to the backend. Differential Revision: https://reviews.llvm.org/D61750 llvm-svn: 363346
* [AMDGPU] gfx1011/gfx1012 clang supportStanislav Mekhanoshin2019-06-141-0/+7
| | | | | | Differential Revision: https://reviews.llvm.org/D63308 llvm-svn: 363345
* [RISCV] Add inline asm constraints I, J & K for RISC-VLewis Revill2019-06-112-3/+21
| | | | | | | | | | | | | | | | This allows the constraints I, J & K to be used in inline asm for RISC-V, with the following semantics (equivalent to GCC): I: Any 12-bit signed immediate. J: Integer zero only. K: Any 5-bit unsigned immediate. See the GCC definitions here: https://gcc.gnu.org/onlinedocs/gccint/Machine-Constraints.html Differential Revision: https://reviews.llvm.org/D54091 llvm-svn: 363055
* [X86] Attempt to make the Intel core CPU inheritance a little more readable ↵Craig Topper2019-06-101-24/+27
| | | | | | | | | | | | and maintainable The recently added cooperlake CPU has made our already ugly switch statement even worse. There's a CPU exclusion list around the bf16 feature in the cooper lake block. I worry that we'll have to keep adding new CPUs to that until bf16 intercepts a client space CPU. We have several other exclusion lists in other parts of the switch due to skylakeserver, cascadelake, and cooperlake not having sgx. Another for cannonlake not having clwb but having all other features from skx. This removes all these special ifs at the cost of some duplication of features and a goto. I've copied all of the skx features into either cannonlake or icelakeclient(for clwb). And pulled sklyakeserver, cascadelake, and cooperlake out of the main inheritance chain into their own chain. At the end of skylakeserver we merge back into the main chain at skylakeclient but below sgx. I think this is at least easier to follow. Differential Revision: https://reviews.llvm.org/D63018 llvm-svn: 362965
* [ARM] Add ACLE feature macros for MVE.David Green2019-06-071-0/+1
| | | | | | Fixup uninitialised variable. llvm-svn: 362814
* [ARM] Add ACLE feature macros for MVESjoerd Meijer2019-06-072-0/+30
| | | | | | | | | | | | | | | If MVE is present at all, then the macro __ARM_FEATURE_MVE is defined to a value which has bit 0 set for integer MVE, and bit 1 set for floating-point MVE. (Floating-point MVE implies integer MVE, so if this macro is defined at all then it will be set to 1 or 3, never 2.) Patch mostly by Simon Tatham Differential Revision: https://reviews.llvm.org/D60710 llvm-svn: 362806
* [ARM] Fix bugs introduced by the fp64/d32 rework.Simon Tatham2019-06-071-4/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change D60691 caused some knock-on failures that weren't caught by the existing tests. Firstly, selecting a CPU that should have had a restricted FPU (e.g. `-mcpu=cortex-m4`, which should have 16 d-regs and no double precision) could give the unrestricted version, because `ARM::getFPUFeatures` returned a list of features including subtracted ones (here `-fp64`,`-d32`), but `ARMTargetInfo::initFeatureMap` threw away all the ones that didn't start with `+`. Secondly, the preprocessor macros didn't reliably match the actual compilation settings: for example, `-mfpu=softvfp` could still set `__ARM_FP` as if hardware FP was available, because the list of features on the cc1 command line would include things like `+vfp4`,`-vfp4d16` and clang didn't realise that one of those cancelled out the other. I've fixed both of these issues by rewriting `ARM::getFPUFeatures` so that it returns a list that enables every FP-related feature compatible with the selected FPU and disables every feature not compatible, which is more verbose but means clang doesn't have to understand the dependency relationships between the backend features. Meanwhile, `ARMTargetInfo::handleTargetFeatures` is testing for all the various forms of the FP feature names, so that it won't miss cases where it should have set `HW_FP` to feed into feature test macros. That in turn caused an ordering problem when handling `-mcpu=foo+bar` together with `-mfpu=something_that_turns_off_bar`. To fix that, I've arranged that the `+bar` suffixes on the end of `-mcpu` and `-march` cause feature names to be put into a separate vector which is concatenated after the output of `getFPUFeatures`. Another side effect of all this is to fix a bug where `clang -target armv8-eabi` by itself would fail to set `__ARM_FEATURE_FMA`, even though `armv8` (aka Arm v8-A) implies FP-Armv8 which has FMA. That was because `HW_FP` was being set to a value including only the `FPARMV8` bit, but that feature test macro was testing only the `VFP4FPU` bit. Now `HW_FP` ends up with all the bits set, so it gives the right answer. Changes to tests included in this patch: * `arm-target-features.c`: I had to change basically all the expected results. (The Cortex-M4 test in there should function as a regression test for the accidental double-precision bug.) * `arm-mfpu.c`, `armv8.1m.main.c`: switched to using `CHECK-DAG` everywhere so that those tests are no longer sensitive to the order of cc1 feature options on the command line. * `arm-acle-6.5.c`: been updated to expect the right answer to that FMA test. * `Preprocessor/arm-target-features.c`: added a regression test for the `mfpu=softvfp` issue. Reviewers: SjoerdMeijer, dmgreen, ostannard, samparker, JamesNagurne Reviewed By: ostannard Subscribers: srhines, javed.absar, kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D62998 llvm-svn: 362791
* [X86] -march=cooperlake (clang)Pengfei Wang2019-06-071-3/+11
| | | | | | | | | | Support intel -march=cooperlake in clang Patch by Shengchen Kan (skan) Differential Revision: https://reviews.llvm.org/D62835 llvm-svn: 362781
* [X86] Add ENQCMD instructionsPengfei Wang2019-06-062-0/+7
| | | | | | | | | | | | For more details about these instructions, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference. Patch by Tianqing Wang (tianqing) Differential Revision: https://reviews.llvm.org/D62282 llvm-svn: 362685
* [X86] Add VP2INTERSECT instructionsPengfei Wang2019-05-312-1/+8
| | | | | | | | | | Support intel AVX512 VP2INTERSECT instructions in clang Patch by Xiang Zhang (xiangzhangllvm) Differential Revision: https://reviews.llvm.org/D62367 llvm-svn: 362196
* [ARM] Add CLI support for Armv8.1-M and MVESjoerd Meijer2019-05-301-0/+2
| | | | | | | | | | | | Given the existing infrastructure in LLVM side for +fp and +fp.dp, this is more or less trivial, needing only one tiny source change and a couple of tests. Patch by Simon Tatham. Differential Revision: https://reviews.llvm.org/D60699 llvm-svn: 362096
* [ARM] Replace fp-only-sp and d16 with fp64 and d32.Simon Tatham2019-05-281-10/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Those two subtarget features were awkward because their semantics are reversed: each one indicates the _lack_ of support for something in the architecture, rather than the presence. As a consequence, you don't get the behavior you want if you combine two sets of feature bits. Each SubtargetFeature for an FP architecture version now comes in four versions, one for each combination of those options. So you can still say (for example) '+vfp2' in a feature string and it will mean what it's always meant, but there's a new string '+vfp2d16sp' meaning the version without those extra options. A lot of this change is just mechanically replacing positive checks for the old features with negative checks for the new ones. But one more interesting change is that I've rearranged getFPUFeatures() so that the main FPU feature is appended to the output list *before* rather than after the features derived from the Restriction field, so that -fp64 and -d32 can override defaults added by the main feature. Reviewers: dmgreen, samparker, SjoerdMeijer Subscribers: srhines, javed.absar, eraman, kristof.beyls, hiraditya, zzheng, Petar.Avramovic, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D60691 llvm-svn: 361845
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