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path: root/clang/lib/Basic/Targets/Mips.h
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* [mips] Add `octeon+` to the list of CPUs accepted by the driverSimon Atanasyan2019-11-071-0/+2
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* [Headers][mips] Add `__attribute__((__mode__(__unwind_word__)))` to the ↵Simon Atanasyan2019-02-131-0/+2
| | | | | | | | | | | | | | | | | | _Unwind_Word / _Unwind_SWord definitions The rationale of this change is to fix _Unwind_Word / _Unwind_SWord definitions for MIPS N32 ABI. This ABI uses 32-bit pointers, but _Unwind_Word and _Unwind_SWord types are eight bytes long. # The __attribute__((__mode__(__unwind_word__))) is added to the type definitions. It makes them equal to the corresponding definitions used by GCC and allows to override types using `getUnwindWordWidth` function. # The `getUnwindWordWidth` virtual function override in the `MipsTargetInfo` class and provides correct type size values. Differential revision: https://reviews.llvm.org/D58165 llvm-svn: 353965
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* Replace getOS() == llvm::Triple::*BSD with isOS*BSD() [NFCI]Michal Gorny2018-12-201-4/+4
| | | | | | | | | | | | Replace multiple comparisons of getOS() value with FreeBSD, NetBSD, OpenBSD and DragonFly with matching isOS*BSD() methods. This should improve the consistency of coding style without changing the behavior. Direct getOS() comparisons were left whenever used in switch or switch- like context. Differential Revision: https://reviews.llvm.org/D55916 llvm-svn: 349752
* [mips] Fix handling of GNUABIN32 environment in a target tripleSimon Atanasyan2018-10-151-1/+6
| | | | | | | | | | | | The `GNUABIN32` environment in a target triple implies using the N32 ABI. This patch adds support for this environment and switches on N32 ABI if necessary. Patch by Patch by YunQiang Su. Differential revision: https://reviews.llvm.org/D51464 llvm-svn: 344570
* [clang][mips] Set __mips_fpr correctly for -mfpxxStefan Maksimovic2018-08-221-5/+9
| | | | | | | | | | | | | | | | | | | | Set __mips_fpr to 0 if o32 ABI is used with either -mfpxx or none of -mfp32, -mfpxx, -mfp64 being specified. Introduce additional checks: -mfpxx is only to be used in conjunction with the o32 ABI. report an error when incompatible options are provided. Formerly no errors were raised when combining n32/n64 ABIs with -mfp32 and -mfpxx. There are other cases when __mips_fpr should be set to 0 that are not covered, ex. using o32 on a mips64 cpu which is valid but not supported in the backend as of yet. Differential Revision: https://reviews.llvm.org/D50557 llvm-svn: 340391
* Use Triple::isMIPS() instead of enumerating all Triples. NFCAlexander Richardson2018-06-251-4/+1
| | | | | | | | Reviewed By: atanasyan Differential Revision: https://reviews.llvm.org/D48549 llvm-svn: 335495
* [RISCV] Enable __int128_t and __uint128_t through clang flagMandeep Singh Grang2018-02-251-1/+3
| | | | | | | | | | | | | | | | Summary: If the flag -fforce-enable-int128 is passed, it will enable support for __int128_t and __uint128_t types. This flag can then be used to build compiler-rt for RISCV32. Reviewers: asb, kito-cheng, apazos, efriedma Reviewed By: asb, efriedma Subscribers: shiva0217, efriedma, jfb, dschuff, sdardis, sbc100, jgravelle-google, aheejin, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, cfe-commits Differential Revision: https://reviews.llvm.org/D43105 llvm-svn: 326045
* [mips] Spectre variant two mitigation for MIPSR2Simon Dardis2018-02-211-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides mitigation for CVE-2017-5715, Spectre variant two, which affects the P5600 and P6600. It provides the option -mindirect-jump=hazard, which instructs the LLVM backend to replace indirect branches with their hazard barrier variants. This option is accepted when targeting MIPS revision two or later. The migitation strategy suggested by MIPS for these processors is to use two hazard barrier instructions. 'jalr.hb' and 'jr.hb' are hazard barrier variants of the 'jalr' and 'jr' instructions respectively. These instructions impede the execution of instruction stream until architecturally defined hazards (changes to the instruction stream, privileged registers which may affect execution) are cleared. These instructions in MIPS' designs are not speculated past. These instructions are used with the option -mindirect-jump=hazard when branching indirectly and for indirect function calls. These instructions are defined by the MIPS32R2 ISA, so this mitigation method is not compatible with processors which implement an earlier revision of the MIPS ISA. Implementation note: I've opted to provide this as an -mindirect-jump={hazard,...} style option in case alternative mitigation methods are required for other implementations of the MIPS ISA in future, e.g. retpoline style solutions. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D43487 llvm-svn: 325651
* Add Rest of Targets Support to ValidCPUList (enabling march notes)Erich Keane2018-02-081-0/+1
| | | | | | | | | | | A followup to: https://reviews.llvm.org/D42978 Most of the rest of the Targets were pretty rote, so this patch knocks them all out at once. Differential Revision: https://reviews.llvm.org/D43057 llvm-svn: 324676
* [mips] Introducing option -mabs=[legacy/2008]Petar Jovanovic2017-08-241-3/+9
| | | | | | | | | | | | | | | | | In patch r205628 using abs.[ds] instruction is forced, as they should behave in accordance with flags Has2008 and ABS2008. Unfortunately for revisions prior mips32r6 and mips64r6, abs.[ds] is not generating correct result when working with NaNs. To generate a sequence which always produce a correct result but also to allow user more control on how his code is compiled, option -mabs is added where user can choose legacy or 2008. By default legacy mode is used on revisions prior R6. Mips32r6 and mips64r6 use abs2008 mode by default. Patch by Aleksandar Beserminji Differential Revision: https://reviews.llvm.org/D35982 llvm-svn: 311669
* [mips] Rename getSupportedNanEncoding() to getIEEE754Standard()Petar Jovanovic2017-08-221-2/+2
| | | | | | | | | | | Rename the function getSupportedNanEncoding() to getIEEE754Standard(), since this function will be used for non-nan related features. Patch by Aleksandar Beserminji. Differential Revision: https://reviews.llvm.org/D36824 llvm-svn: 311454
* Revert r310057Stefan Maksimovic2017-08-111-1/+4
| | | | | | | | Bring back changes which r304953 introduced since they were in fact not the cause of failures described in r310057 commit message. llvm-svn: 310702
* Revert r304953 for release 5.0.0Stefan Maksimovic2017-08-041-4/+1
| | | | | | | | | | This is causing failures when compiling clang with -O3 as one of the structures used by clang is passed by value and uses the fastcc calling convention. Faliures manifest for stage2 mips build. llvm-svn: 310057
* Break up Targets.cpp into a header/impl pair per target type[NFCI]Erich Keane2017-07-211-0/+391
Targets.cpp is getting unwieldy, and even minor changes cause the entire thing to cause recompilation for everyone. This patch bites the bullet and breaks it up into a number of files. I tended to keep function definitions in the class declaration unless it caused additional includes to be necessary. In those cases, I pulled it over into the .cpp file. Content is copy/paste for the most part, besides includes/format/etc. Differential Revision: https://reviews.llvm.org/D35701 llvm-svn: 308791
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