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* [Targets] Define __BOOL_DEFINED for Windows targets in C++ modeDavid Majnemer2015-07-151-0/+2
| | | | | | | | | | MSVC 4.2 didn't have bool as a builtin type but MSVC 5.0 does. When they added it, they added a macro (__BOOL_DEFINED) which allows build scripts and the like to know if they should provide their own bool. Clang always supports bool as a builtin type in C++ mode. llvm-svn: 242307
* Add support for armv7-windows-gnu targets to the clang front end.Yaron Keren2015-07-151-0/+43
| | | | | | | | | http://reviews.llvm.org/D11071 Patch by Martell Malone Reviewed by Reid Kleckner llvm-svn: 242292
* Add a "maximum TLS alignment" characteristic to the target info, so itPaul Robinson2015-07-141-0/+2
| | | | | | | | | | can be different from the normal variable maximum. Add an error diagnostic for when TLS variables exceed maximum TLS alignment. Currenty only PS4 sets an explicit maximum TLS alignment. Patch by Charles Li! llvm-svn: 242198
* Fix a couple of typos: specifc->specific.Eric Christopher2015-07-101-1/+1
| | | | llvm-svn: 241924
* Add missing builtins to altivec.h for ABI compliance (vol. 3)Nemanja Ivanovic2015-07-101-2/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch corresponds to review: http://reviews.llvm.org/D10972 Fix for the handling of dependent features that are enabled by default on some CPU's (such as -mvsx, -mpower8-vector). Also provides a number of new interfaces or fixes existing ones in altivec.h. Changed signatures to conform to ABI: vector short vec_perm(vector signed short, vector signed short, vector unsigned char) vector int vec_perm(vector signed int, vector signed int, vector unsigned char) vector long long vec_perm(vector signed long long, vector signed long long, vector unsigned char) vector signed char vec_sld(vector signed char, vector signed char, const int) vector unsigned char vec_sld(vector unsigned char, vector unsigned char, const int) vector bool char vec_sld(vector bool char, vector bool char, const int) vector unsigned short vec_sld(vector unsigned short, vector unsigned short, const int) vector signed short vec_sld(vector signed short, vector signed short, const int) vector signed int vec_sld(vector signed int, vector signed int, const int) vector unsigned int vec_sld(vector unsigned int, vector unsigned int, const int) vector float vec_sld(vector float, vector float, const int) vector signed char vec_splat(vector signed char, const int) vector unsigned char vec_splat(vector unsigned char, const int) vector bool char vec_splat(vector bool char, const int) vector signed short vec_splat(vector signed short, const int) vector unsigned short vec_splat(vector unsigned short, const int) vector bool short vec_splat(vector bool short, const int) vector pixel vec_splat(vector pixel, const int) vector signed int vec_splat(vector signed int, const int) vector unsigned int vec_splat(vector unsigned int, const int) vector bool int vec_splat(vector bool int, const int) vector float vec_splat(vector float, const int) Added a VSX path to: vector float vec_round(vector float) Added interfaces: vector signed char vec_eqv(vector signed char, vector signed char) vector signed char vec_eqv(vector bool char, vector signed char) vector signed char vec_eqv(vector signed char, vector bool char) vector unsigned char vec_eqv(vector unsigned char, vector unsigned char) vector unsigned char vec_eqv(vector bool char, vector unsigned char) vector unsigned char vec_eqv(vector unsigned char, vector bool char) vector signed short vec_eqv(vector signed short, vector signed short) vector signed short vec_eqv(vector bool short, vector signed short) vector signed short vec_eqv(vector signed short, vector bool short) vector unsigned short vec_eqv(vector unsigned short, vector unsigned short) vector unsigned short vec_eqv(vector bool short, vector unsigned short) vector unsigned short vec_eqv(vector unsigned short, vector bool short) vector signed int vec_eqv(vector signed int, vector signed int) vector signed int vec_eqv(vector bool int, vector signed int) vector signed int vec_eqv(vector signed int, vector bool int) vector unsigned int vec_eqv(vector unsigned int, vector unsigned int) vector unsigned int vec_eqv(vector bool int, vector unsigned int) vector unsigned int vec_eqv(vector unsigned int, vector bool int) vector signed long long vec_eqv(vector signed long long, vector signed long long) vector signed long long vec_eqv(vector bool long long, vector signed long long) vector signed long long vec_eqv(vector signed long long, vector bool long long) vector unsigned long long vec_eqv(vector unsigned long long, vector unsigned long long) vector unsigned long long vec_eqv(vector bool long long, vector unsigned long long) vector unsigned long long vec_eqv(vector unsigned long long, vector bool long long) vector float vec_eqv(vector float, vector float) vector float vec_eqv(vector bool int, vector float) vector float vec_eqv(vector float, vector bool int) vector double vec_eqv(vector double, vector double) vector double vec_eqv(vector bool long long, vector double) vector double vec_eqv(vector double, vector bool long long) vector bool long long vec_perm(vector bool long long, vector bool long long, vector unsigned char) vector double vec_round(vector double) vector double vec_splat(vector double, const int) vector bool long long vec_splat(vector bool long long, const int) vector signed long long vec_splat(vector signed long long, const int) vector unsigned long long vec_splat(vector unsigned long long, vector bool int vec_sld(vector bool int, vector bool int, const int) vector bool short vec_sld(vector bool short, vector bool short, const int) llvm-svn: 241904
* [MIPS] Add support for direct-to-nacl in ClangPetar Jovanovic2015-07-081-1/+14
| | | | | | | | | | | For Mips direct-to-nacl, the goal is to be close to le32 front-end and use Mips32EL backend. This patch defines new NaClMips32ELTargetInfo and modifies it slightly to be close to le32. It also adds necessary parts, inline with ARM and X86. Differential Revision: http://reviews.llvm.org/D10739 llvm-svn: 241678
* Revert "Refactored ARMTargetInfo in order to use the API of ↵Renato Golin2015-07-031-78/+118
| | | | | | | | llvm/lib/Support/TargetParser.cpp This reverts commit r241343, as it was, again, breaking all ARM buildbots. llvm-svn: 241362
* - Refactored ARMTargetInfo in order to use the API of ↵Alexandros Lamprineas2015-07-031-118/+78
| | | | | | | | | | | llvm/lib/Support/TargetParser.cpp for extracting target specific information. - Patch for commit 241267: ShouldUseInlineAtomic was set incorrectly when subArch was not specified, causing regressions. Change-Id: Iabb35d59722f4972f1a3ab4365880add5bbcfdcc llvm-svn: 241343
* Revert "Refactored ARMTargetInfo in order to use the API of ↵Rafael Espindola2015-07-021-72/+117
| | | | | | | | llvm/lib/Support/TargetParser.cpp for extracting target specific information." This reverts commit r241267. Tests were failing on the bots. llvm-svn: 241275
* Refactored ARMTargetInfo in order to use the API of ↵Alexandros Lamprineas2015-07-021-117/+72
| | | | | | | | | llvm/lib/Support/TargetParser.cpp for extracting target specific information. Change-Id: Ia0b83ecdb8d9223f9c4ef38dd9206969f78e53f3 llvm-svn: 241267
* test commitAlexandros Lamprineas2015-07-021-0/+2
| | | | | Change-Id: Ibaa2e1115544ddfa491335b81226819fd9cc04b4 llvm-svn: 241260
* [OPENMP] Introduced type trait "__builtin_omp_required_simd_align" for ↵Alexey Bataev2015-07-021-0/+4
| | | | | | | | | default simd alignment. Adds type trait "__builtin_omp_required_simd_align" after discussions here http://reviews.llvm.org/D9894 Differential Revision: http://reviews.llvm.org/D10597 llvm-svn: 241237
* Fix sse4 for target attribute feature additions.Eric Christopher2015-07-011-1/+14
| | | | | | | | | | This reinstates part of the hack removed in r233223, by special casing sse4 as part of the feature additions. The notable change here is that we consider it only as part of setting the SSE level and not as part of the actual target features set which handles setting the rest of the masks. llvm-svn: 241130
* Add support for the x86 builtin __builtin_cpu_supports.Eric Christopher2015-06-291-0/+28
| | | | | | | | | | | | | | | | | | | | This matches the implementation of the gcc support for the same feature, including checking the values set up by libgcc at runtime. The structure looks like this: unsigned int __cpu_vendor; unsigned int __cpu_type; unsigned int __cpu_subtype; unsigned int __cpu_features[1]; with a set of enums to match various fields that are field out after parsing the output of the cpuid instruction. This also adds a set of errors checking for valid input (and cpu). compiler-rt support for this and the other builtins in this family (__builtin_cpu_init and __builtin_cpu_is) are forthcoming. llvm-svn: 240994
* [ARM] The bits set in the variable HW_FP could get unsetRanjeet Singh2015-06-241-6/+10
| | | | | | | | | | | | when iterating through the Features vector if we don't keep track of what's already been set. This could lead to the macro __ARM_FP getting the wrong value. This patch fixes this issue by keeping track of the bits that have already been set in the loop. Differential Revision: http://reviews.llvm.org/D10395 llvm-svn: 240607
* [CodeGen] Teach X86_64ABIInfo about AVX512.Ahmed Bougacha2015-06-221-1/+3
| | | | | | | | | | | | | | | | As specified in the SysV AVX512 ABI drafts. It follows the same scheme as AVX2: Arguments of type __m512 are split into eight eightbyte chunks. The least significant one belongs to class SSE and all the others to class SSEUP. This also means we change the OpenMP SIMD default alignment on AVX512. Based on r240337. Differential Revision: http://reviews.llvm.org/D9894 llvm-svn: 240338
* AMDGPU: Fix places missed in renameMatt Arsenault2015-06-191-13/+13
| | | | llvm-svn: 240148
* AMDGPU: Add missing GK_VOLCANIC_ISLANDS to switch statementTom Stellard2015-06-181-0/+1
| | | | | | This fixes buildbot failures introduced by r240038. llvm-svn: 240059
* R600: Add Volcanic Islands targetsTom Stellard2015-06-181-1/+5
| | | | | | | | | | Reviewers: arsenm Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D10316 llvm-svn: 240038
* [SystemZ] Mangle long double as __float128Ulrich Weigand2015-06-161-0/+4
| | | | | | | | | | | | | In r239421, the mangling of long double on PowerPC Linux targets was changed to use "g" instead of "e". This same change also needs to be done for SystemZ (all targets, since we support only Linux on SystemZ anyway). This is because an old ABI variant set "long double" to a 64-bit type equivalent to "double", and the "e" mangling code is still used to refer to that old ABI for compatibility reasons. llvm-svn: 239822
* Add some basic support for CloudABI on i686.Ed Schouten2015-06-131-0/+2
| | | | | | | | | | | Some people want to experiment with building i686 CloudABI binaries. I am not entirely sure this is a good idea, as I'd rather see Intel x32 support appear. As it only requires a two-line change, let's at least provide compiler to ease experimenting. llvm-svn: 239689
* [bpf] add support for BPF backendAlexei Starovoitov2015-06-101-0/+58
| | | | | | add support for bpfel/bpfeb targets llvm-svn: 239496
* [ItaniumMangle] Mangle long double as __float128 for some Power targetsDavid Majnemer2015-06-091-0/+6
| | | | | | | | | | GCC mangles long double like __float128 in order to support compatibility with ABI variants which had a different interpretation of long double. This fixes PR23791. llvm-svn: 239421
* Simplify ARMTargetParser::parseArch(ARMTargetParser::getCanonical()), ↵Artyom Skrobov2015-06-041-3/+1
| | | | | | | | | | | | | | following r239099 Reviewers: rengolin Reviewed By: rengolin Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D10256 llvm-svn: 239101
* [SPARC] Fix types of size_t, intptr_t, and ptrdiff_t on Linux.James Y Knight2015-06-041-10/+11
| | | | | | | | They should be 'int' instead of 'long int' everywhere else except NetBSD too, from what I gather in GCC's spec files. So, optimistically changing it for everyone else, too. llvm-svn: 239046
* [Basic] Transition getEnvironmentVersion from getOSVersion for androidDavid Majnemer2015-06-011-1/+1
| | | | | | | 'android' occupies the environment component of the triple. Let's use getEnvironmentVersion to extract it instead of getOSVersion. llvm-svn: 238797
* ARM: fix ACLE predefine for iOS's "-arch armv7s".Tim Northover2015-05-291-0/+1
| | | | | | We were getting "#define __ARM_ARCH_7 -S__ 1" which is really not a good idea. llvm-svn: 238614
* [ARMTargetParser] Removing string parsing from getCPUDefineSuffix. NFC.Renato Golin2015-05-281-30/+26
| | | | | | Yet another FIXME from ARMTargetParser. llvm-svn: 238416
* [Basic] Define __declspec for cygwinDavid Majnemer2015-05-281-5/+9
| | | | | | | | Cygwin (and MinGW) targets define __declspec to __attribute__ unless -fms-extensions is specified. It turns out that cygwin headers rely on the existence of this macro. llvm-svn: 238394
* ARMTargetParser FIXME getCPUProfile A/R/MRenato Golin2015-05-271-10/+15
| | | | | | This is the last of the easy ones. llvm-svn: 238324
* ARMTargetParser FIXME: ARMv8 detection for hdivRenato Golin2015-05-271-11/+9
| | | | | | | | Avoiding ugly combination of string parsing in the front-end. We still need to move away from CPU parsing at all, but that's for a different commit. llvm-svn: 238318
* [PPC64] Add vector pack/unpack support from ISA 2.07Bill Schmidt2015-05-161-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the following new instructions in the Power ISA 2.07: vpksdss vpksdus vpkudus vpkudum vupkhsw vupklsw These instructions are available through the vec_packs, vec_packsu, vec_unpackh, and vec_unpackl built-in interfaces. These are lane-sensitive instructions, so the built-ins have different implementations for big- and little-endian, and the instructions must be marked as killing the vector swap optimization for now. The first three instructions perform saturating pack operations. The fourth performs a modulo pack operation, which means it can be represented with a vector shuffle, and conversely the appropriate vector shuffles may cause this instruction to be generated. The other instructions are only generated via built-in support for now. I noticed during patch preparation that the macro __VSX__ was not previously predefined when the power8-vector or direct-move features are requested. This is an error, and I've corrected that here as well. Appropriate tests have been added. There is a companion patch to llvm for the rest of this support. llvm-svn: 237500
* Testing for the fix for bug 23429.Nemanja Ivanovic2015-05-141-1/+1
| | | | | | | | | Follow-up to commit for revision 236848. Just a test case for the macro definition under the right CPU/Arch. One combination was actually missed in the initial fix: - powerpc64-unknown-unknown -mcpu=pwr8 (rather than -mcpu=power8). llvm-svn: 237386
* [ARM] Fix of architecture naming typoVladimir Sukharev2015-05-141-1/+1
| | | | | | | | | | Inspired by James Greenhalgh's catch Subscribers: cfe-commits Relates to: http://reviews.llvm.org/rL237349 llvm-svn: 237370
* [ARM] Add v8.1a architectureVladimir Sukharev2015-05-141-3/+30
| | | | | | | | | | | | | | Add support for ARMv8.1a architecture. Briefly it is described on http://community.arm.com/groups/processors/blog/2014/12/02/the-armv8-a-architecture-and-its-ongoing-development Reviewers: jmolloy, rengolin Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D8799 llvm-svn: 237349
* clang-format AllocateTarget. NFCDouglas Katzman2015-05-121-16/+16
| | | | llvm-svn: 237183
* Remove the code that pulled soft float attributes out of the featureEric Christopher2015-05-121-12/+4
| | | | | | | strings and remove the setting of TargetOptions::UseSoftFloat to match the code change in llvm r237079. llvm-svn: 237080
* Update initialization of a class variable and comment.Eric Christopher2015-05-121-2/+4
| | | | llvm-svn: 237071
* [Sparc] Add support for 'sparcel' to clang.Douglas Katzman2015-05-111-0/+24
| | | | | | Differential Revision: http://reviews.llvm.org/D8784 llvm-svn: 237001
* Give isCompatibleWithMSVC a better interfaceDavid Majnemer2015-05-111-1/+1
| | | | | | | We now use an enum which maps the marketing name (almost always a year) to the major version number. llvm-svn: 236967
* Fix for bug 23429.Nemanja Ivanovic2015-05-081-0/+8
| | | | | | | The macros for gcc atomic compare and swaps are defined for Power8 CPU's since the functionality is provided in the back end. llvm-svn: 236848
* [AArch64] Advertise that the __sync_*_compare_and_swap_1/2/4/8 builtins workReid Kleckner2015-05-061-0/+6
| | | | | | | Fixes PR23428, where std::thread in libstdc++ would go haywire without these defines. llvm-svn: 236605
* [SystemZ] Add support for z13 and its vector facilityUlrich Weigand2015-05-051-1/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the z13 architecture type. For compatibility with GCC, a pair of options -mvx / -mno-vx can be used to selectively enable/disable use of the vector facility. When the vector facility is present, we default to the new vector ABI. This is characterized by two major differences: - Vector types are passed/returned in vector registers (except for unnamed arguments of a variable-argument list function). - Vector types are at most 8-byte aligned. The reason for the choice of 8-byte vector alignment is that the hardware is able to efficiently load vectors at 8-byte alignment, and the ABI only guarantees 8-byte alignment of the stack pointer, so requiring any higher alignment for vectors would require dynamic stack re-alignment code. However, for compatibility with old code that may use vector types, when *not* using the vector facility, the old alignment rules (vector types are naturally aligned) remain in use. These alignment rules are not only implemented at the C language level, but also at the LLVM IR level. This is done by selecting a different DataLayout string depending on whether the vector ABI is in effect or not. Based on a patch by Richard Sandiford. llvm-svn: 236531
* R600: Add fma and ldexp asic specific feature macrosJan Vesely2015-05-041-1/+17
| | | | | | Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 236453
* ARM: merge Cyclone into other ARMv8 CPUs and add tests for features.Tim Northover2015-05-011-6/+2
| | | | | | | | Cyclone actually supports all the goodies you'd expect to come with an AArch64 CPU, so it doesn't need its own clause. Also we should probably be testing these clauses. llvm-svn: 236349
* R600: Report fp64 on all capable asicsJan Vesely2015-05-011-1/+9
| | | | | | Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 236325
* Use 4 byte preferred aggregate alignment in datalayout on x86 Win32Reid Kleckner2015-04-301-3/+4
| | | | llvm-svn: 236271
* Propagate a terrible hack to the sparc target feature handling codeEric Christopher2015-04-291-3/+5
| | | | | | | | | by erasing the soft-float target feature if the rest of the front end added it because of defaults or the soft float option. Add some testing for some of the targets that implement this hack. llvm-svn: 236179
* Revert code changes made under r235976.Bradley Smith2015-04-291-6/+0
| | | | | | | | This issue was fixed elsewhere in r235396 in a more general way, hence these changes no longer do anything. Keep the testcase however, to ensure that we don't regress this for ARM. llvm-svn: 236104
* [ARM/AArch64] Enforce alignment for bitfielded structsBradley Smith2015-04-281-0/+6
| | | | | | | | | When creating a global variable with a type of a struct with bitfields, we must forcibly set the alignment of the global from the RecordDecl. We must do this so that the proper bitfield alignment makes its way down to LLVM, since clang will mangle the bitfields into one large type. llvm-svn: 235976
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