[SystemZ] Add support for z13 and its vector facility

This patch adds support for the z13 architecture type.  For compatibility
with GCC, a pair of options -mvx / -mno-vx can be used to selectively
enable/disable use of the vector facility.

When the vector facility is present, we default to the new vector ABI.
This is characterized by two major differences:
- Vector types are passed/returned in vector registers
  (except for unnamed arguments of a variable-argument list function).
- Vector types are at most 8-byte aligned.

The reason for the choice of 8-byte vector alignment is that the hardware
is able to efficiently load vectors at 8-byte alignment, and the ABI only
guarantees 8-byte alignment of the stack pointer, so requiring any higher
alignment for vectors would require dynamic stack re-alignment code.

However, for compatibility with old code that may use vector types, when
*not* using the vector facility, the old alignment rules (vector types
are naturally aligned) remain in use.

These alignment rules are not only implemented at the C language level,
but also at the LLVM IR level.  This is done by selecting a different
DataLayout string depending on whether the vector ABI is in effect or not.

Based on a patch by Richard Sandiford.

llvm-svn: 236531

1 files changed, 22 insertions, 1 deletions

diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp
index 6d946236e28..91babd3d14e 100644
--- a/clang/lib/Basic/Targets.cpp
+++ b/clang/lib/Basic/Targets.cpp
@@ -5531,10 +5531,11 @@ class SystemZTargetInfo : public TargetInfo {
   static const char *const GCCRegNames[];
   std::string CPU;
   bool HasTransactionalExecution;
+  bool HasVector;
 
 public:
   SystemZTargetInfo(const llvm::Triple &Triple)
-    : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false) {
+    : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), HasVector(false) {
     IntMaxType = SignedLong;
     Int64Type = SignedLong;
     TLSSupported = true;
@@ -5587,6 +5588,7 @@ public:
       .Case("z10", true)
       .Case("z196", true)
       .Case("zEC12", true)
+      .Case("z13", true)
       .Default(false);
 
     return CPUKnown;
@@ -5594,6 +5596,10 @@ public:
   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
     if (CPU == "zEC12")
       Features["transactional-execution"] = true;
+    if (CPU == "z13") {
+      Features["transactional-execution"] = true;
+      Features["vector"] = true;
+    }
   }
 
   bool handleTargetFeatures(std::vector<std::string> &Features,
@@ -5602,6 +5608,14 @@ public:
     for (unsigned i = 0, e = Features.size(); i != e; ++i) {
       if (Features[i] == "+transactional-execution")
         HasTransactionalExecution = true;
+      if (Features[i] == "+vector")
+        HasVector = true;
+    }
+    // If we use the vector ABI, vector types are 64-bit aligned.
+    if (HasVector) {
+      MaxVectorAlign = 64;
+      DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64"
+                          "-v128:64-a:8:16-n32:64";
     }
     return true;
   }
@@ -5610,8 +5624,15 @@ public:
     return llvm::StringSwitch<bool>(Feature)
         .Case("systemz", true)
         .Case("htm", HasTransactionalExecution)
+        .Case("vx", HasVector)
         .Default(false);
   }
+
+  StringRef getABI() const override {
+    if (HasVector)
+      return "vector";
+    return "";
+  }
 };
 
 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = {