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* Fix sse4 for target attribute feature additions.Eric Christopher2015-07-011-1/+14
| | | | | | | | | | This reinstates part of the hack removed in r233223, by special casing sse4 as part of the feature additions. The notable change here is that we consider it only as part of setting the SSE level and not as part of the actual target features set which handles setting the rest of the masks. llvm-svn: 241130
* Add support for the x86 builtin __builtin_cpu_supports.Eric Christopher2015-06-291-0/+28
| | | | | | | | | | | | | | | | | | | | This matches the implementation of the gcc support for the same feature, including checking the values set up by libgcc at runtime. The structure looks like this: unsigned int __cpu_vendor; unsigned int __cpu_type; unsigned int __cpu_subtype; unsigned int __cpu_features[1]; with a set of enums to match various fields that are field out after parsing the output of the cpuid instruction. This also adds a set of errors checking for valid input (and cpu). compiler-rt support for this and the other builtins in this family (__builtin_cpu_init and __builtin_cpu_is) are forthcoming. llvm-svn: 240994
* [ARM] The bits set in the variable HW_FP could get unsetRanjeet Singh2015-06-241-6/+10
| | | | | | | | | | | | when iterating through the Features vector if we don't keep track of what's already been set. This could lead to the macro __ARM_FP getting the wrong value. This patch fixes this issue by keeping track of the bits that have already been set in the loop. Differential Revision: http://reviews.llvm.org/D10395 llvm-svn: 240607
* [CodeGen] Teach X86_64ABIInfo about AVX512.Ahmed Bougacha2015-06-221-1/+3
| | | | | | | | | | | | | | | | As specified in the SysV AVX512 ABI drafts. It follows the same scheme as AVX2: Arguments of type __m512 are split into eight eightbyte chunks. The least significant one belongs to class SSE and all the others to class SSEUP. This also means we change the OpenMP SIMD default alignment on AVX512. Based on r240337. Differential Revision: http://reviews.llvm.org/D9894 llvm-svn: 240338
* AMDGPU: Fix places missed in renameMatt Arsenault2015-06-191-13/+13
| | | | llvm-svn: 240148
* AMDGPU: Add missing GK_VOLCANIC_ISLANDS to switch statementTom Stellard2015-06-181-0/+1
| | | | | | This fixes buildbot failures introduced by r240038. llvm-svn: 240059
* R600: Add Volcanic Islands targetsTom Stellard2015-06-181-1/+5
| | | | | | | | | | Reviewers: arsenm Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D10316 llvm-svn: 240038
* [SystemZ] Mangle long double as __float128Ulrich Weigand2015-06-161-0/+4
| | | | | | | | | | | | | In r239421, the mangling of long double on PowerPC Linux targets was changed to use "g" instead of "e". This same change also needs to be done for SystemZ (all targets, since we support only Linux on SystemZ anyway). This is because an old ABI variant set "long double" to a 64-bit type equivalent to "double", and the "e" mangling code is still used to refer to that old ABI for compatibility reasons. llvm-svn: 239822
* Add some basic support for CloudABI on i686.Ed Schouten2015-06-131-0/+2
| | | | | | | | | | | Some people want to experiment with building i686 CloudABI binaries. I am not entirely sure this is a good idea, as I'd rather see Intel x32 support appear. As it only requires a two-line change, let's at least provide compiler to ease experimenting. llvm-svn: 239689
* [bpf] add support for BPF backendAlexei Starovoitov2015-06-101-0/+58
| | | | | | add support for bpfel/bpfeb targets llvm-svn: 239496
* [ItaniumMangle] Mangle long double as __float128 for some Power targetsDavid Majnemer2015-06-091-0/+6
| | | | | | | | | | GCC mangles long double like __float128 in order to support compatibility with ABI variants which had a different interpretation of long double. This fixes PR23791. llvm-svn: 239421
* Simplify ARMTargetParser::parseArch(ARMTargetParser::getCanonical()), ↵Artyom Skrobov2015-06-041-3/+1
| | | | | | | | | | | | | | following r239099 Reviewers: rengolin Reviewed By: rengolin Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D10256 llvm-svn: 239101
* [SPARC] Fix types of size_t, intptr_t, and ptrdiff_t on Linux.James Y Knight2015-06-041-10/+11
| | | | | | | | They should be 'int' instead of 'long int' everywhere else except NetBSD too, from what I gather in GCC's spec files. So, optimistically changing it for everyone else, too. llvm-svn: 239046
* [Basic] Transition getEnvironmentVersion from getOSVersion for androidDavid Majnemer2015-06-011-1/+1
| | | | | | | 'android' occupies the environment component of the triple. Let's use getEnvironmentVersion to extract it instead of getOSVersion. llvm-svn: 238797
* ARM: fix ACLE predefine for iOS's "-arch armv7s".Tim Northover2015-05-291-0/+1
| | | | | | We were getting "#define __ARM_ARCH_7 -S__ 1" which is really not a good idea. llvm-svn: 238614
* [ARMTargetParser] Removing string parsing from getCPUDefineSuffix. NFC.Renato Golin2015-05-281-30/+26
| | | | | | Yet another FIXME from ARMTargetParser. llvm-svn: 238416
* [Basic] Define __declspec for cygwinDavid Majnemer2015-05-281-5/+9
| | | | | | | | Cygwin (and MinGW) targets define __declspec to __attribute__ unless -fms-extensions is specified. It turns out that cygwin headers rely on the existence of this macro. llvm-svn: 238394
* ARMTargetParser FIXME getCPUProfile A/R/MRenato Golin2015-05-271-10/+15
| | | | | | This is the last of the easy ones. llvm-svn: 238324
* ARMTargetParser FIXME: ARMv8 detection for hdivRenato Golin2015-05-271-11/+9
| | | | | | | | Avoiding ugly combination of string parsing in the front-end. We still need to move away from CPU parsing at all, but that's for a different commit. llvm-svn: 238318
* [PPC64] Add vector pack/unpack support from ISA 2.07Bill Schmidt2015-05-161-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the following new instructions in the Power ISA 2.07: vpksdss vpksdus vpkudus vpkudum vupkhsw vupklsw These instructions are available through the vec_packs, vec_packsu, vec_unpackh, and vec_unpackl built-in interfaces. These are lane-sensitive instructions, so the built-ins have different implementations for big- and little-endian, and the instructions must be marked as killing the vector swap optimization for now. The first three instructions perform saturating pack operations. The fourth performs a modulo pack operation, which means it can be represented with a vector shuffle, and conversely the appropriate vector shuffles may cause this instruction to be generated. The other instructions are only generated via built-in support for now. I noticed during patch preparation that the macro __VSX__ was not previously predefined when the power8-vector or direct-move features are requested. This is an error, and I've corrected that here as well. Appropriate tests have been added. There is a companion patch to llvm for the rest of this support. llvm-svn: 237500
* Testing for the fix for bug 23429.Nemanja Ivanovic2015-05-141-1/+1
| | | | | | | | | Follow-up to commit for revision 236848. Just a test case for the macro definition under the right CPU/Arch. One combination was actually missed in the initial fix: - powerpc64-unknown-unknown -mcpu=pwr8 (rather than -mcpu=power8). llvm-svn: 237386
* [ARM] Fix of architecture naming typoVladimir Sukharev2015-05-141-1/+1
| | | | | | | | | | Inspired by James Greenhalgh's catch Subscribers: cfe-commits Relates to: http://reviews.llvm.org/rL237349 llvm-svn: 237370
* [ARM] Add v8.1a architectureVladimir Sukharev2015-05-141-3/+30
| | | | | | | | | | | | | | Add support for ARMv8.1a architecture. Briefly it is described on http://community.arm.com/groups/processors/blog/2014/12/02/the-armv8-a-architecture-and-its-ongoing-development Reviewers: jmolloy, rengolin Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D8799 llvm-svn: 237349
* clang-format AllocateTarget. NFCDouglas Katzman2015-05-121-16/+16
| | | | llvm-svn: 237183
* Remove the code that pulled soft float attributes out of the featureEric Christopher2015-05-121-12/+4
| | | | | | | strings and remove the setting of TargetOptions::UseSoftFloat to match the code change in llvm r237079. llvm-svn: 237080
* Update initialization of a class variable and comment.Eric Christopher2015-05-121-2/+4
| | | | llvm-svn: 237071
* [Sparc] Add support for 'sparcel' to clang.Douglas Katzman2015-05-111-0/+24
| | | | | | Differential Revision: http://reviews.llvm.org/D8784 llvm-svn: 237001
* Give isCompatibleWithMSVC a better interfaceDavid Majnemer2015-05-111-1/+1
| | | | | | | We now use an enum which maps the marketing name (almost always a year) to the major version number. llvm-svn: 236967
* Fix for bug 23429.Nemanja Ivanovic2015-05-081-0/+8
| | | | | | | The macros for gcc atomic compare and swaps are defined for Power8 CPU's since the functionality is provided in the back end. llvm-svn: 236848
* [AArch64] Advertise that the __sync_*_compare_and_swap_1/2/4/8 builtins workReid Kleckner2015-05-061-0/+6
| | | | | | | Fixes PR23428, where std::thread in libstdc++ would go haywire without these defines. llvm-svn: 236605
* [SystemZ] Add support for z13 and its vector facilityUlrich Weigand2015-05-051-1/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the z13 architecture type. For compatibility with GCC, a pair of options -mvx / -mno-vx can be used to selectively enable/disable use of the vector facility. When the vector facility is present, we default to the new vector ABI. This is characterized by two major differences: - Vector types are passed/returned in vector registers (except for unnamed arguments of a variable-argument list function). - Vector types are at most 8-byte aligned. The reason for the choice of 8-byte vector alignment is that the hardware is able to efficiently load vectors at 8-byte alignment, and the ABI only guarantees 8-byte alignment of the stack pointer, so requiring any higher alignment for vectors would require dynamic stack re-alignment code. However, for compatibility with old code that may use vector types, when *not* using the vector facility, the old alignment rules (vector types are naturally aligned) remain in use. These alignment rules are not only implemented at the C language level, but also at the LLVM IR level. This is done by selecting a different DataLayout string depending on whether the vector ABI is in effect or not. Based on a patch by Richard Sandiford. llvm-svn: 236531
* R600: Add fma and ldexp asic specific feature macrosJan Vesely2015-05-041-1/+17
| | | | | | Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 236453
* ARM: merge Cyclone into other ARMv8 CPUs and add tests for features.Tim Northover2015-05-011-6/+2
| | | | | | | | Cyclone actually supports all the goodies you'd expect to come with an AArch64 CPU, so it doesn't need its own clause. Also we should probably be testing these clauses. llvm-svn: 236349
* R600: Report fp64 on all capable asicsJan Vesely2015-05-011-1/+9
| | | | | | Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 236325
* Use 4 byte preferred aggregate alignment in datalayout on x86 Win32Reid Kleckner2015-04-301-3/+4
| | | | llvm-svn: 236271
* Propagate a terrible hack to the sparc target feature handling codeEric Christopher2015-04-291-3/+5
| | | | | | | | | by erasing the soft-float target feature if the rest of the front end added it because of defaults or the soft float option. Add some testing for some of the targets that implement this hack. llvm-svn: 236179
* Revert code changes made under r235976.Bradley Smith2015-04-291-6/+0
| | | | | | | | This issue was fixed elsewhere in r235396 in a more general way, hence these changes no longer do anything. Keep the testcase however, to ensure that we don't regress this for ARM. llvm-svn: 236104
* [ARM/AArch64] Enforce alignment for bitfielded structsBradley Smith2015-04-281-0/+6
| | | | | | | | | When creating a global variable with a type of a struct with bitfields, we must forcibly set the alignment of the global from the RecordDecl. We must do this so that the proper bitfield alignment makes its way down to LLVM, since clang will mangle the bitfields into one large type. llvm-svn: 235976
* Implement target-specific __attribute__((aligned)) valueUlrich Weigand2015-04-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GCC construct __attribute__((aligned)) is defined to set alignment to "the default alignment for the target architecture" according to the GCC documentation: The default alignment is sufficient for all scalar types, but may not be enough for all vector types on a target that supports vector operations. The default alignment is fixed for a particular target ABI. clang currently hard-coded an alignment of 16 bytes for that construct, which is correct on some platforms (including X86), but wrong on others (including SystemZ). Since this value is ABI-relevant, it is important to get correct for compatibility purposes. This patch adds a new TargetInfo member "DefaultAlignForAttributeAligned" that targets can set to the appropriate default __attribute__((aligned)) value. Note that I'm deliberately *not* using the existing "SuitableAlign" value, which is used to set the pre-defined macro __BIGGEST_ALIGNMENT__, since those two values may not be the same on all platforms. In fact, on X86, __attribute__((aligned)) always uses 16-byte alignment, while __BIGGEST_ALIGNMENT__ may be larger if AVX-2 or AVX-512 are supported. (This is actually not yet correctly implemented in clang either.) The patch provides a value for DefaultAlignForAttributeAligned only for SystemZ, and leaves the default for all other targets at 16, which means no visible change in behavior on all other targets. (The value is still wrong for some other targets, but I'd prefer to leave it to the target maintainers for those platforms to fix.) llvm-svn: 235397
* R600: Add GCC reg namesTom Stellard2015-04-141-4/+60
| | | | llvm-svn: 234892
* Add Clang support for -mdirect-move on PPCNemanja Ivanovic2015-04-111-1/+12
| | | | | | | | | | This patch corresponds to review: http://reviews.llvm.org/D8930 This just adds a front end option to let the back end know the target has PPC direct move instructions. llvm-svn: 234683
* Use 'override/final' instead of 'virtual' for overridden methodsAlexander Kornienko2015-04-111-15/+14
| | | | | | | | | | | | | | | | | | | | Summary: The patch is generated using clang-tidy misc-use-override check. This command was used: tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py \ -checks='-*,misc-use-override' -header-filter='llvm|clang' -j=32 -fix Reviewers: dblaikie Reviewed By: dblaikie Subscribers: klimek, cfe-commits Differential Revision: http://reviews.llvm.org/D8926 llvm-svn: 234678
* Create the correct profiling symbol on NetBSD.Joerg Sonnenberger2015-04-101-0/+1
| | | | llvm-svn: 234636
* Create correct platform-specific target for NetBSD PPC64LE.Joerg Sonnenberger2015-04-101-0/+2
| | | | llvm-svn: 234629
* Add Clang support for remaining integer divide and permute instructions from ↵Nemanja Ivanovic2015-04-091-1/+26
| | | | | | | | | | | ISA 2.06 This patch corresponds to review: http://reviews.llvm.org/D8398 It adds some builtin functions to access the extended divide and bit permute instructions. llvm-svn: 234547
* [ARM] add support for Cortex-R4/R4FJaved Absar2015-04-091-3/+3
| | | | | | | | Adds ARM Cortex-R4 and R4F support and tests in Clang. Though Cortex-R4 support was present, the support for hwdiv in thumb-mode was not defined or tested properly. This has also been added. llvm-svn: 234488
* Set the type of ptrdiff_t to signed on NVPTX targetsEli Bendersky2015-04-011-4/+6
| | | | | | | It was unsigned before, which is unlike any other target and also doesn't make much sense. llvm-svn: 233836
* Set NVPTX64 target's size_t to match other 64-bit targetsEli Bendersky2015-04-011-2/+2
| | | | llvm-svn: 233830
* Fix data layout mismatch between LLVM and Clang for i686-pc-windows-msvc-elfReid Kleckner2015-04-011-1/+4
| | | | | | | | Do the same thing as win64. If we're not using COFF, use the ELF manglings. Maybe if we are targetting *-windows-msvc-macho, we should use darwin manglings, but I don't need to stir that pot today. llvm-svn: 233819
* [SystemZ] Add header files to Makefile / module.modulemapUlrich Weigand2015-04-011-1/+2
| | | | | | | | | | This should fix build-bot failures after r233804. The patch also adds a "systemz" feature, and renames the "transactional-execution" feature to "htm", since it turns out "-" is not a legal character in module feature names. llvm-svn: 233807
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