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* AMDGPU/GlobalISel: Select G_TRUNCMatt Arsenault2019-06-245-24/+488
| | | | llvm-svn: 364215
* AMDGPU/GlobalISel: RegBankSelect for amdgcn.classMatt Arsenault2019-06-242-0/+40
| | | | llvm-svn: 364214
* [PowerPC][UpdateTestChecks] powerpc- triple supportJinsong Ji2019-06-242-32/+34
| | | | | | | | | There are quite some old testcases with powerpc- triple, we should add this triple support so that we can update them with script. Differential Revision: https://reviews.llvm.org/D63723 llvm-svn: 364213
* AMDGPU/GlobalISel: Split VALU s64 G_ZEXT/G_SEXT in RegBankSelectMatt Arsenault2019-06-243-25/+144
| | | | | | | | | | | Scalar extends to s64 can use S_BFE_{I64|U64}, but vector extends need to extend to the 32-bit half, and then to 64. I'm not sure what the line should be between what RegBankSelect handles, and what instruction select does, but for now I'm erring on the side of RegBankSelect for future post-RBS combines. llvm-svn: 364212
* [llvm-objdump] Match GNU objdump on symbol types shown in disassemblyYuanfang Chen2019-06-242-16/+62
| | | | | | | | | | | | output. STT_OBJECT and STT_COMMON are dumped as data, not disassembled. https://bugs.llvm.org/show_bug.cgi?id=41947 Differential Revision: https://reviews.llvm.org/D62964 llvm-svn: 364211
* Move common functionality from processwindows into processdebuggerAaron Smith2019-06-245-452/+716
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change extracts functionalities from processwindows into a introduced processdebugger that can be reused in native process debugging. The main reason is that the native process debugging can't directly be based on processwindows or be implemented as a pass-through to this plugin since the plugin has ties to Target and Process classes that are needed in host debugging but not necessary in native debugging. Reviewers: labath, Hui, jfb, clayborg, amccarth Reviewed By: labath Subscribers: amccarth, dexonsmith, mgorny, lldb-commits Tags: #lldb Differential Revision: https://reviews.llvm.org/D63166 llvm-svn: 364210
* [AMDGPU] Allow any value in unused src0 field in v_nopTim Renouf2019-06-244-1/+10
| | | | | | | | | | | | | Summary: The LLVM disassembler assumes that the unused src0 operand of v_nop is zero. Other tools can put another value in that field, which is still valid. This commit fixes the LLVM disassembler to recognize such an encoding as v_nop, in the same way as we already do for s_getpc. Differential Revision: https://reviews.llvm.org/D63724 Change-Id: Iaf0363eae26ff92fc4ebc716216476adbff37a6f llvm-svn: 364208
* [X86] Don't a vzext_movl in LowerBuildVectorv16i8/LowerBuildVectorv8i16 if ↵Craig Topper2019-06-241-3/+3
| | | | | | | | | | | | | | there are no zeroes in the vector we're building. In LowerBuildVectorv16i8 we took care to use an any_extend if the first pair is in the lower 16-bits of the vector and no elements are 0. So bits [31:16] will be undefined. But we still emitted a vzext_movl to ensure that bits [127:32] are 0. If we don't need any zeroes we should be consistent and make all of 127:16 undefined. In LowerBuildVectorv8i16 we can just delete the vzext_movl code because we only use the scalar_to_vector when there are no zeroes. So the vzext_movl is always unnecessary. Found while investigating whether (vzext_movl (scalar_to_vector (loadi32)) patterns are necessary. At least one of the cases where they were necessary was where the loadi32 matched 32-bit aligned 16-bit extload. Seemed weird that we required vzext_movl for that case. Differential Revision: https://reviews.llvm.org/D63700 llvm-svn: 364207
* [X86] Cleanups and safety checks around the isFNEGCraig Topper2019-06-242-37/+32
| | | | | | | | | | | | | This patch does a few things to start cleaning up the isFNEG function. -Remove the Op0/Op1 peekThroughBitcast calls that seem unnecessary. getTargetConstantBitsFromNode has its own peekThroughBitcast inside. And we have a separate peekThroughBitcast on the return value. -Add a check of the scalar size after the first peekThroughBitcast to ensure we haven't changed the element size and just did something like f32->i32 or f64->i64. -Remove an unnecessary check that Op1's type is floating point after the peekThroughBitcast. We're just going to look for a bit pattern from a constant. We don't care about its type. -Add VT checks on several places that consume the return value of isFNEG. Due to the peekThroughBitcasts inside, the type of the return value isn't guaranteed. So its not safe to use it to build other nodes without ensuring the type matches the type being used to build the node. We might be able to replace these checks with bitcasts instead, but I don't have a test case so a bail out check seemed better for now. Differential Revision: https://reviews.llvm.org/D63683 llvm-svn: 364206
* [AArch64] Regenerate vcvt tests. NFCI.Simon Pilgrim2019-06-241-30/+113
| | | | | | Prep work for an upcoming patch llvm-svn: 364205
* [AArch64] Regenerate 2velem tests. NFCI.Simon Pilgrim2019-06-241-479/+1622
| | | | | | Prep work for an upcoming patch llvm-svn: 364204
* [AArch64] Regenerate merge-store tests. NFCI.Simon Pilgrim2019-06-241-13/+31
| | | | | | Prep work for an upcoming patch llvm-svn: 364203
* [clang][NewPM] Add RUNS for tests that produce slightly different IR under ↵Leonard Chan2019-06-241-2/+8
| | | | | | | | | | new PM For CodeGenOpenCL/convergent.cl, the new PM produced a slightly different for loop, but this still checks for no loop unrolling as intended. This is committed separately from D63174. llvm-svn: 364202
* [clang][NewPM] Remove exception handling before loading pgo sample profile dataLeonard Chan2019-06-241-3/+10
| | | | | | | | | This patch ensures that SimplifyCFGPass comes before SampleProfileLoaderPass on PGO runs in the new PM and fixes clang/test/CodeGen/pgo-sample.c. Differential Revision: https://reviews.llvm.org/D63626 llvm-svn: 364201
* [X86] Regenerate fast fadd reduction tests. NFCISimon Pilgrim2019-06-241-2/+2
| | | | | | Fix whitespace. llvm-svn: 364200
* AMDGPU/GlobalISel: Fix selecting G_IMPLICIT_DEF for s1Matt Arsenault2019-06-243-36/+160
| | | | | | Try to fail for scc, since I don't think that should ever be produced. llvm-svn: 364199
* [bindings/go] Add debug information accessorsAyke van Laethem2019-06-242-0/+93
| | | | | | | | | | | | | | | | | | | | | | | Add debug information accessors, as provided in the following patches: https://reviews.llvm.org/D46627 (DILocation) https://reviews.llvm.org/D52693 metadata kind https://reviews.llvm.org/D60481 get/set debug location on a Value https://reviews.llvm.org/D60489 (DIScope) The API as proposed in this patch is similar to the current Value API, with a single root type and methods that are only valid for certain subclasses. I have considered just implementing generic Line() calls (that are valid on all DINodes that have a line) but the implementation of that got a bit awkward without support from the C API. I've also considered creating generic getters like a Metadata.DebugLoc() that returns a DebugLoc, but there is a mismatch between the Go DI nodes in the LLVM API and the actual DINode class hierarchy, so that's also hard to get right (without being confusing or breaking the API). Differential Revision: https://reviews.llvm.org/D63056 llvm-svn: 364198
* [analyzer] print() JSONify: ProgramPoint revisionCsaba Dabis2019-06-242-1/+4
| | | | | | | | | | | | | | | | | Summary: Now we also print out the filename with its path. Reviewers: NoQ Reviewed By: NoQ Subscribers: xazax.hun, baloghadamsoftware, szepet, a.sidorin, mikhail.ramalho, Szelethus, donat.nagy, dkrupp, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D63438 llvm-svn: 364197
* Hexagon: Rename another copy of Register classMatt Arsenault2019-06-241-87/+90
| | | | | | For some reason clang is happy with the conflict, but MSVC is not. llvm-svn: 364196
* ARC: Fix -Wimplicit-fallthroughMatt Arsenault2019-06-241-0/+4
| | | | llvm-svn: 364195
* GlobalISel: Remove unsigned variant of SrcOpMatt Arsenault2019-06-2428-467/+468
| | | | | | | | | Force using Register. One downside is the generated register enums require explicit conversion. llvm-svn: 364194
* [analyzer] Fix JSON dumps for ExplodedNodesCsaba Dabis2019-06-242-10/+10
| | | | | | | | | | | | | | | | | | | Summary: - Now we could see the `has_report` property in `trim-egraph` mode. - This patch also removes the trailing comma after each node. Reviewers: NoQ Reviewed By: NoQ Subscribers: xazax.hun, baloghadamsoftware, szepet, a.sidorin, mikhail.ramalho, Szelethus, donat.nagy, dkrupp, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D63436 llvm-svn: 364193
* CodeGen: Introduce a class for registersMatt Arsenault2019-06-2495-487/+553
| | | | | | | | | Avoids using a plain unsigned for registers throughoug codegen. Doesn't attempt to change every register use, just something a little more than the set needed to build after changing the return type of MachineOperand::getReg(). llvm-svn: 364191
* [AMDGPU] Remove unused variable AllSGPRSpilledToVGPRs. NFCBjorn Pettersson2019-06-241-5/+1
| | | | | | | | | | | | | | | | | | | | | Summary: Removing the unused variable AllSGPRSpilledToVGPRs in SIFrameLowering::processFunctionBeforeFrameFinalized to avoid error: variable 'AllSGPRSpilledToVGPRs' set but not used [-Werror=unused-but-set-variable] Reviewers: arsenm, nhaehnle Reviewed By: nhaehnle Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63721 llvm-svn: 364190
* [OPENMP]Relax the test checks to pacify 32bit buildbots, NFC.Alexey Bataev2019-06-241-2/+2
| | | | llvm-svn: 364189
* Hexagon: Rename Register classMatt Arsenault2019-06-241-32/+33
| | | | | | This avoids a naming conflict in a future patch. llvm-svn: 364188
* [InstCombine] reduce funnel-shift i16 X, X, 8 to bswap XSanjay Patel2019-06-242-3/+16
| | | | | | | | | | Prefer the more exact intrinsic to remove a use of the input value and possibly make further transforms easier (we will still need to match patterns with funnel-shift of wider types as pieces of bswap, especially if we want to canonicalize to funnel-shift with constant shift amount). Discussed in D46760. llvm-svn: 364187
* AMDGPU/GlobalISel: Fix RegBankSelect for s1 sext/zext/anyextMatt Arsenault2019-06-244-24/+768
| | | | | | | | This needs different handling if the source is known to be a valid condition or not. Handle turning it into shifts or a select during regbankselect. llvm-svn: 364186
* AMDGPU: Fold frame index into MUBUFMatt Arsenault2019-06-247-20/+256
| | | | | | | | | | | | | | | | This matters for byval uses outside of the entry block, which appear as copies. Previously, the only folding done was during selection, which could not see the underlying frame index. For any uses outside the entry block, the frame index was materialized in the entry block relative to the global scratch wave offset. This may produce worse code in cases where the offset ends up not fitting in the MUBUF offset field. A better heuristic would be helpfu for extreme frames. llvm-svn: 364185
* [InstCombine] add tests for funnel-shift to bswap; NFCSanjay Patel2019-06-241-0/+37
| | | | llvm-svn: 364184
* [CUDA][HIP] Don't set comdat attribute for CUDA device stub ↵Konstantin Pyzhov2019-06-241-0/+5
| | | | | | functions.\nDifferential Revision: https://reviews.llvm.org/D63277 llvm-svn: 364183
* AMDGPU: Cleanup checking when spills need emergency slotsMatt Arsenault2019-06-241-7/+6
| | | | | | Address fixme, which should no longer be a problem since r363757. llvm-svn: 364182
* [InstCombine] SliceUpIllegalIntegerPHI - bail on out of range shiftsSimon Pilgrim2019-06-242-0/+31
| | | | | | | | trunc(lshr) handling - if the shift is out of range (undefined) then bail like we do for non-constant shifts. Fixes OSS Fuzz #15217 llvm-svn: 364181
* [clangd] Improve SelectionTree string representationSam McCall2019-06-241-1/+12
| | | | llvm-svn: 364180
* [DAGCombine] visitMUL - allow shift by zero in MulByConstant.Simon Pilgrim2019-06-242-6/+30
| | | | | | | | This can occur under certain circumstances when undefs are created later on in the constant multipliers (e.g. in this case due to SimplifyDemandedVectorElts). Its better to let the shift by zero to occur and perform any cleanup afterward. Fixes OSS Fuzz #15429 llvm-svn: 364179
* [ConstantFolding] Use hasVectorInstrinsicScalarOpd. NFCBjorn Pettersson2019-06-241-16/+13
| | | | | | | | | | | | | | | | | | Summary: Use the hasVectorInstrinsicScalarOpd helper function in ConstantFoldVectorCall. Reviewers: rengolin, RKSimon, dblaikie Reviewed By: rengolin, RKSimon Subscribers: tschuett, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63705 llvm-svn: 364178
* [Scalarizer] Add scalarizer support for smul.fix.satBjorn Pettersson2019-06-243-10/+26
| | | | | | | | | | | | | | | | | | | | | | | Summary: Handle smul.fix.sat in the scalarizer. This is done by adding smul.fix.sat to the set of "isTriviallyVectorizable" intrinsics. The addition of smul.fix.sat in isTriviallyVectorizable and hasVectorInstrinsicScalarOpd can also be seen as a preparation to be able to use hasVectorInstrinsicScalarOpd in ConstantFolding. Reviewers: rengolin, RKSimon, dblaikie Reviewed By: rengolin Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63704 llvm-svn: 364177
* [docs][llvm-nm] Add missing options to documentationJames Henderson2019-06-241-21/+91
| | | | | | | | | | | | | | There were several options missing from the documentation. This patch adds them as well as improving some wording and separating the Mach-O only options into a separate section. Fixes https://bugs.llvm.org/show_bug.cgi?id=42234. Reviewed by: MaskRay Differential Revision: https://reviews.llvm.org/D63655 llvm-svn: 364176
* [sancov] Avoid unnecessary unique_ptrFangrui Song2019-06-241-12/+10
| | | | llvm-svn: 364175
* [OpenCL] Restore ATOMIC_VAR_INITSven van Haastregt2019-06-242-1/+10
| | | | | | | | | We accidentally lost the ATOMIC_VAR_INIT and ATOMIC_FLAG_INIT macros in r363794. Also put the `memory_order` typedef back inside a `>= CL2.0` guard. llvm-svn: 364174
* [OpenCL] Remove more duplicates from opencl-c.hSven van Haastregt2019-06-241-29/+0
| | | | | | | | Identified the duplicate declarations using sort lib/Headers/opencl-c.h | uniq -c | grep ' 2' llvm-svn: 364173
* [ARM] Add MVE interleaving load/store family.Simon Tatham2019-06-249-33/+809
| | | | | | | | | | | | | | | | | | This adds the family of loads and stores with names like VLD20.8 and VST42.32, which load and store parts of multiple q-registers in such a way that executing both VLD20 and VLD21, or all four of VLD40..VLD43, will distribute 2 or 4 vectors' worth of memory data across the lanes of the same number of registers but in a transposed order. In addition to the Tablegen descriptions of the instructions themselves, this patch also adds encode and decode support for the QQPR and QQQQPR register classes (representing the range of loaded or stored vector registers), and tweaks to the parsing system for lists of vector registers to make it return the right format in this case (since, unlike NEON, MVE regards q-registers as primitive, and not just an alias for two d-registers). llvm-svn: 364172
* [docs][llvm-nm] Improve symbol code documentationJames Henderson2019-06-241-15/+70
| | | | | | | | | | | | | | The existing symbol code documentation was very incomplete. This patch adds the missing codes, and defines them based on the current code behaviour. Fixes https://bugs.llvm.org/show_bug.cgi?id=42231. Reviewed by: rupprecht, mtrent, MaskRay Differential Revision: https://reviews.llvm.org/D63327 llvm-svn: 364171
* [libcxx] [test] Read files as bytestrings to fix py3 encoding issuesMichal Gorny2019-06-241-6/+8
| | | | | | | | | | | | | | | | Use binary mode to read test files in libcxx LibcxxTestFormat class. This ensures that tests are read correctly independently of encoding, and therefore fixes UnicodeDecodeError when file is opened in Python 3 that defaults to pure ASCII encoding. Technically this could be also fixed via conditionally appending encoding argument when opening the file in Python 3. However, since the code in question only searches for fixed ASCII substrings reading it in binary mode is simpler and more universal. Differential Revision: https://reviews.llvm.org/D63346 llvm-svn: 364170
* [Support] Fix error handling in DataExtractor::get[US]LEB128Pavel Labath2019-06-242-14/+24
| | | | | | | | | | | | | | | | | | | | | | | Summary: These functions are documented as not modifying the offset argument if the extraction fails (just like other DataExtractor functions). However, while reviewing D63591 we discovered that this is not the case -- if the function reaches the end of the data buffer, it will just return the value parsed until that point and set offset to point to the end of the buffer. This fixes the functions to act as advertised, and adds a regression test. Reviewers: dblaikie, probinson, bkramer Subscribers: kristina, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63645 llvm-svn: 364169
* Follow up of rL363913. NFC.Sjoerd Meijer2019-06-241-5/+7
| | | | | | | Minor reshuffle in AArch64 targetparser unittest, solving a potential problem with querying iterators too early. llvm-svn: 364168
* [llvm-readobj/llvm-readelf] - Eliminate the elf-groups.x86_64 precompiled ↵George Rimar2019-06-243-62/+80
| | | | | | | | | | | | | | | | binary from the inputs. We do not need the elf-groups.x86_64. In one of the tests, it was used for no solid reason, and for the second test case we can use YAML input with SHT_GROUP sections. The patch performs a cleanup of one of the test cases, removes another one completely (since during the review was found out it actually duplicates one of the existent tests) and removes the precompiled binary. Differential revision: https://reviews.llvm.org/D63647 llvm-svn: 364167
* PR42362: Fix auto deduction of template parameter packs fromRichard Smith2019-06-242-1/+19
| | | | | | | | | type-dependent argument packs. We need to strip off the PackExpansionExpr to get the real (dependent) type rather than an opaque DependentTy. llvm-svn: 364165
* [ELF][PPC][X86] Use [-2**(n-1), 2**n) to check overflows for R_PPC_ADDR16, ↵Fangrui Song2019-06-2424-114/+110
| | | | | | | | | | | | | | | | | | | | | R_PPC64_ADDR{16,32}, R_X86_64_{8,16} Similar to R_AARCH64_ABS32, R_PPC64_ADDR32 can represent either a signed value or unsigned value, thus we should use `[-2**(n-1), 2**n)` instead of `[-2**(n-1), 2**(n-1))` to check overflows. The issue manifests as a bogus linker error when linking the powerpc64le Linux kernel. The new behavior is compatible with ld.bfd's complain_overflow_bitfield. The upper bound of the error message is not correct. Fix it as well. The changes to R_PPC_ADDR16, R_PPC64_ADDR16, R_X86_64_8 and R_X86_64_16 are similar. Reviewed By: ruiu Differential Revision: https://reviews.llvm.org/D63690 llvm-svn: 364164
* [X86] Turn v16i16->v16i8 truncate+store into a any_extend+truncstore if we ↵Craig Topper2019-06-236-15/+22
| | | | | | | | | | | | | | | | avx512f, but not avx512bw. Ideally we'd be able to represent this truncate as a any_extend to v16i32 and a truncate, but SelectionDAG doens't know how to not fold those together. We have isel patterns to use a vpmovzxwd+vpdmovdb for the truncate, but we aren't able to simultaneously fold the load and the store from the isel pattern. By pulling the truncate into the store we can successfully hide it from the DAG combiner. Then we can isel pattern match the truncstore and load+any_extend separately. llvm-svn: 364163
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