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| author | Tim Renouf <tpr.llvm@botech.co.uk> | 2019-06-24 17:35:20 +0000 |
|---|---|---|
| committer | Tim Renouf <tpr.llvm@botech.co.uk> | 2019-06-24 17:35:20 +0000 |
| commit | d2fdb956e0442707b69df4107cd64c2022c1cb54 (patch) | |
| tree | 34756c861e3dc548cd1942b6b3f231c4e9006508 | |
| parent | 7fccb2ac5e32c074b91411f80da5a038c12489a5 (diff) | |
| download | bcm5719-llvm-d2fdb956e0442707b69df4107cd64c2022c1cb54.tar.gz bcm5719-llvm-d2fdb956e0442707b69df4107cd64c2022c1cb54.zip | |
[AMDGPU] Allow any value in unused src0 field in v_nop
Summary:
The LLVM disassembler assumes that the unused src0 operand of v_nop is
zero. Other tools can put another value in that field, which is still
valid. This commit fixes the LLVM disassembler to recognize such an
encoding as v_nop, in the same way as we already do for s_getpc.
Differential Revision: https://reviews.llvm.org/D63724
Change-Id: Iaf0363eae26ff92fc4ebc716216476adbff37a6f
llvm-svn: 364208
| -rw-r--r-- | llvm/lib/Target/AMDGPU/VOP1Instructions.td | 2 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/AMDGPU/nop.txt | 3 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/AMDGPU/vop1.txt | 3 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/AMDGPU/vop1_vi.txt | 3 |
4 files changed, 10 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td index a916091d6fb..6bc416ed7d4 100644 --- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td @@ -14,7 +14,7 @@ class VOP1e <bits<8> op, VOPProfile P> : Enc32 { bits<8> vdst; bits<9> src0; - let Inst{8-0} = !if(P.HasSrc0, src0{8-0}, 0); + let Inst{8-0} = !if(P.HasSrc0, src0{8-0}, ?); let Inst{16-9} = op; let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0); let Inst{31-25} = 0x3f; //encoding diff --git a/llvm/test/MC/Disassembler/AMDGPU/nop.txt b/llvm/test/MC/Disassembler/AMDGPU/nop.txt index 0305765e6f5..d27c0bc6a58 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/nop.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/nop.txt @@ -2,3 +2,6 @@ # CHECK: v_nop ; encoding: [0x00,0x00,0x00,0x7e] 0x00 0x00 0x00 0x7e + +# CHECK: v_nop ; encoding: [0x00,0x00,0x00,0x7e] +0x80 0x00 0x00 0x7e diff --git a/llvm/test/MC/Disassembler/AMDGPU/vop1.txt b/llvm/test/MC/Disassembler/AMDGPU/vop1.txt index 02540848796..3e65f6142b7 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/vop1.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/vop1.txt @@ -3,6 +3,9 @@ # CHECK: v_nop ; encoding: [0x00,0x00,0x00,0x7e] 0x00 0x00 0x00 0x7e +# CHECK: v_nop ; encoding: [0x00,0x00,0x00,0x7e] +0x80 0x00 0x00 0x7e + # CHECK: v_clrexcp ; encoding: [0x00,0x6a,0x00,0x7e] 0x00 0x6a 0x00 0x7e diff --git a/llvm/test/MC/Disassembler/AMDGPU/vop1_vi.txt b/llvm/test/MC/Disassembler/AMDGPU/vop1_vi.txt index c42c0a62810..8e1a13e2589 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/vop1_vi.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/vop1_vi.txt @@ -6,6 +6,9 @@ # VI: v_nop ; encoding: [0x00,0x00,0x00,0x7e] 0x00 0x00 0x00 0x7e +# VI: v_nop ; encoding: [0x00,0x00,0x00,0x7e] +0x80 0x00 0x00 0x7e + # VI: v_clrexcp ; encoding: [0x00,0x6a,0x00,0x7e] 0x00 0x6a 0x00 0x7e |
