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* [llvm-mca] Add flag -instruction-tables to print the theoretical resource ↵Andrea Di Biagio2018-03-2616-707/+871
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pressure distribution for instructions (PR36874) The goal of this patch is to address most of PR36874. To fully fix PR36874 we need to split the "InstructionInfo" view from the "SummaryView". That would make easy to check the latency and rthroughput as well. The patch reuses all the logic from ResourcePressureView to print out the "instruction tables". We have an entry for every instruction in the input sequence. Each entry reports the theoretical resource pressure distribution. Resource pressure is uniformly distributed across all the processor resource units of a group. At the moment, the backend pipeline is not configurable, so the only way to fix this is by creating a different driver that simply sends instruction events to the resource pressure view. That means, we don't use the Backend interface. Instead, it is simpler to just have a different code-path for when flag -instruction-tables is specified. Once Clement addresses bug 36663, then we can port the "instruction tables" logic into a stage of our configurable pipeline. Updated the BtVer2 test cases (thanks Simon for the help). Now we pass flag -instruction-tables to each modified test. Differential Revision: https://reviews.llvm.org/D44839 llvm-svn: 328487
* [LLDB][PPC64] Fix TestGdbRemoteAuxvSupportPavel Labath2018-03-261-0/+15
| | | | | | | | | | | | | | | Summary: PPC64's auxvec has a special key that must be ignored. Reviewers: clayborg, labath Reviewed By: clayborg, labath Subscribers: alexandreyy, lbianc Differential Revision: https://reviews.llvm.org/D43771 Patch by Leandro Lupori <leandro.lupori@gmail.com>. llvm-svn: 328486
* Add a test for setting the load address of a module with differing ↵Pavel Labath2018-03-261-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | physical/virtual addresses Summary: First attempt at landing D42145 was reverted because it caused test failures on some android devices. It turned out this was because these devices had vdso modules with differing physical and virtual addresses. This was not caught earlier because all of the modules in our tests either lack physical addresses or have them identical to virtual ones. In the discussion on the patch, we came to the conclusion that in the scenario where we are merely setting a load address of a module (for example from a dynamic loader plugin), we should always use virtual addresses (i.e., preserve status quo). This patch adds a test to make sure we don't regress in that direction. Reviewers: owenpshaw Subscribers: lldb-commits Differential Revision: https://reviews.llvm.org/D44738 llvm-svn: 328485
* Test commit - adding a new line.Carlos Alberto Enciso2018-03-261-0/+1
| | | | llvm-svn: 328484
* [LoopUnroll] Fix dangling pointers in SCEVMax Kazantsev2018-03-262-28/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Current logic of loop SCEV invalidation in Loop Unroller implicitly relies on fact that exit count of outer loops cannot rely on exiting blocks of inner loops, which is true in current implementation of backedge taken count calculation but is wrong in general. As result, when we only forget the loop that we have just unrolled, we may still have cached data for its outer loops (in particular, exit counts) which keeps references on blocks of inner loop that could have been changed or even deleted. The attached test demonstrates a situaton when after unrolling of innermost loop the outermost loop contains a dangling pointer on non-existant block. The problem shows up when we apply patch https://reviews.llvm.org/D44677 that makes SCEV smarter about exit count calculation. I am not sure if the bug exists without this patch, it appears that now it is accidentally correct just because in practice exact backedge taken count for outer loops with complex control flow inside is never calculated. But when SCEV learns to do so, this problem shows up. This patch replaces existing logic of SCEV loop invalidation with a correct one, which happens to be invalidation of outermost loop (which also leads to invalidation of all loops inside of it). It is the only way to ensure that no outer loop keeps dangling pointers on removed blocks, or just outdated information that has changed after unrolling. Differential Revision: https://reviews.llvm.org/D44818 Reviewed By: samparker llvm-svn: 328483
* Revert r328386 "[X86] Fix Windows `i1 zeroext` conventions to use i8 instead ↵Hans Wennborg2018-03-269-91/+7
| | | | | | | | | | | | | | | of i32" This broke Chromium (see crbug.com/825748). It looks like mstorsjo's follow-up patch at D44876 fixes this, but let's revert back to green for now until that's ready to land. (Also reverts r328443.) > Both GCC and MSVC only look at the low byte of a boolean when it is > passed. llvm-svn: 328482
* [DeadArgElim] Strip allocsize attributes when deleting an argument.Benjamin Kramer2018-03-262-2/+19
| | | | | | | Since allocsize refers to the argument number it gets invalidated when an argument is removed and the numbers shift. llvm-svn: 328481
* [IRCE] Enable increasing loops of variable boundsSam Parker2018-03-263-64/+254
| | | | | | | | | | | | | | | | | | | | | CanBeMin is currently used which will report true for any unknown values, but often a check is performed outside the loop which covers this situation: for (int i = 0; i < N; ++i) ... if (N > 0) for (int i = 0; i < N; ++i) ... So I've add 'LoopGuardedAgainstMin' which reports whether N is greater than the minimum value which then allows loop with a variable loop count to be optimised. I've also moved the increasing bound checking into its own function and replaced SumCanReachMax is another isLoopEntryGuardedByCond function. llvm-svn: 328480
* This is PR36799.George Rimar2018-03-263-3/+68
| | | | | | | | | | | | | | | | Currently, we might have a bug with scripts like below: .foo : ALIGN(8) { *(.foo) } > ram because do not expand the memory region when doing ALIGN. This might result in file range overlaps. The patch fixes the issue. Differential revision: https://reviews.llvm.org/D44730 llvm-svn: 328479
* [ARM] Simplify constructing the ARMArchFeature string. NFC.Martin Storsjo2018-03-261-12/+9
| | | | | | Differential Revision: https://reviews.llvm.org/D44819 llvm-svn: 328478
* Fix test case initialization issues in permissions testEric Fiselier2018-03-261-1/+7
| | | | llvm-svn: 328477
* Implement filesystem::perm_options specified in NB comments.Eric Fiselier2018-03-266-60/+119
| | | | | | | | | | The NB comments for filesystem changed permissions and added a new enum `perm_options` which control how the permissions are applied. This implements than NB resolution llvm-svn: 328476
* Make filesystem tests generic between experimental and std versions.Eric Fiselier2018-03-26109-235/+192
| | | | | | | | | | | | | | | As I move towards implementing std::filesystem, there is a need to make the existing tests run against both the std and experimental versions. Additionally, it's helpful to allow running the tests against other implementations of filesystem. This patch converts the test to easily target either. First, it adds a filesystem_include.hpp header which is soley responsible for selecting and including the correct implementation. Second, it converts existing tests to use this header instead of including filesystem directly. llvm-svn: 328475
* [X86] Fix the SchedRW for intrinsic register form of SQRT/RCP/RSQRT.Craig Topper2018-03-263-38/+38
| | | | llvm-svn: 328474
* [X86] Merge the SSE and AVX versions of fp divs and sqrts in the ↵Craig Topper2018-03-268-203/+143
| | | | | | | | SandyBridge/Haswell/Broadwell/Skylake scheduler models. I've used Agner's data as best I could to get the values to converge on. llvm-svn: 328473
* [X86] Add itinerary to intrinsic version of sqrtss, rcpss, and rsqrtss ↵Craig Topper2018-03-263-10/+10
| | | | | | instructions. llvm-svn: 328472
* [X86] Correct the itineraries for the dot production instructions.Craig Topper2018-03-261-2/+2
| | | | llvm-svn: 328471
* [X86] Use the same itinerary for VCVTDQ2PD as the SSE version so that the ↵Craig Topper2018-03-261-8/+10
| | | | | | generated scheduler classes will merge. llvm-svn: 328470
* [X86] Swap the itineraries on the memory and register forms of CVTDQ2PD.Craig Topper2018-03-262-5/+6
| | | | | | They were backwards. llvm-svn: 328469
* [X86] Give VMOVSX/ZX the same itinerary as the SSE version so they'll reuse ↵Craig Topper2018-03-261-11/+6
| | | | | | the same generated scheduler class. llvm-svn: 328468
* [sanitizer] Make test compatible with DarwinVitaly Buka2018-03-262-3/+3
| | | | llvm-svn: 328467
* [X86] Give vpmsadbw the same itinerary as the SSE version so they'll be able ↵Craig Topper2018-03-251-7/+2
| | | | | | to share the same generated scheduler class. llvm-svn: 328466
* [X86] Move (v)movss to port 5 only for Skylake. Move (v)movups/d to port 015 ↵Craig Topper2018-03-253-13/+13
| | | | | | | | for Skylake. This matches Agner's data and is consistent with what the EVEX instructions were doing on SKX. llvm-svn: 328465
* [demangler] Use a back-patching scheme to resolve forward references.Erik Pilkington2018-03-253-82/+166
| | | | | | | | | | | | | | | Strictly in a conversion operator's type, a <template-param> refers to a <template-arg> that is further ahead in the mangled name. Instead of doing a second parse to resolve these, introduce a ForwardTemplateReference Node and back-patch the referenced <template-arg> when we're in the right context. This is also a correctness fix, previously we would only do a second parse if the <template-param> was out of bounds in the current set of <template-args>. This lead to misdemangles (gasp!) when the conversion operator was a member of a templated struct, for instance. llvm-svn: 328464
* [demangler] Tweak how parameter pack sizes are determined.Erik Pilkington2018-03-253-427/+220
| | | | | | | | Rather than eagerly propagating up parameter pack sizes in Node ctors, find the parameter pack size during printing. This is being done to support back-patching forward referencing <template-param>s. llvm-svn: 328463
* [demangler] Support for clang's enable_if attribute.Erik Pilkington2018-03-253-13/+75
| | | | | | Fixes PR33569. llvm-svn: 328462
* [PatternMatch] allow undef elements when matching vector FP +0.0Sanjay Patel2018-03-2514-46/+60
| | | | | | | | | | | | | This continues the FP constant pattern matching improvements from: https://reviews.llvm.org/rL327627 https://reviews.llvm.org/rL327339 https://reviews.llvm.org/rL327307 Several integer constant matchers also have this ability. I'm separating matching of integer/pointer null from FP positive zero and renaming/commenting to make the functionality clearer. llvm-svn: 328461
* [X86] Use WriteResPair for WriteIDiv to cleanup sched defs. NFCI.Simon Pilgrim2018-03-254-37/+10
| | | | llvm-svn: 328460
* [SchedModel] Remove instregex entries that don't match any instructionsSimon Pilgrim2018-03-251-2/+11
| | | | | | | | | | This patch throws a fatal error if an instregex entry doesn't actually match any instructions. This is part of the work to reduce the compile time impact of increased instregex usage (PR35955), although the x86 models seem to be relatively clean. All the cases I encountered have now been fixed in trunk and this will ensure they don't get reintroduced. Differential Revision: https://reviews.llvm.org/D44687 llvm-svn: 328459
* [X86][SkylakeClient] Fix missing commaSimon Pilgrim2018-03-251-1/+1
| | | | llvm-svn: 328458
* [ARM] Remove sched model instregex entries that don't match any instructions ↵Simon Pilgrim2018-03-253-41/+39
| | | | | | | | (D44687) Reviewed by @javed.absar llvm-svn: 328457
* [X86] Add missing full stop to comment. NFCI.Simon Pilgrim2018-03-251-1/+1
| | | | llvm-svn: 328456
* [InstSimplify, InstCombine] add/update tests with FP +0.0 vector with undef; NFCSanjay Patel2018-03-258-364/+423
| | | | llvm-svn: 328455
* [X86][SkylakeClient] Fix a set of regular expressions that were checking for ↵Craig Topper2018-03-251-18/+18
| | | | | | | | optionally starting with 'Y' instead of 'V' These bad regexs were introduced by r328435 llvm-svn: 328454
* [X86][MMX] MOVQ2DQ/MOVDQ2Q are better described as WriteVecMove than WriteMoveSimon Pilgrim2018-03-251-1/+1
| | | | | | Not that it makes a difference to current cost values, but will when we try to better model GPR-SIMD transfer costs llvm-svn: 328453
* [X86][SkylakeServer] Merge multiple instregex. NFCISimon Pilgrim2018-03-251-7/+7
| | | | llvm-svn: 328452
* [X86] Update cost model for Goldmont. Add fsqrt costs for SilvermontCraig Topper2018-03-254-23/+278
| | | | | | | | | | | | | | Add fdiv costs for Goldmont using table 16-17 of the Intel Optimization Manual. Also add overrides for FSQRT for Goldmont and Silvermont. Reviewers: RKSimon Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D44644 llvm-svn: 328451
* [InstCombine] adjust test comments; NFCSanjay Patel2018-03-251-9/+6
| | | | llvm-svn: 328450
* [InstCombine] consolidate casted icmp vector testsSanjay Patel2018-03-251-660/+43
| | | | | | | | We have thorough coverage of predicates and scalar types, so we just need a sampling of vector tests to show that things are working or not with vectors types. llvm-svn: 328449
* [InstCombine] peek through more icmp of FP cast + bitcastSanjay Patel2018-03-252-139/+59
| | | | | | This is an extension of rL328426 as noted in D44367. llvm-svn: 328448
* Remove reference to stale (2009) python version.Yaron Keren2018-03-251-1/+1
| | | | llvm-svn: 328447
* [X86] Add the ability to override memory folding latency to schedules and ↵Simon Pilgrim2018-03-256-29/+35
| | | | | | | | | | add 1uop for memory folds for Intel models The Intel models need an extra 1uop for memory folded instructions, plus a lot of instructions take a non-default memory latency which should allow us to use the multiclass a lot more to tidy things up. Differential Revision: https://reviews.llvm.org/D44840 llvm-svn: 328446
* avoid new/delete ellision in construct.pass.cppEric Fiselier2018-03-251-0/+4
| | | | llvm-svn: 328445
* [X86] Consistently prefix all defs in X86ScheduleSLM.td with 'SLM'.Craig Topper2018-03-251-79/+79
| | | | llvm-svn: 328444
* [X86] Update a partially stale comment, since SVN r328386. NFC.Martin Storsjo2018-03-241-1/+1
| | | | llvm-svn: 328443
* [SchedModel] Remove an unneeded temporary vector.Craig Topper2018-03-241-3/+2
| | | | llvm-svn: 328442
* [SchedModel] Use std::move in a couple places to reduce copyingCraig Topper2018-03-241-2/+3
| | | | llvm-svn: 328441
* [SchedModel] Use std::move to replace a vector instead of vector::swapCraig Topper2018-03-241-1/+1
| | | | | | We don't really care about the old vector value so we don't care to swap it. llvm-svn: 328440
* Fix module.modulemap after r328395Eric Fiselier2018-03-241-6/+0
| | | | | | | This patch removes the MachineValueType module since the header was removed in r328395. llvm-svn: 328439
* [SchedModel] Remove std::vectors that were created with 1 element and then ↵Craig Topper2018-03-241-8/+5
| | | | | | | | passed to an ArrayRef parameter. ArrayRef can capture a single element. We don't need a vector for that. llvm-svn: 328438
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