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| author | Craig Topper <craig.topper@intel.com> | 2018-03-26 02:17:14 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-03-26 02:17:14 +0000 |
| commit | 4367874bc5005b2134ccc27c201dfd2c7a7f0502 (patch) | |
| tree | 025f05d97e4930803415f7e4a7e5012b623189cd | |
| parent | 659f85af144d076f650972b02fd3314b08eec036 (diff) | |
| download | bcm5719-llvm-4367874bc5005b2134ccc27c201dfd2c7a7f0502.tar.gz bcm5719-llvm-4367874bc5005b2134ccc27c201dfd2c7a7f0502.zip | |
[X86] Use the same itinerary for VCVTDQ2PD as the SSE version so that the generated scheduler classes will merge.
llvm-svn: 328470
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrSSE.td | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index 99915e7c00a..323e3c60772 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -2016,23 +2016,25 @@ let hasSideEffects = 0, mayLoad = 1 in def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src), "vcvtdq2pd\t{$src, $dst|$dst, $src}", [(set VR128:$dst, - (v2f64 (X86VSintToFP (bc_v4i32 (loadv2i64 addr:$src)))))]>, - VEX, Sched<[WriteCvtI2FLd]>, VEX_WIG; + (v2f64 (X86VSintToFP (bc_v4i32 (loadv2i64 addr:$src)))))], + IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtI2FLd]>, VEX_WIG; def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "vcvtdq2pd\t{$src, $dst|$dst, $src}", [(set VR128:$dst, - (v2f64 (X86VSintToFP (v4i32 VR128:$src))))]>, - VEX, Sched<[WriteCvtI2F]>, VEX_WIG; + (v2f64 (X86VSintToFP (v4i32 VR128:$src))))], + IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtI2F]>, VEX_WIG; def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src), "vcvtdq2pd\t{$src, $dst|$dst, $src}", [(set VR256:$dst, - (v4f64 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))))]>, - VEX, VEX_L, Sched<[WriteCvtI2FLd]>, VEX_WIG; + (v4f64 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))))], + IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtI2FLd]>, + VEX_WIG; def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src), "vcvtdq2pd\t{$src, $dst|$dst, $src}", [(set VR256:$dst, - (v4f64 (sint_to_fp (v4i32 VR128:$src))))]>, - VEX, VEX_L, Sched<[WriteCvtI2F]>, VEX_WIG; + (v4f64 (sint_to_fp (v4i32 VR128:$src))))], + IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtI2F]>, + VEX_WIG; } let hasSideEffects = 0, mayLoad = 1 in |
