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* [ScheduleDAG] Add statistics for maintaining the topological order.Florian Hahn2019-04-101-0/+8
| | | | | | | | | | | | | This is helpful to measure the impact of D60125 on maintaining topological orders. Reviewers: MatzeB, atrick, efriedma, niravd Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D60187 llvm-svn: 358058
* Add REQUIRES: asserts to test using -debug-onlyDavid Stenberg2019-04-101-0/+1
| | | | llvm-svn: 358057
* [VPLAN] Minor improvement to testing and debug messages.Florian Hahn2019-04-104-9/+117
| | | | | | | | | | | | 1. Use computed VF for stress testing. 2. If the computed VF does not produce vector code (VF smaller than 2), force VF to be 4. 3. Test vectorization of i64 data on AArch64 to make sure we generate VF != 4 (on X86 that was already tested on AVX). Patch by Francesco Petrogalli <francesco.petrogalli@arm.com> Differential Revision: https://reviews.llvm.org/D59952 llvm-svn: 358056
* Docstringify some comments in the swig interface filesPavel Labath2019-04-103-4/+8
| | | | | | Without these, the comments don't end up in the generated python code. llvm-svn: 358055
* [DWARF] Simplify LineTable::findRowInSeqFangrui Song2019-04-101-35/+11
| | | | | | | | | | | | | | We want the last row whose address is less than or equal to Address. This can be computed as upper_bound - 1, which is simpler than lower_bound followed by skipping equal rows in a loop. Since FirstRow (LowPC) does not satisfy the predicate (OrderByAddress) while LastRow-1 (HighPC) satisfies the predicate. We can decrease the search range by two, i.e. upper_bound [FirstRow,LastRow) = upper_bound [FirstRow+1,LastRow-1) llvm-svn: 358053
* [InstCombine] Handle usubo always overflowNikita Popov2019-04-102-2/+6
| | | | | | | | | | | Check AlwaysOverflow condition for usubo. The implementation is the same as the existing handling for uaddo and umulo. Handling for saddo and ssubo will follow (smulo doesn't have the necessary ValueTracking support). Differential Revision: https://reviews.llvm.org/D60483 llvm-svn: 358052
* [InstCombine] Directly call computeOverflow methods in ↵Nikita Popov2019-04-101-6/+13
| | | | | | | | | OptimizeOverflowCheck; NFC Instead of using the willOverflow helpers. This makes it easier to extend handling of AlwaysOverflows. llvm-svn: 358051
* [InstCombine] Canonicalize (-X s/ Y) to -(X s/ Y).Chen Zheng2019-04-103-15/+21
| | | | | | Differential Revision: https://reviews.llvm.org/D60395 llvm-svn: 358050
* Rename a variable and add a comment.Rui Ueyama2019-04-102-3/+15
| | | | llvm-svn: 358049
* [CodeGen][ObjC] Emit the retainRV marker as a module flag instead ofAkira Hatanaka2019-04-102-9/+6
| | | | | | | | | | | | | | named metadata. This fixes a bug where ARC contract wasn't inserting the retainRV marker when LTO was enabled, which caused objects returned from a function to be auto-released. rdar://problem/49464214 Differential Revision: https://reviews.llvm.org/D60302 llvm-svn: 358048
* [ObjC][ARC] Convert the retainRV marker that is passed as a namedAkira Hatanaka2019-04-106-23/+17
| | | | | | | | | | | | | | | metadata into a module flag in the auto-upgrader and make the ARC contract pass read the marker as a module flag. This is needed to fix a bug where ARC contract wasn't inserting the retainRV marker when LTO was enabled, which caused objects returned from a function to be auto-released. rdar://problem/49464214 Differential Revision: https://reviews.llvm.org/D60303 llvm-svn: 358047
* [X86] Move the 2 byte VEX optimization for MOV instructions back to the ↵Craig Topper2019-04-104-54/+167
| | | | | | | | X86AsmParser::processInstruction where it used to be. Block when {vex3} prefix is present. Years ago I moved this to an InstAlias using VR128H/VR128L. But now that we support {vex3} pseudo prefix, we need to block the optimization when it is set to match gas behavior. llvm-svn: 358046
* [llvm-objdump] Don't print trailing space in dumpBytesFangrui Song2019-04-102-4/+8
| | | | | | | In disassembly output, dumpBytes prints a space, followed by a tab printed by printInstr. Remove the extra space. llvm-svn: 358045
* [lldb-server] Introduce Socket::Initialize and Terminate to simply WSASocket ↵Aaron Smith2019-04-108-50/+55
| | | | | | | | | | | | | | | | setup Reviewers: zturner, labath Reviewed By: labath Subscribers: lldb-commits Tags: #lldb Differential Revision: https://reviews.llvm.org/D60440 llvm-svn: 358044
* [llvm-objdump] Accept and ignore --wide/-wFangrui Song2019-04-101-0/+4
| | | | | | | | | This is similar to what we do for llvm-readobj (--wide/-W is for GNU readelf compatibility). The test will be added in D60376. llvm-svn: 358043
* [Sparc] Fix incorrect MI insertion position for spilling f128.Jim Lin2019-04-102-2/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Obviously, new built MI (sethi+add or sethi+xor+add) for constructing large offset should be inserted before new created MI for storing even register into memory. So the insertion position should be *StMI instead of II. before fixed: std %f0, [%g1+80] sethi 4, %g1 <<< add %g1, %sp, %g1 <<< this two instructions should be put before "std %f0, [%g1+80]". sethi 4, %g1 add %g1, %sp, %g1 std %f2, [%g1+88] after fixed: sethi 4, %g1 add %g1, %sp, %g1 std %f0, [%g1+80] sethi 4, %g1 add %g1, %sp, %g1 std %f2, [%g1+88] Reviewers: venkatra, jyknight Reviewed By: jyknight Subscribers: jyknight, fedor.sergeev, jrtc27, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60397 llvm-svn: 358042
* [X86] Support the EVEX versions vcvt(t)ss2si and vcvt(t)sd2si with the ↵Craig Topper2019-04-103-120/+115
| | | | | | | | | | | | {evex} pseudo prefix in the assembler. The EVEX versions are ambiguous with the VEX versions based on operands alone so we had explicitly dropped them from the AsmMatcher table. Unfortunately, when we add them they incorrectly show in the table before their VEX counterparts. This is different how the prioritization normally works. To fix this we have to explicitly reject the instructions unless the {evex} prefix has been seen. llvm-svn: 358041
* [X86] Add VEX_LIG to scalar VEX/EVEX instructions that were missing it.Craig Topper2019-04-092-39/+40
| | | | | | | | | | Scalar VEX/EVEX instructions don't use the L bit and don't look at it for decoding either. So we should ignore it in our disassembler. The missing instructions here were found by grepping the raw tablegen class definitions in the tablegen debug output. llvm-svn: 358040
* [LLVM-C] Correct The Current Debug Location AccessorsRobert Widmann2019-04-092-2/+45
| | | | | | | | | | | | | | | | Summary: Deprecate the existing accessors for the "current debug location" of an IRBuilder. The setter could not handle being reset to NULL, and the getter would create bogus metadata if the NULL location was returned. Provide direct metadata-based accessors instead. Reviewers: whitequark, deadalnix Reviewed By: whitequark Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60484 llvm-svn: 358039
* [LLVM-C] Add Bindings to Access an Instruction's DebugLocRobert Widmann2019-04-092-0/+27
| | | | | | | | | | | | | | | | Summary: Provide direct accessors to supplement LLVMSetInstDebugLocation. In addition, properly accept and return the NULL location. The old accessors provided no way to do this, so the current debug location cannot currently be cleared. Reviewers: whitequark, deadalnix Reviewed By: whitequark Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60481 llvm-svn: 358038
* [LLVM-C] Add Section and Symbol Iterator Accessors for Object File BinariesRobert Widmann2019-04-093-32/+122
| | | | | | | | | | | | | | | | Summary: This brings us to full feature parity with the old API, so I've deprecated it and updated the tests. I'll do a follow-up patch to do some more cleanup and documentation work in this header. Reviewers: whitequark, deadalnix Reviewed By: whitequark Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60407 llvm-svn: 358037
* [X86] Fix a dangling StringRef issue introduced in r358029.Craig Topper2019-04-091-3/+4
| | | | | | | | I was attempting to convert mnemonics to lower case after processing a pseudo prefix. But the ParseOperands just hold a StringRef for tokens so there is no where to allocate the memory. Add FIXMEs for the lower case issue which also exists in the prefix parsing code. llvm-svn: 358036
* [AArch64][GlobalISel] Add isel support for vector G_ICMP and G_ASHR & G_SHLAmara Emerson2019-04-093-2/+3729
| | | | | | | | | | | | | | | | The selection for G_ICMP is unfortunately not currently importable from SDAG due to the use of custom SDNodes. To support this, this selection method has an opcode table which has been generated by a script, indexed by various instruction properties. Ideally in future we will have a GISel native selection patterns that we can write in tablegen to improve on this. For selection of some types we also need support for G_ASHR and G_SHL which are generated as a result of legalization. This patch also adds support for them, generating the same code as SelectionDAG currently does. Differential Revision: https://reviews.llvm.org/D60436 llvm-svn: 358035
* [AArch64][GlobalISel] Legalize vector G_ICMP.Amara Emerson2019-04-095-8/+1984
| | | | | | | | Selection support will be coming in a later patch. Differential Revision: https://reviews.llvm.org/D60435 llvm-svn: 358034
* [AArch64][GlobalISel] Add legalization for some vector G_SHL and G_ASHR.Amara Emerson2019-04-094-5/+44
| | | | | | | | This is needed for some future support for vector ICMP. Differential Revision: https://reviews.llvm.org/D60433 llvm-svn: 358033
* [GlobalISel][AArch64] Allow CallLowering to handle types which are normallyAmara Emerson2019-04-098-16/+155
| | | | | | | | | | | required to be passed as different register types. E.g. <2 x i16> may need to be passed as a larger <2 x i32> type, so formal arg lowering needs to be able truncate it back. Likewise, when dealing with returns of these types, they need to be widened in the appropriate way back. Differential Revision: https://reviews.llvm.org/D60425 llvm-svn: 358032
* [InstCombine] Add with.overflow always overflow tests; NFCNikita Popov2019-04-091-0/+79
| | | | | | | | The uadd and umul cases are currently handled, the usub, sadd, ssub and smul cases are not. usub, sadd and ssub already have the necessary ValueTracking support, smul doesn't. llvm-svn: 358031
* [AArch64] Add test case to show missed opportunity to remove a shift before ↵Craig Topper2019-04-091-0/+21
| | | | | | | | tbnz when the shift has been zero extended from i32 to i64. NFC This pattern showed up in D60358 and it was suggested I had a test and fix that separately. llvm-svn: 358030
* [X86] Add support for {vex2}, {vex3}, and {evex} to the assembler to match ↵Craig Topper2019-04-096-705/+823
| | | | | | | | | | | | | | | | gas. Use {evex} to improve the one our 32-bit AVX512 tests. These can be used to force the encoding used for instructions. {vex2} will fail if the instruction is not VEX encoded, but otherwise won't do anything since we prefer vex2 when possible. Might need to skip use of the _REV MOV instructions for this too, but I haven't done that yet. {vex3} will force the instruction to use the 3 byte VEX encoding or fail if there is no VEX form. {evex} will force the instruction to use the EVEX version or fail if there is no EVEX version. Differential Revision: https://reviews.llvm.org/D59266 llvm-svn: 358029
* [pstl][CMake] Install CMake export filesLouis Dionne2019-04-092-15/+35
| | | | | | | This allows other projects to depend on PSTL using the classic CMake find_package protocol. llvm-svn: 358028
* [DAGCombiner][X86][SystemZ] Canonicalize SSUBO with immediate RHS to SADDO ↵Craig Topper2019-04-094-14/+32
| | | | | | | | | | by negating the immediate. This lines up with what we do for regular subtract and it matches up better with X86 assumptions in isel patterns that add with immediate is more canonical than sub with immediate. Differential Revision: https://reviews.llvm.org/D60020 llvm-svn: 358027
* Revert "[InstCombine] [InstCombine] Canonicalize (-X s/ Y) to -(X s/ Y)."Nikita Popov2019-04-092-15/+9
| | | | | | | | | | | This reverts commit 1383a9168948aabfd827220c9445ce0ce5765800. sdiv-canonicalize.ll fails after this revision. The fold needs to be moved outside the branch handling constant operands. However when this is done there are further test changes, so I'm reverting this in the meantime. llvm-svn: 358026
* [InstCombine] Restructure OptimizeOverflowCheck; NFCNikita Popov2019-04-091-31/+28
| | | | | | | | | Change the code to always handle the unsigned+signed cases together with the same basic structure for add/sub/mul. The simple folds are always handled first and then the ValueTracking overflow checks are used. llvm-svn: 358025
* Remove the unit at a time optionEric Christopher2019-04-092-7/+0
| | | | | | | | Removes the code from opt and the pass manager builder. The code was unused - even by the C library code that was supposed to set it and had been removed previously. llvm-svn: 358024
* [TSan][libdispatch] Replace CFRunLoop with dispatch_semaphore, pt. 1Julian Lettner2019-04-096-53/+54
| | | | | | | | | | | | Remove the dependency on Foundation so we can start running those tests on other platforms. Rename/move of tests will be done in a separate commit. Reviewed By: kubamracek, dvyukov Differential Revision: https://reviews.llvm.org/D60347 llvm-svn: 358023
* [PDB Docs] Clarifications and fixes for DBI Stream.Zachary Turner2019-04-091-41/+58
| | | | llvm-svn: 358022
* Update modulemaps for Analysis/VecFuncs.def.Kristina Brooks2019-04-091-0/+1
| | | | | | | | | | | | Avoid a warning while building modular LLVM due to a new textual header missing in the modulemap: TargetLibraryInfo.cpp:1485:6: warning: missing submodule 'LLVM_Analysis.VecFuncs' [-Wincomplete-umbrella] Added VecFuncs.def as a textual header in LLVM_Analysis. llvm-svn: 358021
* [ValueTracking] Use computeConstantRange() for signed sub overflow determinationNikita Popov2019-04-093-12/+10
| | | | | | | | | | This is the same change as D60420 but for signed sub rather than signed add: Range information is intersected into the known bits result, allows to detect more no/always overflow conditions. Differential Revision: https://reviews.llvm.org/D60469 llvm-svn: 358020
* [TargetLowering] SimplifyDemandedBits - add ISD::INSERT_SUBVECTOR supportSimon Pilgrim2019-04-092-16/+50
| | | | llvm-svn: 358019
* [pstl][NFC] Move the ParallelSTLConfig template to the cmake/ subdirectoryLouis Dionne2019-04-092-1/+1
| | | | llvm-svn: 358018
* [InstCombine] [InstCombine] Canonicalize (-X s/ Y) to -(X s/ Y).Chen Zheng2019-04-092-9/+15
| | | | | | Differential Revision: https://reviews.llvm.org/D60395 llvm-svn: 358017
* [OPENMP]Allow allocate directive on parameters.Alexey Bataev2019-04-092-3/+14
| | | | | | Patch allows to use allocate directives on the function parameters. llvm-svn: 358016
* Revert LIS handling in MachineDCEStanislav Mekhanoshin2019-04-094-80/+91
| | | | | | | | | | One of out of tree targets has regressed with this patch. Reverting it for now and let liveness to be fully reconstructed in case pass was used after the LIS is created to resolve the regression. Differential Revision: https://reviews.llvm.org/D60466 llvm-svn: 358015
* [ValueTracking] Use computeConstantRange() in signed add overflow determinationNikita Popov2019-04-097-16/+15
| | | | | | | | | | | | | This is D59386 for the signed add case. The computeConstantRange() result is now intersected into the existing known bits information, allowing to detect additional no-overflow/always-overflow conditions (though the latter isn't used yet). This (finally...) covers the motivating case from D59071. Differential Revision: https://reviews.llvm.org/D60420 llvm-svn: 358014
* [InstCombine] prevent possible miscompile with sdiv+negate of vector opSanjay Patel2019-04-092-14/+18
| | | | | | | | | | | Similar to: rL358005 Forego folding arbitrary vector constants to fix a possible miscompile bug. We can enhance the transform if we do want to handle the more complicated vector case. llvm-svn: 358013
* [DWARF] DWARFDebugLine: replace Sequence::orderByLowPC with orderByHighPCFangrui Song2019-04-092-35/+13
| | | | | | | In a sorted list of non-overlapping [LowPC,HighPC) ranges, locating an address with upper_bound on HighPC is simpler than lower_bound on LowPC. llvm-svn: 358012
* [scudo][standalone] Add flags & related parsersKostya Kortchinsky2019-04-099-0/+510
| | | | | | | | | | | | | | | | | | | | | | | Summary: As with other Sanitizers, and the current version of Scudo, we can provide flags in differents way: at compile time, through a weak function, through an environment variable. This change adds support for the configuration flags, and the string parsers. Those are fairly similar to the sanitizer_common way of doing things. Reviewers: morehouse, hctim, vitalybuka Reviewed By: morehouse, vitalybuka Subscribers: mgorny, delcypher, jdoerfert, #sanitizers, llvm-commits Tags: #llvm, #sanitizers Differential Revision: https://reviews.llvm.org/D59597 llvm-svn: 358011
* [InstCombine] add tests for sdiv with negated dividend and constant divisor; NFCSanjay Patel2019-04-091-12/+97
| | | | llvm-svn: 358010
* [CMake] Fix statically linking in libcxxabi if built separatelyMartin Storsjo2019-04-091-2/+2
| | | | | | | | | | | In this case, CMake doesn't know about the c++abi target within the same CMake run. This reverts this aspect back to how it was before SVN r357811. Differential Revision: https://reviews.llvm.org/D60448 llvm-svn: 358009
* [InstCombine] add tests for sdiv-by-int-min; NFCSanjay Patel2019-04-091-0/+30
| | | | llvm-svn: 358008
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