summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* [x86] avoid infinite loop from SoftenFloatOperand (PR34866)Sanjay Patel2017-10-112-0/+70
| | | | | | | | | Legalization of fp128 assumes things that we should have asserts for, so that's another potential improvement. Differential Revision: https://reviews.llvm.org/D38771 llvm-svn: 315485
* Reland "[llvm-objcopy] Add support for --strip-sections to remove all ↵Jake Ehrlich2017-10-114-22/+118
| | | | | | | | | | | | | | | | | | | | | section headers leaving only program headers and loadable segment data" ubsan caught an issue I made where I was converting a null pointer to a reference. elf utils implements a particularly extreme form of stripping that I'd like to support. eu-strip has an option called "strip-sections" that removes all section headers and leaves only program headers and the segment data. I have implemented this option partly as a test but mainly because in Fuchsia we would like to use this option to minimize the size of our executables. The other strip options that are on my list include --strip-all and --strip-debug. This is a preliminary implementation that I'd like to start using in Fuchsia builds if possible. This change implements such a stripping option for llvm-objcopy Differential Revision: https://reviews.llvm.org/D38335 llvm-svn: 315484
* Convert the last uses of ErrorOr in include/llvm/Object.Rafael Espindola2017-10-114-21/+25
| | | | llvm-svn: 315483
* [NFC] update test case so checks are not order dependent when not neededLei Huang2017-10-111-5/+5
| | | | llvm-svn: 315482
* Remove unused include.Rafael Espindola2017-10-111-1/+0
| | | | llvm-svn: 315481
* Convert the last uses of ErrorOr in COFF.h.Rafael Espindola2017-10-112-11/+10
| | | | llvm-svn: 315480
* [asan] Tweak test output to diagnose buildbot failures.Evgeniy Stepanov2017-10-111-2/+6
| | | | llvm-svn: 315479
* Update for llvm change.Rafael Espindola2017-10-111-5/+2
| | | | llvm-svn: 315478
* Convert a few ErrorOr to Expected.Rafael Espindola2017-10-113-14/+14
| | | | llvm-svn: 315477
* [NFC] Convert OptimizationRemarkEmitter old emit() calls to new closureVivek Pandya2017-10-1123-373/+533
| | | | | | | | | | | | | | parameterized emit() calls Summary: This is not functional change to adopt new emit() API added in r313691. Reviewed By: anemet Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38285 llvm-svn: 315476
* Convert a couple of ErrorOr to Expected. NFC.Rafael Espindola2017-10-112-10/+12
| | | | llvm-svn: 315475
* Remove an unused include.Rafael Espindola2017-10-111-1/+0
| | | | llvm-svn: 315474
* Convert an ErrorOr to Expected.Rafael Espindola2017-10-114-12/+18
| | | | | | | getRelocationAddend should never be called on non SHT_RELA sections, but changing that requires changing RelocVisitor.h. llvm-svn: 315473
* [Hexagon] Handle non-immediate operands to A2_addi in getIncrementValueKrzysztof Parzyszek2017-10-111-4/+6
| | | | llvm-svn: 315472
* Spelling mistake in comment. NFCI.Simon Pilgrim2017-10-111-1/+1
| | | | llvm-svn: 315471
* [X86] Correct type for argument to clflushopt intrinsic.Craig Topper2017-10-112-2/+2
| | | | | | | | | | | | | | Summary: According to Intel docs this should take void const *. We had char*. The lack of const is the main issue. Reviewers: RKSimon, zvi, igorb Reviewed By: igorb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38782 llvm-svn: 315470
* [X86] Remove MVT::i1 handling code from LowerTRUNCATECraig Topper2017-10-111-8/+0
| | | | | | | | | | | | | | Summary: I don't think this is necessary with i1 being illegal now. Reviewers: RKSimon, zvi, guyblank Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38784 llvm-svn: 315469
* [Pipeliner] Fix offset value for instrs dependent on post-inc load/storesKrzysztof Parzyszek2017-10-112-10/+16
| | | | | | | | | | | | The software pipeliner and the packetizer try to break dependence between the post-increment instruction and the dependent memory instructions by changing the base register and the offset value. However, in some cases, the existing logic didn't work properly and created incorrect offset value. Patch by Jyotsna Verma. llvm-svn: 315468
* [OPENMP] Remove extra if, NFC.Alexey Bataev2017-10-111-1/+1
| | | | llvm-svn: 315467
* [Pipeliner] Improve serialization order for post-incrementsKrzysztof Parzyszek2017-10-115-14/+157
| | | | | | | | | | | | | | | | | | | The pipeliner is generating a serial sequence that causes poor register allocation when a post-increment instruction appears prior to the use of the post-increment register. This occurs when there is a circular set of dependences involved with a sequence of instructions in the same cycle. In this case, there is no serialization of the parallel semantics that will not cause an additional register to be allocated. This patch fixes the problem by changing the instructions so that the post-increment instruction is used by the subsequent instruction, which enables the register allocator to make a better decision and not require another register. Patch by Brendon Cahoon. llvm-svn: 315466
* Reland "[clang-fuzzer] Allow building without coverage instrumentation."Matt Morehouse2017-10-113-54/+83
| | | | | | This relands r315336 after fixing bot breakage. llvm-svn: 315465
* [OPENMP] Fix PR34916: Crash on mixing taskloop|tasks directives.Alexey Bataev2017-10-113-3/+22
| | | | | | | | If both taskloop and task directives are used at the same time in one program, we may ran into the situation when the particular type for task directive is reused for taskloop directives. Patch fixes this problem. llvm-svn: 315464
* [clang-fuzzer] Fix shared library dependencies.Matt Morehouse2017-10-113-3/+5
| | | | llvm-svn: 315463
* [Analyzer] Clarify error messages for undefined resultDaniel Marjamaki2017-10-115-64/+99
| | | | | | Differential Revision: https://reviews.llvm.org/D30295 llvm-svn: 315462
* [InstCombine] add baseline tests for D38531; NFCSanjay Patel2017-10-111-1/+103
| | | | llvm-svn: 315461
* [DAGCombiner] convert insertelement of bitcasted vector into shuffleSanjay Patel2017-10-113-51/+77
| | | | | | | | | | | | | | | | Eg: insert v4i32 V, (v2i16 X), 2 --> shuffle v8i16 V', X', {0,1,2,3,8,9,6,7} This is a generalization of the IR fold in D38316 to handle insertion into a non-undef vector. We may want to abandon that one if we can't find value in squashing the more specific pattern sooner. We're using the existing legal shuffle target hook to avoid AVX512 horror with vXi1 shuffles. There may be room for improvement in the shuffle lowering here, but that would be follow-up work. Differential Revision: https://reviews.llvm.org/D38388 llvm-svn: 315460
* [clang-rename] Add more unittest.Haojian Wu2017-10-111-0/+118
| | | | llvm-svn: 315459
* Revert "[dsymutil] Timestmap verification for __swift_ast"Jonas Devlieghere2017-10-117-74/+23
| | | | | | This reverts commit r315456. llvm-svn: 315458
* [TargetLowering] Correctly track NumFixedArgs field of CallLoweringInfoAlex Bradbury2017-10-112-2/+3
| | | | | | | | | | | | | | | | | | | | | The NumFixedArgs field of CallLoweringInfo is used by TargetLowering::LowerCallTo to determine whether a given argument is passed using the vararg calling convention or not (specifically, to set IsFixed for each ISD::OutputArg). Firstly, CallLoweringInfo::setLibCallee and CallLoweringInfo::setCallee both incorrectly set NumFixedArgs based on the _previous_ args list. Secondly, TargetLowering::LowerCallTo failed to increment NumFixedArgs when modifying the argument list so a pointer is passed for the return value. If your backend uses the IsFixed property or directly accesses NumFixedArgs, it is _possible_ this change could result in codegen changes (although the previous behaviour would have been incorrect). No such cases have been identified during code review for any in-tree architecture. Differential Revision: https://reviews.llvm.org/D37898 llvm-svn: 315457
* [dsymutil] Timestmap verification for __swift_astJonas Devlieghere2017-10-117-23/+74
| | | | | | | | | | | | This patch adds timestamp verification for swiftmodule files. - A new flag is provided to allows us to continue testing of the code for embedding the__swift_ast. (git doesn't maintain timestamps) - Adds a new test for fat (arm) binaries. Differential revision: https://reviews.llvm.org/D38686 llvm-svn: 315456
* [RISCV] Fix build after r315327Alex Bradbury2017-10-113-6/+10
| | | | | | | Differential Revision: https://reviews.llvm.org/D38779 Patch by Chih-Mao Chen. llvm-svn: 315455
* [mips] Add missing tests from rL315451Simon Dardis2017-10-114-0/+704
| | | | llvm-svn: 315454
* [OpenCL] Allow function declaration with empty argument list.Alexey Bader2017-10-114-4/+9
| | | | | | | | | | | | | | | | Treat 'f()' as 'f(void)' rather than a function w/o a prototype. Reviewers: Anastasia, yaxunl Reviewed By: Anastasia, yaxunl Subscribers: cfe-commits, echuraev, chapuni Differential Revision: https://reviews.llvm.org/D33681 Re-apply revision 306653. llvm-svn: 315453
* [clang-rename] Don't add prefix qualifiers to the declaration and definition ↵Haojian Wu2017-10-112-40/+59
| | | | | | | | | | | | | | of the renamed symbol. Reviewers: ioeric Reviewed By: ioeric Subscribers: klimek, cfe-commits, arphaman Differential Revision: https://reviews.llvm.org/D38723 llvm-svn: 315452
* [mips] Add support for parsing target specific flags for MIRSimon Dardis2017-10-112-0/+42
| | | | | | | | Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D38620 llvm-svn: 315451
* llvm/module.modulemap: Create LLVM_MC_TableGen. It is used by llvm-tblgen.NAKAMURA Takumi2017-10-111-0/+10
| | | | llvm-svn: 315450
* llvm/module.modulemap: Move Support_TargetRegistry to let LLVMSupport free ↵NAKAMURA Takumi2017-10-111-6/+7
| | | | | | from MC. llvm-svn: 315449
* [NFC] Fix variables used only for assert in GVNMax Kazantsev2017-10-111-6/+6
| | | | llvm-svn: 315448
* [llvm-rc] Fix spelling in messageSimon Dardis2017-10-111-1/+1
| | | | llvm-svn: 315447
* [TableGen] Tidy up CodeGenSchedule.cppJaved Absar2017-10-111-13/+13
| | | | | | Use range_loop where it simplifies. llvm-svn: 315446
* [Asm] Add debug tracing in table-generated assembly matcherOliver Stannard2017-10-1116-30/+122
| | | | | | | | | | | | | This adds debug tracing to the table-generated assembly instruction matcher, enabled by the -debug-only=asm-matcher option. The changes in the target AsmParsers are to add an MCInstrInfo reference under a consistent name, so that we can use it from table-generated code. This was already being used this way for targets that use deprecation warnings, but 5 targets did not have it, and Hexagon had it under a different name to the other backends. llvm-svn: 315445
* Fix dumping of characters with non-standard sizesPetr Pavlu2017-10-114-93/+176
| | | | | | | | | | | | | | | | * Prevent dumping of characters in DumpDataExtractor() with item_byte_size bigger than 8 bytes. This case is not supported by the code and results in a crash because the code calls DataExtractor::GetMaxU64Bitfield() -> GetMaxU64() that asserts for byte size > 8 bytes. * Teach DataExtractor::GetMaxU64(), GetMaxU32(), GetMaxS64() and GetMaxU64_unchecked() how to handle byte sizes that are not a multiple of 2. This allows DumpDataExtractor() to dump characters and booleans with item_byte_size in the interval of [1, 8] bytes. Values that are not a multiple of 2 would previously result in a crash because they were not handled by GetMaxU64(). llvm-svn: 315444
* [X86] Added tests for TESTM and TESTNM (NFC)Uriel Korach2017-10-114-0/+1148
| | | | | | | | Adding this test files now so after another commit that will add a new pattern for TESTM and TESTNM instructions will show the improvemnts that have been done. Change-Id: If3908b7f91897d764053312365a2bc1de78b291d llvm-svn: 315443
* [ELF] - Fix out of sync comment. NFC.George Rimar2017-10-111-1/+1
| | | | llvm-svn: 315442
* [ELF] - Do not set output section flags except SHF_{ALLOC,WRITE,EXECINSTR}.George Rimar2017-10-113-4/+59
| | | | | | | | | | | | | | | | | | | | | | | This is PR34546. Currently LLD creates output sections even if it has no input sections, but its command contains an assignment. Committed code just assigns the same flag that was used in previous live section. That does not work sometimes. For example if we have following script: .ARM.exidx : { *(.ARM.exidx*) } .foo : { _foo = 0; } } Then first section has SHF_LINK_ORDER flag. But section foo should not. That was a reason of crash in OutputSection::finalize(). LLD tried to calculate Link value, calling front() on empty input sections list. We should only keep access flags and omit all others when creating such sections. Patch fixes the crash observed. Differential revision: https://reviews.llvm.org/D37736 llvm-svn: 315441
* [GVN] Prevent LoadPRE from hoisting across instructions that don't pass ↵Max Kazantsev2017-10-114-0/+258
| | | | | | | | | | | | | | | | | | control flow to successors This patch fixes the miscompile that happens when PRE hoists loads across guards and other instructions that don't always pass control flow to their successors. PRE is now prohibited to hoist across such instructions because there is no guarantee that the load standing after such instruction is still valid before such instruction. For example, a load from under a guard may be invalid before the guard in the following case: int array[LEN]; ... guard(0 <= index && index < LEN); use(array[index]); Differential Revision: https://reviews.llvm.org/D37460 llvm-svn: 315440
* Revert r314955: "Remove PendingBody mechanism for function and ObjC method ↵Daniel Jasper2017-10-115-122/+79
| | | | | | | | | | | deserialization." This is breaking a build of https://github.com/abseil/abseil-cpp and so likely not really NFC. Also reverted subsequent r314956/7. I'll forward reproduction instructions to Richard. llvm-svn: 315439
* [LICM] Disallow sinking of unordered atomic loads into loopsMax Kazantsev2017-10-112-5/+104
| | | | | | | | | | | | | | | | | | | | | | | | Sinking of unordered atomic load into loop must be disallowed because it turns a single load into multiple loads. The relevant section of the documentation is: http://llvm.org/docs/Atomics.html#unordered, specifically the Notes for Optimizers section. Here is the full text of this section: > Notes for optimizers > In terms of the optimizer, this **prohibits any transformation that > transforms a single load into multiple loads**, transforms a store into > multiple stores, narrows a store, or stores a value which would not be > stored otherwise. Some examples of unsafe optimizations are narrowing > an assignment into a bitfield, rematerializing a load, and turning loads > and stores into a memcpy call. Reordering unordered operations is safe, > though, and optimizers should take advantage of that because unordered > operations are common in languages that need them. Patch by Daniil Suchkov! Reviewed By: reames Differential Revision: https://reviews.llvm.org/D38392 llvm-svn: 315438
* [IRCE] Do not process empty safe rangesMax Kazantsev2017-10-113-9/+85
| | | | | | | | | | | | | | | IRCE should not apply when the safe iteration range is proved to be empty. In this case we do unneeded job creating pre/post loops and then never go to the main loop. This patch makes IRCE not apply to empty safe ranges, adds test for this situation and also modifies one of existing tests where it used to happen slightly. Reviewed By: anna Differential Revision: https://reviews.llvm.org/D38577 llvm-svn: 315437
* Do not copy Sections vector.Rui Ueyama2017-10-111-1/+1
| | | | llvm-svn: 315436
OpenPOWER on IntegriCloud