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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-10-11 16:10:05 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-10-11 16:10:05 +0000 |
| commit | 7db366630c003ecf1d5effeda5ebea2f7fa2f2b9 (patch) | |
| tree | ec68031066639c692b6ca43327d78db94c8fd658 | |
| parent | 189576f80eb9449420380b46bffc35856a619819 (diff) | |
| download | bcm5719-llvm-7db366630c003ecf1d5effeda5ebea2f7fa2f2b9.tar.gz bcm5719-llvm-7db366630c003ecf1d5effeda5ebea2f7fa2f2b9.zip | |
Spelling mistake in comment. NFCI.
llvm-svn: 315471
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 4813763465a..f95603e9fef 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -8026,7 +8026,7 @@ static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op, // If this node promotes - by concatenating zeroes - the type of the result // of a node with instruction that zeroes all upper (irrelevant) bits of the // output register, mark it as legal and catch the pattern in instruction - // selection to avoid emitting extra insturctions (for zeroing upper bits). + // selection to avoid emitting extra instructions (for zeroing upper bits). if (SDValue Promoted = isTypePromotionOfi1ZeroUpBits(Op)) { SDValue ZeroC = DAG.getIntPtrConstant(0, dl); SDValue AllZeros = getZeroVector(ResVT, Subtarget, DAG, dl); |
