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authorKrzysztof Parzyszek <kparzysz@codeaurora.org>2017-10-11 15:59:51 +0000
committerKrzysztof Parzyszek <kparzysz@codeaurora.org>2017-10-11 15:59:51 +0000
commit12bdcab59c7ed91475b2f9cd25f45e72b5d1f9f1 (patch)
treed050f64fca87108c93a6bd93eb27bf4893b42a6a
parent3a03a7f6365ae85644ed61a6c6d45bdb8da77305 (diff)
downloadbcm5719-llvm-12bdcab59c7ed91475b2f9cd25f45e72b5d1f9f1.tar.gz
bcm5719-llvm-12bdcab59c7ed91475b2f9cd25f45e72b5d1f9f1.zip
[Pipeliner] Fix offset value for instrs dependent on post-inc load/stores
The software pipeliner and the packetizer try to break dependence between the post-increment instruction and the dependent memory instructions by changing the base register and the offset value. However, in some cases, the existing logic didn't work properly and created incorrect offset value. Patch by Jyotsna Verma. llvm-svn: 315468
-rw-r--r--llvm/lib/CodeGen/MachinePipeliner.cpp11
-rw-r--r--llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp15
2 files changed, 16 insertions, 10 deletions
diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp
index 20141f7f8d6..c852c2e1564 100644
--- a/llvm/lib/CodeGen/MachinePipeliner.cpp
+++ b/llvm/lib/CodeGen/MachinePipeliner.cpp
@@ -3892,9 +3892,14 @@ void SwingSchedulerDAG::fixupRegisterOverlaps(std::deque<SUnit *> &Instrs) {
unsigned BasePos, OffsetPos;
// Update the base register and adjust the offset.
if (TII->getBaseAndOffsetPosition(*MI, BasePos, OffsetPos)) {
- MI->getOperand(BasePos).setReg(NewBaseReg);
- int64_t Offset = MI->getOperand(OffsetPos).getImm();
- MI->getOperand(OffsetPos).setImm(Offset - It->second.second);
+ MachineInstr *NewMI = MF.CloneMachineInstr(MI);
+ NewMI->getOperand(BasePos).setReg(NewBaseReg);
+ int64_t NewOffset =
+ MI->getOperand(OffsetPos).getImm() - It->second.second;
+ NewMI->getOperand(OffsetPos).setImm(NewOffset);
+ SU->setInstr(NewMI);
+ MISUnitMap[NewMI] = SU;
+ NewMIs.insert(NewMI);
}
}
OverlapReg = 0;
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index c2125bec3a5..5e2cfbd531a 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -1651,13 +1651,14 @@ bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint(
bool HexagonInstrInfo::getIncrementValue(const MachineInstr &MI,
int &Value) const {
if (isPostIncrement(MI)) {
- // For a post-increment, the offset is zero and the increment value is
- // determined by the instruction's access size.
- int Zero;
- unsigned AccessSize;
- bool RetVal = getBaseAndOffset(MI, Zero, AccessSize);
- Value = (int) AccessSize;
- return RetVal;
+ unsigned BasePos = 0, OffsetPos = 0;
+ if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
+ return false;
+ const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
+ if (OffsetOp.isImm()) {
+ Value = OffsetOp.getImm();
+ return true;
+ }
}
if (MI.getOpcode() == Hexagon::A2_addi) {
Value = MI.getOperand(2).getImm();
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