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* [DarwinLog] Remove other dead code. Found while reading this file.Davide Italiano2017-12-101-54/+0
| | | | llvm-svn: 320338
* [MachException] Garbage collect unused and dead code.Davide Italiano2017-12-101-27/+0
| | | | llvm-svn: 320337
* [ScopBuilder] Fix typo. NFC.Michael Kruse2017-12-101-4/+4
| | | | | | | | Contributed-by: Nandini Singhal <cs15mtech01004@iith.ac.in> Differential Revision: https://reviews.llvm.org/D41047 llvm-svn: 320336
* [DataEncoder] Replace buggy versions of write functions.Davide Italiano2017-12-101-36/+8
| | | | | | | | | | They cause an ubsan error when ran through the testsuite (store to misaligned address is UB). This commit kills two birds with one stone, as we also remove some code while fixing it. <rdar://problem/35941757> llvm-svn: 320335
* [X86] Add ROL/ROR schedule testsSimon Pilgrim2017-12-101-2/+732
| | | | llvm-svn: 320334
* [X86] Add DIV/MUL/NEG/NOP/NOT/PAUSE schedule testsSimon Pilgrim2017-12-101-6/+862
| | | | llvm-svn: 320333
* [X86] Add DEC/INC schedule testsSimon Pilgrim2017-12-102-2/+1079
| | | | | | Include i686 (non-REX) variant tests as well llvm-svn: 320332
* [X86] Add INS/OUTS schedule testsSimon Pilgrim2017-12-101-8/+186
| | | | llvm-svn: 320331
* [X86] Add CMPS/MOVS/SCAS/STOS schedule testsSimon Pilgrim2017-12-101-20/+412
| | | | llvm-svn: 320330
* [X86] Add CMOV schedule testsSimon Pilgrim2017-12-102-1/+2004
| | | | llvm-svn: 320329
* [X86] Add BT/BTC/BTR/BTS schedule testsSimon Pilgrim2017-12-101-4/+669
| | | | llvm-svn: 320328
* Move RelaPlt and RelaIplt to InX. NFC.Rafael Espindola2017-12-104-28/+29
| | | | llvm-svn: 320327
* [X86] Add VCOMISDZrr, VCOMISSZrr, VUCOMISDZrr, and VUCOMISSZrr to the ↵Craig Topper2017-12-101-4/+4
| | | | | | skylake server sheduler model llvm-svn: 320326
* [X86] Rename some instructions that start with Int_ to have the _Int at the end.Craig Topper2017-12-1013-267/+267
| | | | | | | | This matches AVX512 version and is more consistent overall. And improves our scheduler models. In some cases this adds _Int to instructions that didn't have any Int_ before. It's a side effect of the adjustments made to some of the multiclasses. llvm-svn: 320325
* Move RelaDyn to InX. NFC.Rafael Espindola2017-12-104-40/+38
| | | | llvm-svn: 320324
* Remove this->. NFC.Rafael Espindola2017-12-101-2/+2
| | | | llvm-svn: 320323
* [X86][X87] Fix typo in znver1 FIST/FISTT schedule patternsSimon Pilgrim2017-12-102-5/+5
| | | | llvm-svn: 320322
* [X86][X87] Add missing x87 scheduler testsSimon Pilgrim2017-12-101-62/+1322
| | | | | | Split off some 'n' instruction versions to make it clearer when WAIT is being inserted llvm-svn: 320321
* [X86] Rename some instructions from 'rb' to 'rrb' to make 'b' a proper ↵Craig Topper2017-12-103-18/+18
| | | | | | | | suffix. Fix the scheduling information for some of them. Some of the scheduling information was only present for the 'rb' version' and not the 'rr' version. Now we match 'rr(b?)' llvm-svn: 320320
* [X86] Add VCVTQQ2PS to the skylake server scheduler models.Craig Topper2017-12-102-1/+7
| | | | llvm-svn: 320319
* [X86] Add VPMULLWZ256 to the skylake server scheduler modelCraig Topper2017-12-101-0/+2
| | | | llvm-svn: 320318
* [X86] Add 256/512-bit EVEX VPSADBW instructions to skylake server scheduler ↵Craig Topper2017-12-101-2/+4
| | | | | | model. llvm-svn: 320317
* [X86] Fix a few instructions that were named Z512 instead of just Z.Craig Topper2017-12-104-15/+15
| | | | | | This makes things consistent with our normal instruction naming. llvm-svn: 320316
* [X86] Add VPSRLWZrr to skylake server scheduler model.Craig Topper2017-12-101-0/+1
| | | | llvm-svn: 320315
* [X86] Add VPUNPCKLWDZrr to skylake server scheduler model.Craig Topper2017-12-101-0/+1
| | | | llvm-svn: 320314
* [X86] Adjust tablegen includes so we can use Instructions in scheduler ↵Craig Topper2017-12-102-26/+25
| | | | | | | | models instead of just instregexs. This separates the CPU specific scheduler model includes to occur after the instructions. Moves the instruction includes between the basic scheduler information and the CPU specific scheduler models. llvm-svn: 320313
* [SimplifyLibCalls] propagate FMF when folding pow(x, -1.0) callSanjay Patel2017-12-102-15/+12
| | | | | | | Follow-up for a bug that's similar to: https://bugs.llvm.org/show_bug.cgi?id=35601 llvm-svn: 320312
* [InstCombine] add test for pow(x, -1.0) with FMF; NFCSanjay Patel2017-12-101-20/+23
| | | | llvm-svn: 320311
* [SimplifyLibCalls] propagate FMF when folding pow(x, 2.0) call (PR35601)Sanjay Patel2017-12-102-3/+8
| | | | | | | This should fix the larger problem with sqrt shown in: https://bugs.llvm.org/show_bug.cgi?id=35601 llvm-svn: 320310
* [InstCombine] add test for pow(x, 2.0) with FMF; NFCSanjay Patel2017-12-101-6/+18
| | | | llvm-svn: 320309
* [X86] Flag BroadWell scheduler model as completeSimon Pilgrim2017-12-108-44/+43
| | | | | | Locally tag COPY as WriteMove, which has caused some reg-reg + reg-mem instruction tests to reorder. llvm-svn: 320308
* Regenerate some AVX2+ scheduling tests that got missedSimon Pilgrim2017-12-102-39/+39
| | | | llvm-svn: 320307
* Strip trailing whitespace. NFCI.Simon Pilgrim2017-12-101-3/+3
| | | | llvm-svn: 320306
* Regenerate some scheduling tests that got missedSimon Pilgrim2017-12-102-20/+20
| | | | llvm-svn: 320305
* [X86] Flag ZNVER1 scheduler model as completeSimon Pilgrim2017-12-101-6/+3
| | | | | | We just have to locally tag COPY as WriteMove llvm-svn: 320304
* [X86] Flag SLM scheduler model as completeSimon Pilgrim2017-12-101-5/+3
| | | | | | We just have to locally tag COPY as WriteMove llvm-svn: 320303
* [X86][AVX[ Tag VZEROALL/VZEROUPPER instructions scheduler classesSimon Pilgrim2017-12-102-3/+9
| | | | llvm-svn: 320302
* [X86] Tag SSE4A instructions as SSE INTALU scheduler classesSimon Pilgrim2017-12-101-4/+8
| | | | llvm-svn: 320301
* [X86] Flag BTVER2 scheduler model as completeSimon Pilgrim2017-12-101-4/+3
| | | | | | We just have to locally tag COPY as WriteMove llvm-svn: 320300
* [X86] Tag ADJSTACK instructions as INTALU scheduler classSimon Pilgrim2017-12-101-11/+9
| | | | llvm-svn: 320299
* [SCEV] Fix wrong Equal predicate created in getAddRecForPhiWithCastsDorit Nuzman2017-12-102-8/+12
| | | | | | | | | | | | | | | | | | | CreateAddRecFromPHIWithCastsImpl() adds an IncrementNUSW overflow predicate which allows the PSCEV rewriter to rewrite this scev expression: (zext i8 {0, + , (trunc i32 step to i8)} to i32) into {0, +, (sext i8 (trunc i32 step to i8) to i32)} But then it adds the wrong Equal predicate: %step == (zext i8 (trunc i32 %step to i8) to i32). instead of: %step == (sext i8 (trunc i32 %step to i8) to i32) This is fixed here. Differential Revision: https://reviews.llvm.org/D40641 llvm-svn: 320298
* Fix MSVC 'not all control paths return a value' warningSimon Pilgrim2017-12-101-0/+1
| | | | llvm-svn: 320297
* [X86] Tag MORESTACK instructions as ret scheduler classSimon Pilgrim2017-12-101-3/+3
| | | | llvm-svn: 320296
* [X86] Fix duplicate entries in skylake server scheduler model by changing ↵Craig Topper2017-12-102-24/+24
| | | | | | | | Z128 to Z256 Based on the fact that the 'Y' version of the instruction is next to this, I assume Z256 is the intended value. llvm-svn: 320295
* [X86] Add MOVQI2PQIrm, MOVSDmr, and MOVSDrm to scheduler informationCraig Topper2017-12-107-9/+24
| | | | | | The VEX versions were present but not the legacy SSE versions. llvm-svn: 320294
* [X86] Add LEA64_32r to scheduler models for ↵Craig Topper2017-12-105-5/+5
| | | | | | Sandybridge,Haswell,Broadwell,Skylake llvm-svn: 320293
* [X86] Add IN16/OUT16 to scheduling information for Haswell,Broadwell,SkylakeCraig Topper2017-12-104-16/+16
| | | | | | Sandy Bridge is also missing it, but it has other issues. See PR35590. llvm-svn: 320292
* [X86] Fix scheduler models to support ADD32ri in addition to ADD32ri8. ↵Craig Topper2017-12-105-80/+80
| | | | | | Similar for all sizes of AND/OR/XOR/SUB/ADC/SBB/CMP. llvm-svn: 320291
* [X86] Rename some instructions so that 'b' is added as a suffix instead of ↵Craig Topper2017-12-103-22/+22
| | | | | | replacing an 'r' llvm-svn: 320290
* [X86] Add CMPSDrr/rm to the scheduler models.Craig Topper2017-12-105-0/+10
| | | | | | Somehow CMPSSrr/rm was there and the VEX version was there, but this was consistently missing. llvm-svn: 320289
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