5 files changed, 53 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td
index 6e5f6f39525..75d46d6ff31 100755
--- a/llvm/lib/Target/X86/X86SchedBroadwell.td
+++ b/llvm/lib/Target/X86/X86SchedBroadwell.td
@@ -21,6 +21,10 @@ def BroadwellModel : SchedMachineModel {
 
   // Based on the LSD (loop-stream detector) queue size and benchmarking data.
   let LoopMicroOpBufferSize = 50;
+
+  // This flag is set to allow the scheduler to assign a default model to 
+  // unrecognized opcodes.
+  let CompleteModel = 0;
 }
 
 let SchedModel = BroadwellModel in {
diff --git a/llvm/lib/Target/X86/X86ScheduleBtVer2.td b/llvm/lib/Target/X86/X86ScheduleBtVer2.td
index d7474a28896..6ea81a25e41 100644
--- a/llvm/lib/Target/X86/X86ScheduleBtVer2.td
+++ b/llvm/lib/Target/X86/X86ScheduleBtVer2.td
@@ -22,6 +22,10 @@ def BtVer2Model : SchedMachineModel {
   let HighLatency = 25;
   let MispredictPenalty = 14; // Minimum branch misdirection penalty
   let PostRAScheduler = 1;
+
+  // FIXME: SSE4/AVX is unimplemented. This flag is set to allow
+  // the scheduler to assign a default model to unrecognized opcodes.
+  let CompleteModel = 0;
 }
 
 let SchedModel = BtVer2Model in {
diff --git a/llvm/lib/Target/X86/X86ScheduleSLM.td b/llvm/lib/Target/X86/X86ScheduleSLM.td
index fb0999b59ca..35ec7488db7 100644
--- a/llvm/lib/Target/X86/X86ScheduleSLM.td
+++ b/llvm/lib/Target/X86/X86ScheduleSLM.td
@@ -23,6 +23,10 @@ def SLMModel : SchedMachineModel {
 
   // For small loops, expand by a small factor to hide the backedge cost.
   let LoopMicroOpBufferSize = 10;
+
+  // FIXME: SSE4 is unimplemented. This flag is set to allow
+  // the scheduler to assign a default model to unrecognized opcodes.
+  let CompleteModel = 0;
 }
 
 let SchedModel = SLMModel in {
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td
index 80d3bdb90df..a4e5327213c 100644
--- a/llvm/lib/Target/X86/X86ScheduleZnver1.td
+++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td
@@ -21,6 +21,12 @@ def Znver1Model : SchedMachineModel {
   let MispredictPenalty = 17;
   let HighLatency = 25;
   let PostRAScheduler = 1;
+
+  // FIXME: This variable is required for incomplete model.
+  // We haven't catered all instructions.
+  // So, we reset the value of this variable so as to
+  // say that the model is incomplete.
+  let CompleteModel = 0;
 }
 
 let SchedModel = Znver1Model in {
diff --git a/llvm/test/CodeGen/X86/pr35636.ll b/llvm/test/CodeGen/X86/pr35636.ll
new file mode 100644
index 00000000000..70ff8d83e7e
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr35636.ll
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver1 | FileCheck %s
+
+define void @_Z15uint64_to_asciimPc(i64 %arg) {
+; CHECK-LABEL: _Z15uint64_to_asciimPc:
+; CHECK:       # %bb.0: # %bb
+; CHECK-NEXT:    movabsq $811296384146066817, %rax # imm = 0xB424DC35095CD81
+; CHECK-NEXT:    movq %rdi, %rdx
+; CHECK-NEXT:    mulxq %rax, %rax, %rcx
+; CHECK-NEXT:    shrq $42, %rcx
+; CHECK-NEXT:    imulq $281474977, %rcx, %rax # imm = 0x10C6F7A1
+; CHECK-NEXT:    shrq $20, %rax
+; CHECK-NEXT:    leal 5(%rax,%rax,4), %eax
+; CHECK-NEXT:    andl $134217727, %eax # imm = 0x7FFFFFF
+; CHECK-NEXT:    leal (%rax,%rax,4), %eax
+; CHECK-NEXT:    shrl $26, %eax
+; CHECK-NEXT:    orb $48, %al
+; CHECK-NEXT:    movb %al, (%rax)
+; CHECK-NEXT:    retq
+bb:
+  %tmp = udiv i64 %arg, 100000000000000
+  %tmp1 = mul nuw nsw i64 %tmp, 281474977
+  %tmp2 = lshr i64 %tmp1, 20
+  %tmp3 = trunc i64 %tmp2 to i32
+  %tmp4 = add nuw nsw i32 %tmp3, 1
+  %tmp5 = and i32 %tmp4, 268435455
+  %tmp6 = mul nuw nsw i32 %tmp5, 5
+  %tmp7 = and i32 %tmp6, 134217727
+  %tmp8 = mul nuw nsw i32 %tmp7, 5
+  %tmp9 = lshr i32 %tmp8, 26
+  %tmp10 = trunc i32 %tmp9 to i8
+  %tmp11 = or i8 %tmp10, 48
+  store i8 %tmp11, i8* undef, align 1
+  ret void
+}