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* [AArch64] Fixes for ARMv8.2-A FP16 scalar intrinsic - clang portionAbderrazek Zaafrani2018-02-122-48/+145
| | | | | | https://reviews.llvm.org/D42993 llvm-svn: 324940
* [X86] Simplify X86DAGToDAGISel::matchBEXTRFromAnd by creating an ↵Craig Topper2018-02-125-38/+43
| | | | | | | | X86ISD::BEXTR node and calling Select. Add isel patterns to recognize this node. This removes a bunch of special case code for selecting the immediate and folding loads. llvm-svn: 324939
* [X86] Remove unused multiclass argument. NFCCraig Topper2018-02-121-3/+3
| | | | llvm-svn: 324938
* [GlobalMerge] Allow merging of dllexported variablesMartin Storsjo2018-02-122-6/+15
| | | | | | | | | If merging them, the dllexport attribute needs to be brought along to the new GlobalAlias. Differential Revision: https://reviews.llvm.org/D43192 llvm-svn: 324937
* Fix the syntax highlighting of strings in dwarfdump.Adrian Prantl2018-02-121-4/+4
| | | | llvm-svn: 324936
* Factor out common condition into an easier to understand helper function (NFC).Adrian Prantl2018-02-122-2/+12
| | | | llvm-svn: 324935
* [ScopBuilder] scalar-indep: Fix mutually referencing PHIs.Michael Kruse2018-02-123-0/+165
| | | | | | | | | | | | | | Two or more PHIs mutually using each other directly or indirectly as incoming value could cause that a PHI WRITE be added before the PHI READ (i.e. it overwrites the current incoming value with the next incoming value before it being read). Fix by ensuring that the PHI WRITE and PHI READ are in the same statement. This should fix the miscompile of SingleSource/Benchmark/Misc/whetstone from the test-suite. llvm-svn: 324934
* Move the debuginfo-dce-or test into debuginfo-variables.ll, NFCVedant Kumar2018-02-122-46/+10
| | | | llvm-svn: 324933
* Revert "[ThinLTO] Add GraphTraits for FunctionSummaries"Volodymyr Sapsai2018-02-124-181/+2
| | | | | | | | | It caused assertion failure Assertion failed: (!DD.IsLambda && !MergeDD.IsLambda && "faked up lambda definition?"), function MergeDefinitionData, file /Users/buildslave/jenkins/workspace/clang-stage1-configure-RA/llvm/tools/clang/lib/Serialization/ASTReaderDecl.cpp, line 1675. on the second stage build bots. llvm-svn: 324932
* Revert "Follow on to rL324854 (Added tests)" as part of r324854 revert.Volodymyr Sapsai2018-02-121-58/+0
| | | | | | r324854 caused broken build on the second stage build bots. llvm-svn: 324931
* Remove the pubnames support from the Xcode project.Jim Ingham2018-02-121-216/+24
| | | | llvm-svn: 324930
* [DebugInfo] Update Checksum handling in CGDebugInfoScott Linder2018-02-122-12/+16
| | | | | | Update to match new DIFile API. llvm-svn: 324929
* [DebugInfo] Unify ChecksumKind and Checksum value in DIFileScott Linder2018-02-1217-122/+198
| | | | | | | | | Rather than encode the absence of a checksum with a Kind variant, instead put both the kind and value in a struct and wrap it in an Optional. Differential Revision: http://reviews.llvm.org/D43043 llvm-svn: 324928
* [InstCombine] X / (X * Y) --> 1.0 / YSanjay Patel2018-02-122-6/+12
| | | | | | | | | This is similar to the instsimplify fold added with D42385 ( rL323716 ) ...but this can't be in instsimplify because we're creating/morphing a different instruction. llvm-svn: 324927
* [InstCombine] add tests for missing fdiv fold; NFCSanjay Patel2018-02-121-0/+42
| | | | llvm-svn: 324926
* Remove dead code for handling DWARF pubnamesAdrian McCarthy2018-02-127-540/+0
| | | | | | | | | | | | Summary: LLDB doesn't use this code, the code has no tests, and the code does suspicious things like hashing pointers to strings instead of the strings themselves. Subscribers: sanjoy, mgorny, JDevlieghere Differential Revision: https://reviews.llvm.org/D43202 llvm-svn: 324925
* [InstCombine] regenerate checks; NFCSanjay Patel2018-02-121-28/+44
| | | | llvm-svn: 324924
* Implement LWG 2835 - fix <tgmath.h>Marshall Clow2018-02-122-5/+13
| | | | llvm-svn: 324923
* [InstCombine] various clean-ups for div transforms; NFCSanjay Patel2018-02-121-108/+94
| | | | llvm-svn: 324922
* [testsuite] Reintroduce test to check leaking.Davide Italiano2018-02-123-0/+141
| | | | | | | It wasn't python leaking, it was lldb. Thanks to Pavel for the explanation. Pointy-hat to me. llvm-svn: 324919
* Add a unit test for Driver::getDefaultModuleCachePath().Adrian Prantl2018-02-122-0/+29
| | | | llvm-svn: 324917
* [LICM] update BlockColors after splitting predecessorsJun Bum Lim2018-02-122-8/+84
| | | | | | | | | | Update BlockColors after splitting predecessors. Do not allow splitting EHPad for sinking when the BlockColors is not empty, so we can simply assign predecessor's color to the new block. Fixes PR36184 llvm-svn: 324916
* Further cleanup to Driver mode code, as suggested by dblaikie [NFC]Erich Keane2018-02-121-9/+7
| | | | llvm-svn: 324915
* [libclang] Add `CXSymbolRole role` to CXIdxEntityRefInfoFangrui Song2018-02-127-15/+85
| | | | | | | | | | | | | | | | | | Summary: CXIdxEntityRefInfo contains the member `CXIdxEntityRefKind kind;` to differentiate implicit and direct calls. However, there are more roles defined in SymbolRole. Among them, `Read/Write` are probably the most useful ones as they can be used to differentiate Read/Write occurrences of a symbol for document highlight in a text document. See `export namespace DocumentHighlightKind` on https://microsoft.github.io/language-server-protocol/specification Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D42895 llvm-svn: 324914
* [Sema] Don't mark plain MS enums as fixedReid Kleckner2018-02-126-48/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This fixes a flaw in our AST: PR27098 MSVC always gives plain enums the underlying type 'int'. Clang does this as well, but we claim the enum is "fixed", as if the user actually wrote ': int'. It means we end up emitting spurious -Wsign-compare warnings on code like this: enum Vals { E1, E2, E3 }; bool f(unsigned v1, Vals v2) { return v1 == v2; } We think 'v2' can take on negative values because we think 'Vals' is fixed. This fixes that. Reviewers: rsmith Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D43110 llvm-svn: 324913
* [AArch64] Fixes for ARMv8.2-A FP16 scalar intrinsic - llvm portionAbderrazek Zaafrani2018-02-122-0/+36
| | | | | | https://reviews.llvm.org/D42993 llvm-svn: 324912
* Implement LWG#2908 - The less-than operator for shared pointers could do ↵Marshall Clow2018-02-122-3/+8
| | | | | | more, and mark 2878 as complete as well (we already do that) llvm-svn: 324911
* [X86] Add missing scheduling class tag for i64 absolute address movesSimon Pilgrim2018-02-121-5/+5
| | | | | | | | Expand existing SchedRW to encompass these like it did for the other memory offset movs - added comments to closing braces to keep track of def scopes. We only tagged it with the itinerary class, so completeness checks were erroneously passed (PR35639). llvm-svn: 324910
* Update target-note-test to be current with the AMDGPU changesErich Keane2018-02-121-9/+9
| | | | llvm-svn: 324909
* [AArch64] Improve v8.1-A code-gen for atomic load-andOliver Stannard2018-02-1211-1/+136
| | | | | | | | | | | | | | | | | | | | | | | | Armv8.1-A added an atomic load-clear instruction (which performs bitwise and with the complement of it's operand), but not a load-and instruction. Our current code-generation for atomic load-and always inserts an MVN instruction to invert its argument, even if it could be folded into a constant or another instruction. This adds lowering early in selection DAG to convert a load-and operation into an xor with -1 and a load-clear, allowing the normal DAG optimisations to work on it. To do this, I've had to add a new ISD opcode, ATOMIC_LOAD_CLR. I don't see any easy way to do this with an AArch64-specific ISD node, because the code-generation for atomic operations assumes the SDNodes are of type AtomicSDNode. I've left the old tablegen patterns in because they are still needed for global isel. Differential revision: https://reviews.llvm.org/D42478 llvm-svn: 324908
* Make attribute-target on a Definition-after-use update the LLVM attributesErich Keane2018-02-124-40/+71
| | | | | | | | | | | | | | | As reported here: https://bugs.llvm.org/show_bug.cgi?id=36301 The issue is that the 'use' causes the plain declaration to emit the attributes to LLVM-IR. However, if the definition added it later, these would silently disappear. This commit extracts that logic to its own function in CodeGenModule, and has the attribute-applications done during 'definition' update the attributes properly. Differential Revision: https://reviews.llvm.org/D43095 llvm-svn: 324907
* [sanitizer] Size class map & local cache improvementsKostya Kortchinsky2018-02-123-40/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: - Reland rL324263, this time allowing for a compile-time decision as to whether or not use the 32-bit division. A single test is using a class map covering a maximum size greater than 4GB, this can be checked via the template parameters, and allows SizeClassAllocator64PopulateFreeListOOM to pass; - `MaxCachedHint` is always called on a class id for which we have already computed the size, but we still recompute `Size(class_id)`. Change the prototype of the function to work on sizes instead of class ids. This also allows us to get rid of the `kBatchClassID` special case. Update the callers accordingly; - `InitCache` and `Drain` will start iterating at index 1: index 0 contents are unused and can safely be left to be 0. Plus we do not pay the cost of going through an `UNLIKELY` in `MaxCachedHint`, and touching memory that is otherwise not used; - `const` some variables in the areas modified; - Remove an spurious extra line at the end of a file. Reviewers: alekseyshl, tl0gic, dberris Reviewed By: alekseyshl, dberris Subscribers: dberris, kubamracek, delcypher, llvm-commits, #sanitizers Differential Revision: https://reviews.llvm.org/D43088 llvm-svn: 324906
* [X86][AVX512] Add missing scheduling class tag for KMOVB/KMOVW/KMOVD/KMOVQ ↵Simon Pilgrim2018-02-121-3/+5
| | | | | | | | moves/loads/stores. We only tagged it with the itinerary class, so completeness checks were erroneously passed (PR35639). llvm-svn: 324905
* [OpenMP][libomptarget] Enable the compilation of multiple bc libraries for ↵Gheorghe-Teodor Bercea2018-02-122-43/+53
| | | | | | | | | | | | | | | | | | | runtime inlining Summary: Different NVIDIA GPUs support different compute capabilities. To enable the inlining of runtime functions and the best performance on different generations of NVIDIA GPUs, a bc library for each compute capability needs to be compiled. The same compiler build will then be usable in conjunction with multiple generations of NVIDIA GPUs. To differentiate between versions of the same bc lib, the output file name will contain the compute capability ID. Depends on D14254 Reviewers: Hahnfeld, hfinkel, carlo.bertolli, caomhin, ABataev, grokos Reviewed By: Hahnfeld, grokos Subscribers: guansong, mgorny, openmp-commits Differential Revision: https://reviews.llvm.org/D41724 llvm-svn: 324904
* [AArch64] Refactor identification of SIMD immediatesEvandro Menezes2018-02-121-368/+280
| | | | | | | | Get rid of icky goto loops and make the code easier to maintain (NFC). Differential revision: https://reviews.llvm.org/D42723 llvm-svn: 324903
* Add Invalid-note test negllected in R324673,324674,324675,324676Erich Keane2018-02-121-0/+162
| | | | llvm-svn: 324902
* [X86][AVX512] Add missing scheduling class tag for ↵Simon Pilgrim2018-02-121-3/+7
| | | | | | | | | | VMOVQ/VMOVHLPS/VMOVLHPS/VMOVHPD/VMOVHPS/VMOVLPD/VMOVLPS Tag AVX512 variants to match SSE/AVX originals. We only tagged it with the itinerary class, so completeness checks were erroneously passed (PR35639). llvm-svn: 324901
* Re-commit r324490: [DebugInfo] Improvements to representation of enumeration ↵Momchil Velikov2018-02-125-10/+112
| | | | | | | | types (PR36168) Differential revision: https://reviews.llvm.org/D42736 llvm-svn: 324900
* Re-commit r324489: [DebugInfo] Improvements to representation of enumeration ↵Momchil Velikov2018-02-1216-51/+392
| | | | | | | | types (PR36168) Differential Revision: https://reviews.llvm.org/D42734 llvm-svn: 324899
* [X86] Tag CET-IBT instruction scheduler classesSimon Pilgrim2018-02-121-2/+2
| | | | llvm-svn: 324898
* [X86][MMX] Add missing scheduling class tag for EMMS/FEMMSSimon Pilgrim2018-02-124-6/+10
| | | | | | | | We only tagged it with the itinerary class, so completeness checks were erroneously passed (PR35639). AMD targets can perform these a lot quicker than WriteMicrocoded so will need an override in the models. llvm-svn: 324897
* [clang-format] Fix comment indentation in text protosKrasimir Georgiev2018-02-122-0/+13
| | | | | | | | | | Summary: This patch fixes a bug where the comment indent of comments in text protos gets messed up because by default paren states get created with AlignColons = true (which makes snese for ObjC). Subscribers: klimek, cfe-commits Differential Revision: https://reviews.llvm.org/D43194 llvm-svn: 324896
* While implementing P0777 - preventing unnecessary decay, I found some ↵Marshall Clow2018-02-122-11/+11
| | | | | | non-public uses of decay that could be replaced by __uncvref. NFC intented llvm-svn: 324895
* [NFC] Fix comment of class InstrStageKrzysztof Parzyszek2018-02-121-3/+3
| | | | | | | | Patch by Wei-Ren Chen. Differential Revision: https://reviews.llvm.org/D42905 llvm-svn: 324894
* [SLP] Take user instructions cost into consideration in insertelement ↵Alexey Bataev2018-02-127-142/+160
| | | | | | | | | | | | | | | | | | | | | | | | vectorization. Summary: For better vectorization result we should take into consideration the cost of the user insertelement instructions when we try to vectorize sequences that build the whole vector. I.e. if we have the following scalar code: ``` <Scalar code> insertelement <ScalarCode>, ... ``` we should consider the cost of the last `insertelement ` instructions as the cost of the scalar code. Reviewers: RKSimon, spatel, hfinkel, mkuper Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D42657 llvm-svn: 324893
* [AArch64] Improve v8.1-A code-gen for atomic load-subtractOliver Stannard2018-02-123-0/+134
| | | | | | | | | | | | | | | | | | | | | Armv8.1-A added an atomic load-add instruction, but not a load-subtract instruction. Our current code-generation for atomic load-subtract always inserts a NEG instruction to negate it's argument, even if it could be folded into a constant or another instruction. This adds lowering early in selection DAG to convert a load-subtract operation into a subtract and a load-add, allowing the normal DAG optimisations to work on it. I've left the old tablegen patterns in because they are still needed for global isel. Some of the tests in this patch are copied from D35375 by Chad Rosier (which was abandoned). Differential revision: https://reviews.llvm.org/D42477 llvm-svn: 324892
* [InstCombine] various clean-ups for commonIDivTransforms; NFCSanjay Patel2018-02-121-16/+17
| | | | llvm-svn: 324891
* Allow the NS, CF, and ObjC attributes to be used with ↵Aaron Ballman2018-02-126-50/+134
| | | | | | -fdouble-square-bracket-attributes. The syntactic locations for such attributes on ObjC constructs have been specifically chosen to follow the GNU attribute syntactic locations. llvm-svn: 324890
* Test commit: reformat commentNicholas Wilson2018-02-121-3/+3
| | | | llvm-svn: 324889
* [clangd] Log all ignored diagnostics.Ilya Biryukov2018-02-123-18/+33
| | | | | | | | | | | | | | | | | Summary: To aid debugging failures and crashes. Only part of ignored diagnostics was logged before, now we log all of them. Reviewers: ioeric, hokein, sammccall Reviewed By: hokein Subscribers: klimek, jkorous-apple, cfe-commits Differential Revision: https://reviews.llvm.org/D43123 llvm-svn: 324888
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