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* [ScopInfo] Allow uniform branch conditionsTobias Grosser2017-09-255-1/+108
| | | | | | | If all but one branch come from an error condition and the incoming value from this branch is a constant, we can model this branch. llvm-svn: 314116
* Remove trailing whitespaces.Michael Liao2017-09-251-41/+41
| | | | llvm-svn: 314115
* [DebugInfo] Sort the SDDbgValue list before assuming it is in IR orderReid Kleckner2017-09-253-10/+169
| | | | | | | | | | | | | | | | | | | | | | | Summary: This code iterates the 'Orders' vector in parallel with the DbgValue list, emitting all DBG_VALUEs that occurred between the last IR order insertion point and the next insertion point. This assumes the SDDbgValue list is sorted in IR order, which it usually is. However, it is not sorted when a node with a debug value is replaced with another one. When this happens, TransferDbgValues is called, and the new value is added to the end of the list. The problem can be solved by stably sorting the list by IR order. Reviewers: aprantl, Ka-Ka Reviewed By: aprantl Subscribers: MatzeB, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D38197 llvm-svn: 314114
* Use {} instead of make_pair and an iterator for the insertion point, NFCReid Kleckner2017-09-251-5/+6
| | | | llvm-svn: 314113
* Rework atomic ops to use clang builtins rather than llvm asmJan Vesely2017-09-2513-202/+117
| | | | | | | reviewer: Aaron Watry Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 314112
* prepare_builtins: Fix compile breakage with older LLVMJan Vesely2017-09-251-0/+5
| | | | | | | | | Fixes r314050 reviewer: Tom Stellard Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 314111
* [scudo] Scudo thread specific data refactor, part 2Kostya Kortchinsky2017-09-258-145/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Following D38139, we now consolidate the TSD definition, merging the shared TSD definition with the exclusive TSD definition. We introduce a boolean set at initializaton denoting the need for the TSD to be unlocked or not. This adds some unused members to the exclusive TSD, but increases consistency and reduces the definitions fragmentation. We remove the fallback mechanism from `scudo_allocator.cpp` and add a fallback TSD in the non-shared version. Since the shared version doesn't require one, this makes overall more sense. There are a couple of additional cosmetic changes: removing the header guards from the remaining `.inc` files, added error string to a `CHECK`. Question to reviewers: I thought about friending `getTSDAndLock` in `ScudoTSD` so that the `FallbackTSD` could `Mutex.Lock()` directly instead of `lock()` which involved zeroing out the `Precedence`, which is unused otherwise. Is it worth doing? Reviewers: alekseyshl, dvyukov, kcc Reviewed By: dvyukov Subscribers: srhines, llvm-commits Differential Revision: https://reviews.llvm.org/D38183 llvm-svn: 314110
* [X86][LLVM]Expanding Supports lowerInterleavedStore() in ↵Michael Zuckerman2017-09-253-36/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | X86InterleavedAccess (VF8 stride 4): This patch expands the support of lowerInterleavedStore to 8x8i stride 4. LLVM creates suboptimal shuffle code-gen for AVX2. In overall, this patch is a specific fix for the pattern (Strid=4 VF=8) and we plan to include more patterns in the future. The patch goal is to optimize the following sequence: At the end of the computation, we have xmm2, xmm0, xmm12 and xmm3 holding each 8 chars: c0, c1, , c7 m0, m1, , m7 y0, y1, , y7 k0, k1, ., k7 And these need to be transposed/interleaved and stored like so: c0 m0 y0 k0 c1 m1 y1 k1 c2 m2 y2 k2 c3 m3 y3 k3 .... Reviewers DavidKreitzer Farhana zvi igorb guyblank RKSimon Ayal Differential Revision: https://reviews.llvm.org/D36058 Change-Id: I3cc5c2ca5d6318901c192a4428493b99ef424c32 llvm-svn: 314109
* [ELF][fix] Using statically linked lld leads to segmentation fault on ↵Evgeny Mankov2017-09-251-0/+5
| | | | | | | | | | | | | | | linking ELF [Synopsys] Using function elf::link(...) leads to segmentation fault on its second call. First call finishes correctly. [Solution] Clear the rest of globals. Reviewed by: George Rimar and Rui Ueyama Differential Revision: http://reviews.llvm.org/D38131 llvm-svn: 314108
* Fix clangd when built with LLVM_LINK_LLVM_DYLIB=ONSylvestre Ledru2017-09-251-1/+4
| | | | | | | | | | | | Reviewers: malaperle, malaperle-ericsson, bkramer Reviewed By: bkramer Subscribers: bkramer, mgorny, ilya-biryukov, cfe-commits Differential Revision: https://reviews.llvm.org/D38228 llvm-svn: 314107
* [PowerPC] Eliminate compares - add i64 sext/zext handling for SETLT/SETGTNemanja Ivanovic2017-09-256-3/+543
| | | | | | | | As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314106
* [AArch64] Add basic support for Qualcomm's Saphira CPU.Chad Rosier2017-09-2511-0/+45
| | | | llvm-svn: 314105
* [Clang] Adding missing feature to goldmontMichael Zuckerman2017-09-252-0/+3
| | | | | Change-Id: I6c22478d16b8e02ce60dae2f8c80d43bc5ab3a9c llvm-svn: 314104
* Adding missing feature to goldmont.Michael Zuckerman2017-09-251-1/+2
| | | | | Change-Id: I1ddc619169fae6a56308deef8dae5db3da702cf4 llvm-svn: 314103
* fixing a bug in mask[z]_set1 intrinsicJina Nahias2017-09-252-34/+6
| | | | | | | Differential Revision: https://reviews.llvm.org/D38231 Change-Id: I80bbff9cbe93e4be54d8a761ef9723edf3f57c57 llvm-svn: 314102
* [SLP] Support for horizontal min/max reduction.Alexey Bataev2017-09-253-1299/+1852
| | | | | | | | | | | | | | | Summary: SLP vectorizer supports horizontal reductions for Add/FAdd binary operations. Patch adds support for horizontal min/max reductions. Function getReductionCost() is split to getArithmeticReductionCost() for binary operation reductions and getMinMaxReductionCost() for min/max reductions. Patch fixes PR26956. Reviewers: spatel, mkuper, hfinkel, RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D27846 llvm-svn: 314101
* [mips][compiler-rt] Disable sem_init_glibc.cc for MIPS64.Simon Dardis2017-09-251-1/+1
| | | | | | | | | | | This test can't pass on MIPS64 due to the lack of versioned interceptors for asan and company. The interceptors bind to the earlier version of sem_init rather than the latest version. For MIPS64el this causes an accidental pass while MIPS64 big endian fails due reading back a different 32bit word to what sem_init wrote when the test is corrected to use 64bit atomics. llvm-svn: 314100
* [ELF] - Simplify removeUnusedSyntheticSections a bit.George Rimar2017-09-252-5/+4
| | | | | | | | | | | | | | | Previously`InX::Got` and InX::MipsGot synthetic sections were not removed if ElfSym::GlobalOffsetTable was defined. ElfSym::GlobalOffsetTable is a symbol for _GLOBAL_OFFSET_TABLE_. Patch moves ElfSym::GlobalOffsetTable check out from removeUnusedSyntheticSections. Also note that there was no point to check ElfSym::GlobalOffsetTable for MIPS case because InX::MipsGot::empty() always returns false for non-relocatable case, and in case of relocatable output we do not create special symbols anyways. Differential revision: https://reviews.llvm.org/D37623 llvm-svn: 314099
* [ELF] - Report orphan sections if -verbose given.George Rimar2017-09-252-0/+35
| | | | | | | | | When -verbose is specified, patch outputs names of each input orphan section assigned to output. Differential revision: https://reviews.llvm.org/D37517 llvm-svn: 314098
* [ELF] - LTO: do not optimize away symbols accessed from linkerscript.George Rimar2017-09-254-1/+104
| | | | | | | | | | | Previously when BC file had global variable that was accessed from script, it was optimized away or inlined by IPO. In this patch I add symbols at left side of assignment expression as LinkerRedefined, what prevents optimization for them. Differential revision: https://reviews.llvm.org/D37059 llvm-svn: 314097
* [CodeGenPrepare][NFC] Rename TargetTransformInfo::expandMemCmp -> ↵Clement Courbet2017-09-258-12/+12
| | | | | | | | | | | | | | | | TargetTransformInfo::enableMemCmpExpansion. Summary: Right now there are two functions with the same name, one does the work and the other one returns true if expansion is needed. Rename TargetTransformInfo::expandMemCmp to make it more consistent with other members of TargetTransformInfo. Remove the unused Instruction* parameter. Differential Revision: https://reviews.llvm.org/D38165 llvm-svn: 314096
* Do not sort CU vectors.Rui Ueyama2017-09-251-6/+7
| | | | | | | We used to sort and uniquify CU vectors, but looks like CU vectors in .gdb_index sections created by gold are not guaranteed to be sorted. llvm-svn: 314095
* Speeds up CU vector creation.Rui Ueyama2017-09-252-13/+16
| | | | | | | | | | | | | We used to use std::set to uniquify CU vector elements, but as we know, std::set is pretty slow. Fortunately we didn't actually have to use a std::set here. This patch replaces it with std::vector. With this patch, lld's -gdb-index overhead when linking a clang debug build is now about 1 second (8.65 seconds without -gdb-index vs 9.60 seconds with -gdb-index). Since gold takes more than 6 seconds to create a .gdb_index for the same output, our number isn't that bad. llvm-svn: 314094
* Fix off-by-one error.Rui Ueyama2017-09-252-14/+14
| | | | llvm-svn: 314093
* Do not use StringTableBuilder to build symbol table for .gdb_index.Rui Ueyama2017-09-253-20/+26
| | | | | | | | | | | | | | | | Previously, we had two levels of hash table lookup. The first hash lookup uses CachedHashStringRefs as keys and returns offsets in string table. Then, we did the second hash table lookup to obtain GdbSymbol pointers. But we can directly map strings to GDbSymbols. One test file is updated in this patch because we no longer have a '\0' byte at the start of the string pool, which was automatically inserted by StringTableBuilder. This patch speeds up Clang debug build (with -gdb-index) link time by 0.3 seconds. llvm-svn: 314092
* Compute string hashes early and cache them.Rui Ueyama2017-09-252-7/+8
| | | | | | | | This change alone speeds up linking of Clang debug build with -gdb-index by 1.2 seconds, from 12.5 seconds to 11.3 seconds. (Without -gdb-index, lld takes 8.5 seconds to link the same input files.) llvm-svn: 314090
* Rename copy -> copyFrom.Rui Ueyama2017-09-253-3/+3
| | | | | | This patch is to improve code readability. llvm-svn: 314089
* Move Config->SymbolRenaming to SymbolTable.Rui Ueyama2017-09-254-16/+34
| | | | | | | | | | | | In order to keep track of symbol renaming, we used to have Config->SymbolRenaming, and whether a symbol is in the map or not affects its symbol attribute (i.e. "LinkeRedefined" bit). This patch adds "CanInline" bit to Symbol to aggreagate symbol information in one place and removed the member from Config since no one except SymbolTable now uses the table. llvm-svn: 314088
* Remove unused member variable.Rui Ueyama2017-09-242-3/+1
| | | | llvm-svn: 314087
* Refactor GdbIndexSection. NFC.Rui Ueyama2017-09-244-184/+151
| | | | | | | | | | | | | | | | | | | This patch rewrites a part of GdbIndexSection to address the following issues in the previous implementation: - Previously, some struct declarations were in GdbIndex.h while they were not used in GdbIndex.cpp. Such structs are moved to SyntheticSection.h. - The actual implementation were split into GdbIndexSection and GdbHash section, but that separation didn't make much sense. They are now unified as GdbIndexSection. In addition to the above changes, this patch splits functions, rename variables and remove redundant functions/variables to generally improve code quality. llvm-svn: 314084
* [X86] Make IFMA instructions during isel so we can fold broadcast loads.Craig Topper2017-09-246-27/+49
| | | | | | This required changing the ISD opcode for these instructions to have the commutable operands first and the addend last. This way tablegen can autogenerate the additional patterns for us. llvm-svn: 314083
* [X86] Add tests to show missed opportunities to fold broadcast loads into ↵Craig Topper2017-09-241-0/+85
| | | | | | | | IFMA instructions when the load is on operand1 of the instrinsic. We need to enable commuting during isel to catch this since the load folding tables can't handle broadcasts. llvm-svn: 314082
* [Polly] Information about generalized matrix multiplicationRoman Gareev2017-09-242-0/+15
| | | | | | | | Reviewed-by: Tobias Grosser <tobias@grosser.es> Differential Revision: https://reviews.llvm.org/D38218 llvm-svn: 314081
* [X86] Add IFMA instructions to the load folding tables and make them ↵Craig Topper2017-09-243-1/+124
| | | | | | commutable for the multiply operands. llvm-svn: 314080
* Fix implicit-fallthrough warning by adding missing breakSimon Pilgrim2017-09-241-0/+1
| | | | llvm-svn: 314079
* Fix signed/unsigned warningSimon Pilgrim2017-09-241-1/+1
| | | | llvm-svn: 314078
* [X86][SSE] Add more tests for shuffle combining with extracted vector ↵Simon Pilgrim2017-09-241-0/+56
| | | | | | elements (PR22415) llvm-svn: 314077
* [X86][SSE] Add support for extending bool vectors bitcasted from scalarsSimon Pilgrim2017-09-244-6582/+1212
| | | | | | | | | | This patch acts as a reverse to combineBitcastvxi1 - bitcasting a scalar integer to a boolean vector and extending it 'in place' to the requested legal type. Currently this doesn't handle AVX512 at all - but the current mask register approach is lacking for some cases. Differential Revision: https://reviews.llvm.org/D35320 llvm-svn: 314076
* [ScopDetect/Info] Look through PHIs that follow an error blockTobias Grosser2017-09-248-23/+188
| | | | | | | | | | | In case a PHI node follows an error block we can assume that the incoming value can only come from the node that is not an error block. As a result, conditions that seemed non-affine before are now in fact affine. This is a recommit of r312663 after fixing test/Isl/CodeGen/phi_after_error_block_outside_of_scop.ll llvm-svn: 314075
* [PowerPC] Eliminate compares - add i64 sext/zext handling for SETLE/SETGENemanja Ivanovic2017-09-245-0/+620
| | | | | | | | As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314073
* [AVX-512] Add pattern for selecting masked version of v8i32/v8f32 compare ↵Craig Topper2017-09-243-70/+54
| | | | | | | | instructions when VLX isn't available. We use a v16i32/v16f32 compare instead and truncate the result. We already did this for the unmasked version, but were missing the version with 'and'. llvm-svn: 314072
* [X86] Make sure we still mark the full register as implicitly defined when ↵Craig Topper2017-09-241-4/+10
| | | | | | | | we shrink 256/512 bit zeroing xors to 128-bit. Not sure if anything really cares, but this seems like the right thing to do. llvm-svn: 314071
* [AVR] Implement getCmpLibcallReturnType().Dylan McKay2017-09-241-0/+5
| | | | | | | | | This fixes the avr-rust issue (#75) with floating-point comparisons generating broken code. By default, LLVM assumes these comparisons return 32-bit values, but ours are 8-bit. Patch By Thomas Backman. llvm-svn: 314070
* [Verifier] Stop accepting broken DIGlobalVariable(s).Davide Italiano2017-09-243-3/+27
| | | | | | | | The code wasn't yelling at the user when there's a reference from a DIGlobalVariableExpression. Thanks to Adrian for the reduced testcase. Fixes PR34672. llvm-svn: 314069
* [X86] Regenerate i64 to v2f32 bitcast testSimon Pilgrim2017-09-231-3/+30
| | | | llvm-svn: 314068
* Don't warn about runtime behavior problems in variable initializers that weRichard Smith2017-09-235-15/+29
| | | | | | | | know are going to be constant-evaluated. Any relevant diagnostics should be produced by constant expression evaluation. llvm-svn: 314067
* Silence unused variable warning in Release builds.Benjamin Kramer2017-09-231-0/+1
| | | | llvm-svn: 314066
* [IslExprBuilder] Do not generate RTC with more than 64 bitTobias Grosser2017-09-236-24/+67
| | | | | | | | | | Such RTCs may introduce integer wrapping intrinsics with more than 64 bit, which are translated to library calls on AOSP that are not part of the runtime and will consequently cause linker errors. Thanks to Eli Friedman for reporting this issue and reducing the test case. llvm-svn: 314065
* [x86] reduce 64-bit mask constant to 32-bits by right shiftingSanjay Patel2017-09-232-16/+17
| | | | | | | | | | | | | | This is a follow-up from D38181 (r314023). We have to put 64-bit constants into a register using a separate instruction, so we should try harder to avoid that. From what I see, we're not likely to encounter this pattern in the DAG because the upstream setcc combines from this don't (usually?) produce this pattern. If we fix that, then this will become more relevant. Since the cost of handling this case is just loosening the predicate of the existing fold, we might as well do it now. llvm-svn: 314064
* [x86] add an add+shift test for follow-up suggestion from D38181; NFCSanjay Patel2017-09-231-0/+21
| | | | llvm-svn: 314063
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