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| author | Craig Topper <craig.topper@intel.com> | 2017-09-24 05:24:51 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-09-24 05:24:51 +0000 |
| commit | 675bdd30c6c540608f31d8abd3a6c414ec9bfd16 (patch) | |
| tree | 4982285d3e39a7aa7e8d6cca8e507e1b1ea4ca84 | |
| parent | f9e291a2f655c0859bf64c2d700266f864c0e6b5 (diff) | |
| download | bcm5719-llvm-675bdd30c6c540608f31d8abd3a6c414ec9bfd16.tar.gz bcm5719-llvm-675bdd30c6c540608f31d8abd3a6c414ec9bfd16.zip | |
[X86] Make sure we still mark the full register as implicitly defined when we shrink 256/512 bit zeroing xors to 128-bit.
Not sure if anything really cares, but this seems like the right thing to do.
llvm-svn: 314071
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.cpp | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index abef03c2ea8..4b56807cffc 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -7731,7 +7731,9 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const { unsigned SrcReg = MIB->getOperand(0).getReg(); unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm); MIB->getOperand(0).setReg(XReg); - return Expand2AddrUndef(MIB, get(X86::VXORPSrr)); + Expand2AddrUndef(MIB, get(X86::VXORPSrr)); + MIB.addReg(SrcReg, RegState::ImplicitDefine); + return true; } case X86::AVX512_128_SET0: case X86::AVX512_FsFLD0SS: @@ -7755,8 +7757,10 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const { if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) { unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm); MIB->getOperand(0).setReg(XReg); - return Expand2AddrUndef(MIB, - get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr)); + Expand2AddrUndef(MIB, + get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr)); + MIB.addReg(SrcReg, RegState::ImplicitDefine); + return true; } return Expand2AddrUndef(MIB, get(X86::VPXORDZrr)); } @@ -7766,7 +7770,9 @@ bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const { if (TRI->getEncodingValue(SrcReg) < 16) { unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm); MIB->getOperand(0).setReg(XReg); - return Expand2AddrUndef(MIB, get(X86::VXORPSrr)); + Expand2AddrUndef(MIB, get(X86::VXORPSrr)); + MIB.addReg(SrcReg, RegState::ImplicitDefine); + return true; } return Expand2AddrUndef(MIB, get(X86::VPXORDZrr)); } |
