1 files changed, 25 insertions, 16 deletions
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp
index c30ef652295..4736c4e510d 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.cpp
+++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp
@@ -100,15 +100,17 @@ namespace X86Local {
     RawFrmDstSrc  = 6,
     RawFrmImm8    = 7,
     RawFrmImm16   = 8,
-    MRMDestMem   = 32,
-    MRMSrcMem    = 33,
-    MRMSrcMemOp4 = 34,
+    MRMDestMem     = 32,
+    MRMSrcMem      = 33,
+    MRMSrcMem4VOp3 = 34,
+    MRMSrcMemOp4   = 35,
     MRMXm = 39,
     MRM0m = 40, MRM1m = 41, MRM2m = 42, MRM3m = 43,
     MRM4m = 44, MRM5m = 45, MRM6m = 46, MRM7m = 47,
-    MRMDestReg   = 48,
-    MRMSrcReg    = 49,
-    MRMSrcRegOp4 = 50,
+    MRMDestReg     = 48,
+    MRMSrcReg      = 49,
+    MRMSrcReg4VOp3 = 50,
+    MRMSrcRegOp4   = 51,
     MRMXr = 55,
     MRM0r = 56, MRM1r = 57, MRM2r = 58, MRM3r = 59,
     MRM4r = 60, MRM5r = 61, MRM6r = 62, MRM7r = 63,
@@ -201,7 +203,6 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
   AdSize           = byteFromRec(Rec, "AdSizeBits");
   HasREX_WPrefix   = Rec->getValueAsBit("hasREX_WPrefix");
   HasVEX_4V        = Rec->getValueAsBit("hasVEX_4V");
-  HasVEX_4VOp3     = Rec->getValueAsBit("hasVEX_4VOp3");
   HasVEX_WPrefix   = Rec->getValueAsBit("hasVEX_WPrefix");
   IgnoresVEX_L     = Rec->getValueAsBit("ignoresVEX_L");
   HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
@@ -553,7 +554,7 @@ void RecognizableInstr::emitInstructionSpecifier() {
   // Given the set of prefix bits, how many additional operands does the
   // instruction have?
   unsigned additionalOperands = 0;
-  if (HasVEX_4V || HasVEX_4VOp3)
+  if (HasVEX_4V)
     ++additionalOperands;
   if (HasEVEX_K)
     ++additionalOperands;
@@ -655,14 +656,17 @@ void RecognizableInstr::emitInstructionSpecifier() {
       HANDLE_OPERAND(vvvvRegister)
 
     HANDLE_OPERAND(rmRegister)
-
-    if (HasVEX_4VOp3)
-      HANDLE_OPERAND(vvvvRegister)
-
     HANDLE_OPTIONAL(immediate)
     HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
     HANDLE_OPTIONAL(immediate)
     break;
+  case X86Local::MRMSrcReg4VOp3:
+    assert(numPhysicalOperands == 3 &&
+           "Unexpected number of operands for MRMSrcRegFrm");
+    HANDLE_OPERAND(roRegister)
+    HANDLE_OPERAND(rmRegister)
+    HANDLE_OPERAND(vvvvRegister)
+    break;
   case X86Local::MRMSrcRegOp4:
     assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 &&
            "Unexpected number of operands for MRMSrcRegOp4Frm");
@@ -693,13 +697,16 @@ void RecognizableInstr::emitInstructionSpecifier() {
       HANDLE_OPERAND(vvvvRegister)
 
     HANDLE_OPERAND(memory)
-
-    if (HasVEX_4VOp3)
-      HANDLE_OPERAND(vvvvRegister)
-
     HANDLE_OPTIONAL(immediate)
     HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
     break;
+  case X86Local::MRMSrcMem4VOp3:
+    assert(numPhysicalOperands == 3 &&
+           "Unexpected number of operands for MRMSrcMemFrm");
+    HANDLE_OPERAND(roRegister)
+    HANDLE_OPERAND(memory)
+    HANDLE_OPERAND(vvvvRegister)
+    break;
   case X86Local::MRMSrcMemOp4:
     assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 &&
            "Unexpected number of operands for MRMSrcMemOp4Frm");
@@ -853,12 +860,14 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
       break;
     case X86Local::MRMDestReg:
     case X86Local::MRMSrcReg:
+    case X86Local::MRMSrcReg4VOp3:
     case X86Local::MRMSrcRegOp4:
     case X86Local::MRMXr:
       filter = new ModFilter(true);
       break;
     case X86Local::MRMDestMem:
     case X86Local::MRMSrcMem:
+    case X86Local::MRMSrcMem4VOp3:
     case X86Local::MRMSrcMemOp4:
     case X86Local::MRMXm:
       filter = new ModFilter(false);