diff options
Diffstat (limited to 'llvm/utils/TableGen/CodeGenSchedule.h')
-rw-r--r-- | llvm/utils/TableGen/CodeGenSchedule.h | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/llvm/utils/TableGen/CodeGenSchedule.h b/llvm/utils/TableGen/CodeGenSchedule.h index 755ffd25b0c..3a30ba9ba2a 100644 --- a/llvm/utils/TableGen/CodeGenSchedule.h +++ b/llvm/utils/TableGen/CodeGenSchedule.h @@ -27,11 +27,11 @@ class CodeGenTarget; class CodeGenSchedModels; class CodeGenInstruction; -typedef std::vector<Record*> RecVec; -typedef std::vector<Record*>::const_iterator RecIter; +using RecVec = std::vector<Record*>; +using RecIter = std::vector<Record*>::const_iterator; -typedef std::vector<unsigned> IdxVec; -typedef std::vector<unsigned>::const_iterator IdxIter; +using IdxVec = std::vector<unsigned>; +using IdxIter = std::vector<unsigned>::const_iterator; void splitSchedReadWrites(const RecVec &RWDefs, RecVec &WriteDefs, RecVec &ReadDefs); @@ -234,7 +234,7 @@ class CodeGenSchedModels { std::vector<CodeGenProcModel> ProcModels; // Map Processor's MachineModel or ProcItin to a CodeGenProcModel index. - typedef DenseMap<Record*, unsigned> ProcModelMapTy; + using ProcModelMapTy = DenseMap<Record*, unsigned>; ProcModelMapTy ProcModelMap; // Per-operand SchedReadWrite types. @@ -252,15 +252,15 @@ class CodeGenSchedModels { // Map each instruction to its unique SchedClass index considering the // combination of it's itinerary class, SchedRW list, and InstRW records. - typedef DenseMap<Record*, unsigned> InstClassMapTy; + using InstClassMapTy = DenseMap<Record*, unsigned>; InstClassMapTy InstrClassMap; public: CodeGenSchedModels(RecordKeeper& RK, const CodeGenTarget &TGT); // iterator access to the scheduling classes. - typedef std::vector<CodeGenSchedClass>::iterator class_iterator; - typedef std::vector<CodeGenSchedClass>::const_iterator const_class_iterator; + using class_iterator = std::vector<CodeGenSchedClass>::iterator; + using const_class_iterator = std::vector<CodeGenSchedClass>::const_iterator; class_iterator classes_begin() { return SchedClasses.begin(); } const_class_iterator classes_begin() const { return SchedClasses.begin(); } class_iterator classes_end() { return SchedClasses.end(); } @@ -306,7 +306,7 @@ public: } // Iterate over the unique processor models. - typedef std::vector<CodeGenProcModel>::const_iterator ProcIter; + using ProcIter = std::vector<CodeGenProcModel>::const_iterator; ProcIter procModelBegin() const { return ProcModels.begin(); } ProcIter procModelEnd() const { return ProcModels.end(); } ArrayRef<CodeGenProcModel> procModels() const { return ProcModels; } @@ -360,7 +360,7 @@ public: // for NoItinerary. unsigned getSchedClassIdx(const CodeGenInstruction &Inst) const; - typedef std::vector<CodeGenSchedClass>::const_iterator SchedClassIter; + using SchedClassIter = std::vector<CodeGenSchedClass>::const_iterator; SchedClassIter schedClassBegin() const { return SchedClasses.begin(); } SchedClassIter schedClassEnd() const { return SchedClasses.end(); } ArrayRef<CodeGenSchedClass> schedClasses() const { return SchedClasses; } |