1 files changed, 6 insertions, 12 deletions
diff --git a/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp b/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp
index 0ef2a707993..0c255ac74e3 100644
--- a/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp
+++ b/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp
@@ -261,13 +261,7 @@ private:
 
 using FakeSnippetGeneratorTest = SnippetGeneratorTest<FakeSnippetGenerator>;
 
-testing::Matcher<const RegisterValue &> IsRegisterValue(unsigned Reg,
-                                                        llvm::APInt Value) {
-  return testing::AllOf(testing::Field(&RegisterValue::Register, Reg),
-                        testing::Field(&RegisterValue::Value, Value));
-}
-
-TEST_F(FakeSnippetGeneratorTest, ComputeRegisterInitialValuesAdd16ri) {
+TEST_F(FakeSnippetGeneratorTest, ComputeRegsToDefAdd16ri) {
   // ADD16ri:
   // explicit def 0       : reg RegClass=GR16
   // explicit use 1       : reg RegClass=GR16 | TIED_TO:0
@@ -278,11 +272,11 @@ TEST_F(FakeSnippetGeneratorTest, ComputeRegisterInitialValuesAdd16ri) {
       llvm::MCOperand::createReg(llvm::X86::AX);
   std::vector<InstructionBuilder> Snippet;
   Snippet.push_back(std::move(IB));
-  const auto RIV = Generator.computeRegisterInitialValues(Snippet);
-  EXPECT_THAT(RIV, ElementsAre(IsRegisterValue(llvm::X86::AX, llvm::APInt())));
+  const auto RegsToDef = Generator.computeRegsToDef(Snippet);
+  EXPECT_THAT(RegsToDef, UnorderedElementsAre(llvm::X86::AX));
 }
 
-TEST_F(FakeSnippetGeneratorTest, ComputeRegisterInitialValuesAdd64rr) {
+TEST_F(FakeSnippetGeneratorTest, ComputeRegsToDefAdd64rr) {
   // ADD64rr:
   //  mov64ri rax, 42
   //  add64rr rax, rax, rbx
@@ -304,8 +298,8 @@ TEST_F(FakeSnippetGeneratorTest, ComputeRegisterInitialValuesAdd64rr) {
     Snippet.push_back(std::move(Add));
   }
 
-  const auto RIV = Generator.computeRegisterInitialValues(Snippet);
-  EXPECT_THAT(RIV, ElementsAre(IsRegisterValue(llvm::X86::RBX, llvm::APInt())));
+  const auto RegsToDef = Generator.computeRegsToDef(Snippet);
+  EXPECT_THAT(RegsToDef, UnorderedElementsAre(llvm::X86::RBX));
 }
 
 } // namespace