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-rw-r--r--llvm/test/MC/AArch64/SVE/fadda-diagnostics.s21
-rw-r--r--llvm/test/MC/AArch64/SVE/fadda.s26
-rw-r--r--llvm/test/MC/AArch64/SVE/faddv-diagnostics.s20
-rw-r--r--llvm/test/MC/AArch64/SVE/faddv.s26
-rw-r--r--llvm/test/MC/AArch64/SVE/fmaxnmv-diagnostics.s20
-rw-r--r--llvm/test/MC/AArch64/SVE/fmaxnmv.s26
-rw-r--r--llvm/test/MC/AArch64/SVE/fmaxv-diagnostics.s20
-rw-r--r--llvm/test/MC/AArch64/SVE/fmaxv.s26
-rw-r--r--llvm/test/MC/AArch64/SVE/fminnmv-diagnostics.s20
-rw-r--r--llvm/test/MC/AArch64/SVE/fminnmv.s26
-rw-r--r--llvm/test/MC/AArch64/SVE/fminv-diagnostics.s20
-rw-r--r--llvm/test/MC/AArch64/SVE/fminv.s26
12 files changed, 277 insertions, 0 deletions
diff --git a/llvm/test/MC/AArch64/SVE/fadda-diagnostics.s b/llvm/test/MC/AArch64/SVE/fadda-diagnostics.s
new file mode 100644
index 00000000000..bff63367b15
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fadda-diagnostics.s
@@ -0,0 +1,21 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+fadda b0, p7, b0, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fadda b0, p7, b0, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fadda h0, p7, h1, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: fadda h0, p7, h1, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fadda h0, p8, h0, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fadda h0, p8, h0, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fadda v0.8h, p7, v0.8h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fadda v0.8h, p7, v0.8h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: \ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SVE/fadda.s b/llvm/test/MC/AArch64/SVE/fadda.s
new file mode 100644
index 00000000000..8f99eb02032
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fadda.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fadda h0, p7, h0, z31.h
+// CHECK-INST: fadda h0, p7, h0, z31.h
+// CHECK-ENCODING: [0xe0,0x3f,0x58,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 58 65 <unknown>
+
+fadda s0, p7, s0, z31.s
+// CHECK-INST: fadda s0, p7, s0, z31.s
+// CHECK-ENCODING: [0xe0,0x3f,0x98,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 98 65 <unknown>
+
+fadda d0, p7, d0, z31.d
+// CHECK-INST: fadda d0, p7, d0, z31.d
+// CHECK-ENCODING: [0xe0,0x3f,0xd8,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f d8 65 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/faddv-diagnostics.s b/llvm/test/MC/AArch64/SVE/faddv-diagnostics.s
new file mode 100644
index 00000000000..37cb19337d9
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/faddv-diagnostics.s
@@ -0,0 +1,20 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+faddv b0, p7, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: faddv b0, p7, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+faddv h0, p8, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: faddv h0, p8, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Result must be a valid FP register.
+
+faddv v0, p7, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: faddv v0, p7, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: \ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SVE/faddv.s b/llvm/test/MC/AArch64/SVE/faddv.s
new file mode 100644
index 00000000000..a6b01928d3b
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/faddv.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+faddv h0, p7, z31.h
+// CHECK-INST: faddv h0, p7, z31.h
+// CHECK-ENCODING: [0xe0,0x3f,0x40,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 40 65 <unknown>
+
+faddv s0, p7, z31.s
+// CHECK-INST: faddv s0, p7, z31.s
+// CHECK-ENCODING: [0xe0,0x3f,0x80,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 80 65 <unknown>
+
+faddv d0, p7, z31.d
+// CHECK-INST: faddv d0, p7, z31.d
+// CHECK-ENCODING: [0xe0,0x3f,0xc0,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f c0 65 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/fmaxnmv-diagnostics.s b/llvm/test/MC/AArch64/SVE/fmaxnmv-diagnostics.s
new file mode 100644
index 00000000000..2eb6191b389
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fmaxnmv-diagnostics.s
@@ -0,0 +1,20 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+fmaxnmv b0, p7, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmaxnmv b0, p7, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmaxnmv h0, p8, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fmaxnmv h0, p8, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Result must be a valid FP register.
+
+fmaxnmv v0, p7, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmaxnmv v0, p7, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: \ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SVE/fmaxnmv.s b/llvm/test/MC/AArch64/SVE/fmaxnmv.s
new file mode 100644
index 00000000000..0f18ae486a7
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fmaxnmv.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fmaxnmv h0, p7, z31.h
+// CHECK-INST: fmaxnmv h0, p7, z31.h
+// CHECK-ENCODING: [0xe0,0x3f,0x44,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 44 65 <unknown>
+
+fmaxnmv s0, p7, z31.s
+// CHECK-INST: fmaxnmv s0, p7, z31.s
+// CHECK-ENCODING: [0xe0,0x3f,0x84,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 84 65 <unknown>
+
+fmaxnmv d0, p7, z31.d
+// CHECK-INST: fmaxnmv d0, p7, z31.d
+// CHECK-ENCODING: [0xe0,0x3f,0xc4,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f c4 65 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/fmaxv-diagnostics.s b/llvm/test/MC/AArch64/SVE/fmaxv-diagnostics.s
new file mode 100644
index 00000000000..d679734e2d6
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fmaxv-diagnostics.s
@@ -0,0 +1,20 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+fmaxv b0, p7, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmaxv b0, p7, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmaxv h0, p8, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fmaxv h0, p8, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Result must be a valid FP register.
+
+fmaxv v0, p7, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmaxv v0, p7, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: \ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SVE/fmaxv.s b/llvm/test/MC/AArch64/SVE/fmaxv.s
new file mode 100644
index 00000000000..cd12d266b4a
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fmaxv.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fmaxv h0, p7, z31.h
+// CHECK-INST: fmaxv h0, p7, z31.h
+// CHECK-ENCODING: [0xe0,0x3f,0x46,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 46 65 <unknown>
+
+fmaxv s0, p7, z31.s
+// CHECK-INST: fmaxv s0, p7, z31.s
+// CHECK-ENCODING: [0xe0,0x3f,0x86,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 86 65 <unknown>
+
+fmaxv d0, p7, z31.d
+// CHECK-INST: fmaxv d0, p7, z31.d
+// CHECK-ENCODING: [0xe0,0x3f,0xc6,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f c6 65 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/fminnmv-diagnostics.s b/llvm/test/MC/AArch64/SVE/fminnmv-diagnostics.s
new file mode 100644
index 00000000000..d613d053a5f
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fminnmv-diagnostics.s
@@ -0,0 +1,20 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+fminnmv b0, p7, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fminnmv b0, p7, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fminnmv h0, p8, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fminnmv h0, p8, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Result must be a valid FP register.
+
+fminnmv v0, p7, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fminnmv v0, p7, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: \ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SVE/fminnmv.s b/llvm/test/MC/AArch64/SVE/fminnmv.s
new file mode 100644
index 00000000000..7391b3565fb
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fminnmv.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fminnmv h0, p7, z31.h
+// CHECK-INST: fminnmv h0, p7, z31.h
+// CHECK-ENCODING: [0xe0,0x3f,0x45,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 45 65 <unknown>
+
+fminnmv s0, p7, z31.s
+// CHECK-INST: fminnmv s0, p7, z31.s
+// CHECK-ENCODING: [0xe0,0x3f,0x85,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 85 65 <unknown>
+
+fminnmv d0, p7, z31.d
+// CHECK-INST: fminnmv d0, p7, z31.d
+// CHECK-ENCODING: [0xe0,0x3f,0xc5,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f c5 65 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/fminv-diagnostics.s b/llvm/test/MC/AArch64/SVE/fminv-diagnostics.s
new file mode 100644
index 00000000000..e1dc7715396
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fminv-diagnostics.s
@@ -0,0 +1,20 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+fminv b0, p7, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fminv b0, p7, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fminv h0, p8, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fminv h0, p8, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Result must be a valid FP register.
+
+fminv v0, p7, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fminv v0, p7, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: \ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SVE/fminv.s b/llvm/test/MC/AArch64/SVE/fminv.s
new file mode 100644
index 00000000000..9b310049ded
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fminv.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fminv h0, p7, z31.h
+// CHECK-INST: fminv h0, p7, z31.h
+// CHECK-ENCODING: [0xe0,0x3f,0x47,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 47 65 <unknown>
+
+fminv s0, p7, z31.s
+// CHECK-INST: fminv s0, p7, z31.s
+// CHECK-ENCODING: [0xe0,0x3f,0x87,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 87 65 <unknown>
+
+fminv d0, p7, z31.d
+// CHECK-INST: fminv d0, p7, z31.d
+// CHECK-ENCODING: [0xe0,0x3f,0xc7,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f c7 65 <unknown>
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