summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td8
-rw-r--r--llvm/lib/Target/AArch64/SVEInstrFormats.td64
-rw-r--r--llvm/test/MC/AArch64/SVE/fadda-diagnostics.s21
-rw-r--r--llvm/test/MC/AArch64/SVE/fadda.s26
-rw-r--r--llvm/test/MC/AArch64/SVE/faddv-diagnostics.s20
-rw-r--r--llvm/test/MC/AArch64/SVE/faddv.s26
-rw-r--r--llvm/test/MC/AArch64/SVE/fmaxnmv-diagnostics.s20
-rw-r--r--llvm/test/MC/AArch64/SVE/fmaxnmv.s26
-rw-r--r--llvm/test/MC/AArch64/SVE/fmaxv-diagnostics.s20
-rw-r--r--llvm/test/MC/AArch64/SVE/fmaxv.s26
-rw-r--r--llvm/test/MC/AArch64/SVE/fminnmv-diagnostics.s20
-rw-r--r--llvm/test/MC/AArch64/SVE/fminnmv.s26
-rw-r--r--llvm/test/MC/AArch64/SVE/fminv-diagnostics.s20
-rw-r--r--llvm/test/MC/AArch64/SVE/fminv.s26
14 files changed, 348 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 8ebe0cea234..12a669a0d05 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -158,6 +158,14 @@ let Predicates = [HasSVE] in {
defm FCMLA_ZZZI : sve_fp_fcmla_by_indexed_elem<"fcmla">;
defm FMUL_ZZZI : sve_fp_fmul_by_indexed_elem<"fmul">;
+ // SVE floating point reductions.
+ defm FADDA_VPZ : sve_fp_2op_p_vd<0b000, "fadda">;
+ defm FADDV_VPZ : sve_fp_fast_red<0b000, "faddv">;
+ defm FMAXNMV_VPZ : sve_fp_fast_red<0b100, "fmaxnmv">;
+ defm FMINNMV_VPZ : sve_fp_fast_red<0b101, "fminnmv">;
+ defm FMAXV_VPZ : sve_fp_fast_red<0b110, "fmaxv">;
+ defm FMINV_VPZ : sve_fp_fast_red<0b111, "fminv">;
+
// Splat immediate (unpredicated)
defm DUP_ZI : sve_int_dup_imm<"dup">;
defm FDUP_ZI : sve_int_dup_fpimm<"fdup">;
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index a82598c320d..92ab1e24d76 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -2083,6 +2083,68 @@ multiclass sve_int_ucmp_vi<bits<2> opc, string asm> {
//===----------------------------------------------------------------------===//
+// SVE Floating Point Fast Reduction Group
+//===----------------------------------------------------------------------===//
+
+class sve_fp_fast_red<bits<2> sz, bits<3> opc, string asm,
+ ZPRRegOp zprty, RegisterClass dstRegClass>
+: I<(outs dstRegClass:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn),
+ asm, "\t$Vd, $Pg, $Zn",
+ "",
+ []>, Sched<[]> {
+ bits<5> Zn;
+ bits<5> Vd;
+ bits<3> Pg;
+ let Inst{31-24} = 0b01100101;
+ let Inst{23-22} = sz;
+ let Inst{21-19} = 0b000;
+ let Inst{18-16} = opc;
+ let Inst{15-13} = 0b001;
+ let Inst{12-10} = Pg;
+ let Inst{9-5} = Zn;
+ let Inst{4-0} = Vd;
+}
+
+multiclass sve_fp_fast_red<bits<3> opc, string asm> {
+ def _H : sve_fp_fast_red<0b01, opc, asm, ZPR16, FPR16>;
+ def _S : sve_fp_fast_red<0b10, opc, asm, ZPR32, FPR32>;
+ def _D : sve_fp_fast_red<0b11, opc, asm, ZPR64, FPR64>;
+}
+
+
+//===----------------------------------------------------------------------===//
+// SVE Floating Point Accumulating Reduction Group
+//===----------------------------------------------------------------------===//
+
+class sve_fp_2op_p_vd<bits<2> sz, bits<3> opc, string asm,
+ ZPRRegOp zprty, RegisterClass dstRegClass>
+: I<(outs dstRegClass:$Vdn), (ins PPR3bAny:$Pg, dstRegClass:$_Vdn, zprty:$Zm),
+ asm, "\t$Vdn, $Pg, $_Vdn, $Zm",
+ "",
+ []>,
+ Sched<[]> {
+ bits<3> Pg;
+ bits<5> Vdn;
+ bits<5> Zm;
+ let Inst{31-24} = 0b01100101;
+ let Inst{23-22} = sz;
+ let Inst{21-19} = 0b011;
+ let Inst{18-16} = opc;
+ let Inst{15-13} = 0b001;
+ let Inst{12-10} = Pg;
+ let Inst{9-5} = Zm;
+ let Inst{4-0} = Vdn;
+
+ let Constraints = "$Vdn = $_Vdn";
+}
+
+multiclass sve_fp_2op_p_vd<bits<3> opc, string asm> {
+ def _H : sve_fp_2op_p_vd<0b01, opc, asm, ZPR16, FPR16>;
+ def _S : sve_fp_2op_p_vd<0b10, opc, asm, ZPR32, FPR32>;
+ def _D : sve_fp_2op_p_vd<0b11, opc, asm, ZPR64, FPR64>;
+}
+
+//===----------------------------------------------------------------------===//
// SVE Floating Point Compare - Vectors Group
//===----------------------------------------------------------------------===//
@@ -4003,4 +4065,4 @@ class sve_int_bin_cons_misc_0_c<bits<8> opc, string asm, ZPRRegOp zprty>
let Inst{10} = opc{0};
let Inst{9-5} = Zn;
let Inst{4-0} = Zd;
-} \ No newline at end of file
+}
diff --git a/llvm/test/MC/AArch64/SVE/fadda-diagnostics.s b/llvm/test/MC/AArch64/SVE/fadda-diagnostics.s
new file mode 100644
index 00000000000..bff63367b15
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fadda-diagnostics.s
@@ -0,0 +1,21 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+fadda b0, p7, b0, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fadda b0, p7, b0, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fadda h0, p7, h1, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: fadda h0, p7, h1, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fadda h0, p8, h0, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fadda h0, p8, h0, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fadda v0.8h, p7, v0.8h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fadda v0.8h, p7, v0.8h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: \ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SVE/fadda.s b/llvm/test/MC/AArch64/SVE/fadda.s
new file mode 100644
index 00000000000..8f99eb02032
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fadda.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fadda h0, p7, h0, z31.h
+// CHECK-INST: fadda h0, p7, h0, z31.h
+// CHECK-ENCODING: [0xe0,0x3f,0x58,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 58 65 <unknown>
+
+fadda s0, p7, s0, z31.s
+// CHECK-INST: fadda s0, p7, s0, z31.s
+// CHECK-ENCODING: [0xe0,0x3f,0x98,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 98 65 <unknown>
+
+fadda d0, p7, d0, z31.d
+// CHECK-INST: fadda d0, p7, d0, z31.d
+// CHECK-ENCODING: [0xe0,0x3f,0xd8,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f d8 65 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/faddv-diagnostics.s b/llvm/test/MC/AArch64/SVE/faddv-diagnostics.s
new file mode 100644
index 00000000000..37cb19337d9
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/faddv-diagnostics.s
@@ -0,0 +1,20 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+faddv b0, p7, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: faddv b0, p7, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+faddv h0, p8, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: faddv h0, p8, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Result must be a valid FP register.
+
+faddv v0, p7, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: faddv v0, p7, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: \ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SVE/faddv.s b/llvm/test/MC/AArch64/SVE/faddv.s
new file mode 100644
index 00000000000..a6b01928d3b
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/faddv.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+faddv h0, p7, z31.h
+// CHECK-INST: faddv h0, p7, z31.h
+// CHECK-ENCODING: [0xe0,0x3f,0x40,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 40 65 <unknown>
+
+faddv s0, p7, z31.s
+// CHECK-INST: faddv s0, p7, z31.s
+// CHECK-ENCODING: [0xe0,0x3f,0x80,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 80 65 <unknown>
+
+faddv d0, p7, z31.d
+// CHECK-INST: faddv d0, p7, z31.d
+// CHECK-ENCODING: [0xe0,0x3f,0xc0,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f c0 65 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/fmaxnmv-diagnostics.s b/llvm/test/MC/AArch64/SVE/fmaxnmv-diagnostics.s
new file mode 100644
index 00000000000..2eb6191b389
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fmaxnmv-diagnostics.s
@@ -0,0 +1,20 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+fmaxnmv b0, p7, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmaxnmv b0, p7, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmaxnmv h0, p8, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fmaxnmv h0, p8, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Result must be a valid FP register.
+
+fmaxnmv v0, p7, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmaxnmv v0, p7, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: \ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SVE/fmaxnmv.s b/llvm/test/MC/AArch64/SVE/fmaxnmv.s
new file mode 100644
index 00000000000..0f18ae486a7
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fmaxnmv.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fmaxnmv h0, p7, z31.h
+// CHECK-INST: fmaxnmv h0, p7, z31.h
+// CHECK-ENCODING: [0xe0,0x3f,0x44,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 44 65 <unknown>
+
+fmaxnmv s0, p7, z31.s
+// CHECK-INST: fmaxnmv s0, p7, z31.s
+// CHECK-ENCODING: [0xe0,0x3f,0x84,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 84 65 <unknown>
+
+fmaxnmv d0, p7, z31.d
+// CHECK-INST: fmaxnmv d0, p7, z31.d
+// CHECK-ENCODING: [0xe0,0x3f,0xc4,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f c4 65 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/fmaxv-diagnostics.s b/llvm/test/MC/AArch64/SVE/fmaxv-diagnostics.s
new file mode 100644
index 00000000000..d679734e2d6
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fmaxv-diagnostics.s
@@ -0,0 +1,20 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+fmaxv b0, p7, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmaxv b0, p7, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmaxv h0, p8, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fmaxv h0, p8, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Result must be a valid FP register.
+
+fmaxv v0, p7, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fmaxv v0, p7, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: \ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SVE/fmaxv.s b/llvm/test/MC/AArch64/SVE/fmaxv.s
new file mode 100644
index 00000000000..cd12d266b4a
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fmaxv.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fmaxv h0, p7, z31.h
+// CHECK-INST: fmaxv h0, p7, z31.h
+// CHECK-ENCODING: [0xe0,0x3f,0x46,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 46 65 <unknown>
+
+fmaxv s0, p7, z31.s
+// CHECK-INST: fmaxv s0, p7, z31.s
+// CHECK-ENCODING: [0xe0,0x3f,0x86,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 86 65 <unknown>
+
+fmaxv d0, p7, z31.d
+// CHECK-INST: fmaxv d0, p7, z31.d
+// CHECK-ENCODING: [0xe0,0x3f,0xc6,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f c6 65 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/fminnmv-diagnostics.s b/llvm/test/MC/AArch64/SVE/fminnmv-diagnostics.s
new file mode 100644
index 00000000000..d613d053a5f
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fminnmv-diagnostics.s
@@ -0,0 +1,20 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+fminnmv b0, p7, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fminnmv b0, p7, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fminnmv h0, p8, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fminnmv h0, p8, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Result must be a valid FP register.
+
+fminnmv v0, p7, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fminnmv v0, p7, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: \ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SVE/fminnmv.s b/llvm/test/MC/AArch64/SVE/fminnmv.s
new file mode 100644
index 00000000000..7391b3565fb
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fminnmv.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fminnmv h0, p7, z31.h
+// CHECK-INST: fminnmv h0, p7, z31.h
+// CHECK-ENCODING: [0xe0,0x3f,0x45,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 45 65 <unknown>
+
+fminnmv s0, p7, z31.s
+// CHECK-INST: fminnmv s0, p7, z31.s
+// CHECK-ENCODING: [0xe0,0x3f,0x85,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 85 65 <unknown>
+
+fminnmv d0, p7, z31.d
+// CHECK-INST: fminnmv d0, p7, z31.d
+// CHECK-ENCODING: [0xe0,0x3f,0xc5,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f c5 65 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/fminv-diagnostics.s b/llvm/test/MC/AArch64/SVE/fminv-diagnostics.s
new file mode 100644
index 00000000000..e1dc7715396
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fminv-diagnostics.s
@@ -0,0 +1,20 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+fminv b0, p7, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fminv b0, p7, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fminv h0, p8, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fminv h0, p8, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Result must be a valid FP register.
+
+fminv v0, p7, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fminv v0, p7, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: \ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SVE/fminv.s b/llvm/test/MC/AArch64/SVE/fminv.s
new file mode 100644
index 00000000000..9b310049ded
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fminv.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fminv h0, p7, z31.h
+// CHECK-INST: fminv h0, p7, z31.h
+// CHECK-ENCODING: [0xe0,0x3f,0x47,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 47 65 <unknown>
+
+fminv s0, p7, z31.s
+// CHECK-INST: fminv s0, p7, z31.s
+// CHECK-ENCODING: [0xe0,0x3f,0x87,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 87 65 <unknown>
+
+fminv d0, p7, z31.d
+// CHECK-INST: fminv d0, p7, z31.d
+// CHECK-ENCODING: [0xe0,0x3f,0xc7,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f c7 65 <unknown>
OpenPOWER on IntegriCloud