diff options
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/Mips/cconv/callee-saved-float.ll | 4 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt | 6 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/micromips32r6/invalid-wrong-error.s | 2 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/micromips32r6/valid.s | 6 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/mips32r5/invalid.s | 6 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/mips64r5/invalid.s | 10 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/mips64r6/invalid.s | 3 |
7 files changed, 7 insertions, 30 deletions
diff --git a/llvm/test/CodeGen/Mips/cconv/callee-saved-float.ll b/llvm/test/CodeGen/Mips/cconv/callee-saved-float.ll index 2aaa1b10a09..c84f0f439c2 100644 --- a/llvm/test/CodeGen/Mips/cconv/callee-saved-float.ll +++ b/llvm/test/CodeGen/Mips/cconv/callee-saved-float.ll @@ -17,7 +17,6 @@ ; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s ; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=ALL-INV --check-prefix=N64-INV %s ; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=ALL-INV --check-prefix=N64-INV %s -; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -filetype=obj < %s -o - | llvm-objdump -no-show-raw-insn -arch mips -mcpu=mips32r6 -mattr=micromips -d - | FileCheck --check-prefix=MM32R6 %s ; Test the the callee-saved registers are callee-saved as specified by section ; 2 of the MIPSpro N32 Handbook and section 3 of the SYSV ABI spec. @@ -110,6 +109,3 @@ entry: ; N64-DAG: ldc1 [[F30]], [[OFF30]]($sp) ; N64-DAG: ldc1 [[F31]], [[OFF31]]($sp) ; N64: addiu $sp, $sp, 64 - -; Check the mapping between LDC164 and LDC1_64_MMR6. -; MM32R6: ldc1 diff --git a/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt b/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt index 737e169b7d4..13a9abfee14 100644 --- a/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt +++ b/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt @@ -60,10 +60,6 @@ 0x20 0x25 0x60 0x08 # CHECK: cache 1, 8($5) 0x01 0x65 0x4b 0x3c # CHECK: clo $11, $5 0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp -0x54 0x22 0x10 0x3b # CHECK: cfc1 $1, $2 -0x00 0x64 0xcd 0x3c # CHECK: cfc2 $3, $4 -0x54 0xa6 0x18 0x3b # CHECK: ctc1 $5, $6 -0x00 0xe8 0xdd 0x3c # CHECK: ctc2 $7, $8 0x00 0x00 0xe3 0x7c # CHECK: deret 0x00 0xa4 0x19 0x18 # CHECK: div $3, $4, $5 0x00 0xa4 0x19 0x98 # CHECK: divu $3, $4, $5 @@ -83,8 +79,6 @@ 0x20 0x44 0xd0 0x08 # CHECK: swm32 $16, $17, 8($4) 0x00 0x00 0x8b 0x7c # CHECK: syscall 0x01 0x8c 0x8b 0x7c # CHECK: syscall 396 -0xbd 0x0a 0x01 0x2c # CHECK: ldc1 $f8, 300($10) -0x21 0x6c 0x23 0xff # CHECK: ldc2 $11, 1023($12) 0x78 0x48 0x00 0x43 # CHECK: lwpc $2, 268 0x00 0x43 0x26 0x0f # CHECK: lsa $2, $3, $4, 4 0x00 0xa4 0x19 0x58 # CHECK: mod $3, $4, $5 diff --git a/llvm/test/MC/Mips/micromips32r6/invalid-wrong-error.s b/llvm/test/MC/Mips/micromips32r6/invalid-wrong-error.s index d31502c4f8c..39f1731862c 100644 --- a/llvm/test/MC/Mips/micromips32r6/invalid-wrong-error.s +++ b/llvm/test/MC/Mips/micromips32r6/invalid-wrong-error.s @@ -7,8 +7,6 @@ # the diagnostic for the 10-bit form. This isn't exactly wrong but it is # misleading. Ideally, we'd emit every way to achieve a valid match instead # of picking only one. - ldc2 $11, -1025($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - ldc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled teq $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate teq $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate teq $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled diff --git a/llvm/test/MC/Mips/micromips32r6/valid.s b/llvm/test/MC/Mips/micromips32r6/valid.s index 39b4cf51b47..041915711a4 100644 --- a/llvm/test/MC/Mips/micromips32r6/valid.s +++ b/llvm/test/MC/Mips/micromips32r6/valid.s @@ -45,10 +45,6 @@ cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0x20,0x25,0x60,0x08] clo $11, $a1 # CHECK: clo $11, $5 # encoding: [0x01,0x65,0x4b,0x3c] clz $sp, $gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50] - cfc1 $1, $2 # CHECK: cfc1 $1, $2 # encoding: [0x54,0x22,0x10,0x3b] - cfc2 $3, $4 # CHECK: cfc2 $3, $4 # encoding: [0x00,0x64,0xcd,0x3c] - ctc1 $5, $6 # CHECK: ctc1 $5, $6 # encoding: [0x54,0xa6,0x18,0x3b] - ctc2 $7, $8 # CHECK: ctc2 $7, $8 # encoding: [0x00,0xe8,0xdd,0x3c] div $3, $4, $5 # CHECK: div $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x18] divu $3, $4, $5 # CHECK: divu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x98] ehb # CHECK: ehb # encoding: [0x00,0x00,0x18,0x00] @@ -65,8 +61,6 @@ jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xa0,0x05,0x01,0x00] jrc16 $9 # CHECK: jrc16 $9 # encoding: [0x45,0x23] jrcaddiusp 20 # CHECK: jrcaddiusp 20 # encoding: [0x44,0xb3] - ldc1 $f8, 300($10) # CHECK: ldc1 $f8, 300($10) # encoding: [0xbd,0x0a,0x01,0x2c] - ldc2 $11, 1023($12) # CHECK: ldc2 $11, 1023($12) # encoding: [0x21,0x6c,0x23,0xff] lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x43,0x24,0x0f] lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0x78,0x48,0x00,0x43] lwm $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22] diff --git a/llvm/test/MC/Mips/mips32r5/invalid.s b/llvm/test/MC/Mips/mips32r5/invalid.s index b51975fedde..e74a23d03d5 100644 --- a/llvm/test/MC/Mips/mips32r5/invalid.s +++ b/llvm/test/MC/Mips/mips32r5/invalid.s @@ -10,8 +10,8 @@ cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different - ldc2 $11, -32769($12) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset - ldc2 $11, 32768($12) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset + pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate + pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate mtc0 $4, $3, -1 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate mtc0 $4, $3, 8 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate mtc2 $4, $3, -1 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate @@ -20,5 +20,3 @@ mfc0 $4, $3, 8 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate mfc2 $4, $3, -1 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate mfc2 $4, $3, 8 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate - pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate - pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate diff --git a/llvm/test/MC/Mips/mips64r5/invalid.s b/llvm/test/MC/Mips/mips64r5/invalid.s index 26faa8d1d26..a88fb06d11d 100644 --- a/llvm/test/MC/Mips/mips64r5/invalid.s +++ b/llvm/test/MC/Mips/mips64r5/invalid.s @@ -10,13 +10,11 @@ cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate drotr32 $2, $3, -1 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate drotr32 $2, $3, 32 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate - dmtc0 $4, $3, -1 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate - dmtc0 $4, $3, 8 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate - dmfc0 $4, $3, -1 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate - dmfc0 $4, $3, 8 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate jalr.hb $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different jalr.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different - ldc2 $11, -32769($12) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset - ldc2 $11, 32768($12) # CHECK: :[[@LINE]]:19: error: expected memory with 16-bit signed offset pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate + dmtc0 $4, $3, -1 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate + dmtc0 $4, $3, 8 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate + dmfc0 $4, $3, -1 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate + dmfc0 $4, $3, 8 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate diff --git a/llvm/test/MC/Mips/mips64r6/invalid.s b/llvm/test/MC/Mips/mips64r6/invalid.s index d1b31376f21..a28b234ac15 100644 --- a/llvm/test/MC/Mips/mips64r6/invalid.s +++ b/llvm/test/MC/Mips/mips64r6/invalid.s @@ -12,6 +12,7 @@ local_label: align $4, $2, $3, 4 # CHECK: :[[@LINE]]:29: error: expected 2-bit unsigned immediate jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different + ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled break -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate break 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate break -1, 5 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate @@ -38,8 +39,6 @@ local_label: drotr32 $2, $3, 32 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate jalr.hb $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different jalr.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different - ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - ldc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled lsa $2, $3, $4, 0 # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4 lsa $2, $3, $4, 5 # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4 pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate |
