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-rw-r--r--llvm/test/Transforms/InstCombine/zext-phi.ll9
1 files changed, 6 insertions, 3 deletions
diff --git a/llvm/test/Transforms/InstCombine/zext-phi.ll b/llvm/test/Transforms/InstCombine/zext-phi.ll
index 5d64b0582f0..5e352415c74 100644
--- a/llvm/test/Transforms/InstCombine/zext-phi.ll
+++ b/llvm/test/Transforms/InstCombine/zext-phi.ll
@@ -2,16 +2,19 @@
target datalayout = "e-m:e-i64:64-n8:16:32:64"
+; Although i1 is not in the datalayout, we should treat it
+; as a legal type because it is a fundamental type in IR.
+; This means we should shrink the phi (sink the zexts).
+
define i64 @sink_i1_casts(i1 %cond1, i1 %cond2) {
; CHECK-LABEL: @sink_i1_casts(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[Z1:%.*]] = zext i1 %cond1 to i64
; CHECK-NEXT: br i1 %cond1, label %if, label %end
; CHECK: if:
-; CHECK-NEXT: [[Z2:%.*]] = zext i1 %cond2 to i64
; CHECK-NEXT: br label %end
; CHECK: end:
-; CHECK-NEXT: [[PHI:%.*]] = phi i64 [ [[Z1]], %entry ], [ [[Z2]], %if ]
+; CHECK-NEXT: [[PHI_IN:%.*]] = phi i1 [ %cond1, %entry ], [ %cond2, %if ]
+; CHECK-NEXT: [[PHI:%.*]] = zext i1 [[PHI_IN]] to i64
; CHECK-NEXT: ret i64 [[PHI]]
;
entry:
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