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-rw-r--r--llvm/lib/Transforms/InstCombine/InstructionCombining.cpp12
-rw-r--r--llvm/test/Transforms/InstCombine/zext-phi.ll9
2 files changed, 14 insertions, 7 deletions
diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
index 851569c4a3d..b74b3273acd 100644
--- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
@@ -89,11 +89,13 @@ Value *InstCombiner::EmitGEPOffset(User *GEP) {
/// Return true if it is desirable to convert an integer computation from a
/// given bit width to a new bit width.
/// We don't want to convert from a legal to an illegal type or from a smaller
-/// to a larger illegal type.
+/// to a larger illegal type. A width of '1' is always treated as a legal type
+/// because i1 is a fundamental type in IR, and there are many specialized
+/// optimizations for i1 types.
bool InstCombiner::shouldChangeType(unsigned FromWidth,
unsigned ToWidth) const {
- bool FromLegal = DL.isLegalInteger(FromWidth);
- bool ToLegal = DL.isLegalInteger(ToWidth);
+ bool FromLegal = FromWidth == 1 || DL.isLegalInteger(FromWidth);
+ bool ToLegal = ToWidth == 1 || DL.isLegalInteger(ToWidth);
// If this is a legal integer from type, and the result would be an illegal
// type, don't do the transformation.
@@ -110,7 +112,9 @@ bool InstCombiner::shouldChangeType(unsigned FromWidth,
/// Return true if it is desirable to convert a computation from 'From' to 'To'.
/// We don't want to convert from a legal to an illegal type or from a smaller
-/// to a larger illegal type.
+/// to a larger illegal type. i1 is always treated as a legal type because it is
+/// a fundamental type in IR, and there are many specialized optimizations for
+/// i1 types.
bool InstCombiner::shouldChangeType(Type *From, Type *To) const {
assert(From->isIntegerTy() && To->isIntegerTy());
diff --git a/llvm/test/Transforms/InstCombine/zext-phi.ll b/llvm/test/Transforms/InstCombine/zext-phi.ll
index 5d64b0582f0..5e352415c74 100644
--- a/llvm/test/Transforms/InstCombine/zext-phi.ll
+++ b/llvm/test/Transforms/InstCombine/zext-phi.ll
@@ -2,16 +2,19 @@
target datalayout = "e-m:e-i64:64-n8:16:32:64"
+; Although i1 is not in the datalayout, we should treat it
+; as a legal type because it is a fundamental type in IR.
+; This means we should shrink the phi (sink the zexts).
+
define i64 @sink_i1_casts(i1 %cond1, i1 %cond2) {
; CHECK-LABEL: @sink_i1_casts(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[Z1:%.*]] = zext i1 %cond1 to i64
; CHECK-NEXT: br i1 %cond1, label %if, label %end
; CHECK: if:
-; CHECK-NEXT: [[Z2:%.*]] = zext i1 %cond2 to i64
; CHECK-NEXT: br label %end
; CHECK: end:
-; CHECK-NEXT: [[PHI:%.*]] = phi i64 [ [[Z1]], %entry ], [ [[Z2]], %if ]
+; CHECK-NEXT: [[PHI_IN:%.*]] = phi i1 [ %cond1, %entry ], [ %cond2, %if ]
+; CHECK-NEXT: [[PHI:%.*]] = zext i1 [[PHI_IN]] to i64
; CHECK-NEXT: ret i64 [[PHI]]
;
entry:
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