diff options
Diffstat (limited to 'llvm/test/tools/llvm-mca')
86 files changed, 15775 insertions, 0 deletions
diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/add-sequence.s b/llvm/test/tools/llvm-mca/X86/BdVer2/add-sequence.s new file mode 100644 index 00000000000..287095b7fb5 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/add-sequence.s @@ -0,0 +1,95 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1000 -timeline < %s | FileCheck %s + +add %eax, %ecx +add %esi, %eax +add %eax, %edx + +# CHECK: Iterations: 1000 +# CHECK-NEXT: Instructions: 3000 +# CHECK-NEXT: Total Cycles: 1004 +# CHECK-NEXT: Total uOps: 3000 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 2.99 +# CHECK-NEXT: IPC: 2.99 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 0.33 addl %eax, %ecx +# CHECK-NEXT: 1 1 0.33 addl %esi, %eax +# CHECK-NEXT: 1 1 0.33 addl %eax, %edx + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - - - - addl %eax, %ecx +# CHECK-NEXT: - - - - - 1.00 - - addl %esi, %eax +# CHECK-NEXT: - - 1.00 - - - - - addl %eax, %edx + +# CHECK: Timeline view: +# CHECK-NEXT: 0123 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeER . . . addl %eax, %ecx +# CHECK-NEXT: [0,1] DeER . . . addl %esi, %eax +# CHECK-NEXT: [0,2] D=eER. . . addl %eax, %edx +# CHECK-NEXT: [1,0] D=eER. . . addl %eax, %ecx +# CHECK-NEXT: [1,1] .DeER. . . addl %esi, %eax +# CHECK-NEXT: [1,2] .D=eER . . addl %eax, %edx +# CHECK-NEXT: [2,0] .D=eER . . addl %eax, %ecx +# CHECK-NEXT: [2,1] .D=eER . . addl %esi, %eax +# CHECK-NEXT: [2,2] . D=eER . . addl %eax, %edx +# CHECK-NEXT: [3,0] . D=eER . . addl %eax, %ecx +# CHECK-NEXT: [3,1] . D=eER . . addl %esi, %eax +# CHECK-NEXT: [3,2] . D==eER . . addl %eax, %edx +# CHECK-NEXT: [4,0] . D=eER . . addl %eax, %ecx +# CHECK-NEXT: [4,1] . D=eER . . addl %esi, %eax +# CHECK-NEXT: [4,2] . D==eER . . addl %eax, %edx +# CHECK-NEXT: [5,0] . D==eER . . addl %eax, %ecx +# CHECK-NEXT: [5,1] . D=eER . . addl %esi, %eax +# CHECK-NEXT: [5,2] . D==eER. . addl %eax, %edx +# CHECK-NEXT: [6,0] . D==eER. . addl %eax, %ecx +# CHECK-NEXT: [6,1] . D==eER. . addl %esi, %eax +# CHECK-NEXT: [6,2] . D==eER . addl %eax, %edx +# CHECK-NEXT: [7,0] . D==eER . addl %eax, %ecx +# CHECK-NEXT: [7,1] . D==eER . addl %esi, %eax +# CHECK-NEXT: [7,2] . D===eER . addl %eax, %edx +# CHECK-NEXT: [8,0] . .D==eER . addl %eax, %ecx +# CHECK-NEXT: [8,1] . .D==eER . addl %esi, %eax +# CHECK-NEXT: [8,2] . .D===eER. addl %eax, %edx +# CHECK-NEXT: [9,0] . .D===eER. addl %eax, %ecx +# CHECK-NEXT: [9,1] . . D==eER. addl %esi, %eax +# CHECK-NEXT: [9,2] . . D===eER addl %eax, %edx + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 10 2.5 0.1 0.0 addl %eax, %ecx +# CHECK-NEXT: 1. 10 2.2 0.1 0.0 addl %esi, %eax +# CHECK-NEXT: 2. 10 3.0 0.0 0.0 addl %eax, %edx diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/clear-super-register-1.s b/llvm/test/tools/llvm-mca/X86/BdVer2/clear-super-register-1.s new file mode 100644 index 00000000000..c8e18731a3e --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/clear-super-register-1.s @@ -0,0 +1,63 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=100 -resource-pressure=false -timeline -timeline-max-iterations=2 < %s | FileCheck %s + +## Sets register RAX. +imulq $5, %rcx, %rax + +## Kills the previous definition of RAX. +## The upper portion of RAX is cleared. +lzcnt %ecx, %eax + +## The AND can start immediately after the LZCNT. +## It doesn't need to wait for the IMUL. +and %rcx, %rax +bsf %rax, %rcx + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 400 +# CHECK-NEXT: Total Cycles: 803 +# CHECK-NEXT: Total uOps: 400 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.50 +# CHECK-NEXT: IPC: 0.50 +# CHECK-NEXT: Block RThroughput: 3.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 imulq $5, %rcx, %rax +# CHECK-NEXT: 1 3 1.00 lzcntl %ecx, %eax +# CHECK-NEXT: 1 1 0.33 andq %rcx, %rax +# CHECK-NEXT: 1 3 1.00 bsfq %rax, %rcx + +# CHECK: Timeline view: +# CHECK-NEXT: 012345678 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeeeER . . . imulq $5, %rcx, %rax +# CHECK-NEXT: [0,1] D=eeeER . . . lzcntl %ecx, %eax +# CHECK-NEXT: [0,2] D====eER . . . andq %rcx, %rax +# CHECK-NEXT: [0,3] D=====eeeER . . bsfq %rax, %rcx +# CHECK-NEXT: [1,0] .D=======eeeER . . imulq $5, %rcx, %rax +# CHECK-NEXT: [1,1] .D========eeeER. . lzcntl %ecx, %eax +# CHECK-NEXT: [1,2] .D===========eER . andq %rcx, %rax +# CHECK-NEXT: [1,3] .D============eeeER bsfq %rax, %rcx + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 4.5 0.5 0.0 imulq $5, %rcx, %rax +# CHECK-NEXT: 1. 2 5.5 1.5 0.0 lzcntl %ecx, %eax +# CHECK-NEXT: 2. 2 8.5 0.0 0.0 andq %rcx, %rax +# CHECK-NEXT: 3. 2 9.5 0.0 0.0 bsfq %rax, %rcx diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/clear-super-register-2.s b/llvm/test/tools/llvm-mca/X86/BdVer2/clear-super-register-2.s new file mode 100644 index 00000000000..99f463c3509 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/clear-super-register-2.s @@ -0,0 +1,137 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=100 -resource-pressure=false -timeline -timeline-max-iterations=2 < %s | FileCheck %s + +# In this test, the VDIVPS takes 38 cycles to write to register YMM3. The first +# VADDPS does not depend on the VDIVPS (the WAW dependency is eliminated at +# register renaming stage). So the first VADDPS can be executed in parallel to +# the VDIVPS. That VADDPS also writes to register XMM3, and the upper half of +# YMM3 is implicitly cleared. As a consequence, the definition of YMM3 from the +# VDIVPS is killed, and the subsequent VADDPS instructions don't need to wait +# for the VDIVPS to complete. +# The block reciprocal throughput is limited by the VDIVPS reciprocal throughput +# (which is 38 cycles). The sequence of VADDPS can be executed in parallel on +# the FPA unit; their latency is "hidden" by the long latency of the VDIVPS. + +vdivps %ymm0, %ymm1, %ymm3 +vaddps %xmm0, %xmm1, %xmm3 +vaddps %ymm3, %ymm1, %ymm4 +vaddps %ymm3, %ymm1, %ymm4 +vaddps %ymm3, %ymm1, %ymm4 +vaddps %ymm3, %ymm1, %ymm4 +vaddps %ymm3, %ymm1, %ymm4 +vaddps %ymm3, %ymm1, %ymm4 +vaddps %ymm3, %ymm1, %ymm4 +vaddps %ymm3, %ymm1, %ymm4 +vaddps %ymm3, %ymm1, %ymm4 +vaddps %ymm3, %ymm1, %ymm4 +vaddps %ymm3, %ymm1, %ymm4 +vaddps %ymm3, %ymm1, %ymm4 +vaddps %ymm3, %ymm1, %ymm4 +vaddps %ymm3, %ymm1, %ymm4 +vaddps %ymm3, %ymm1, %ymm4 +vandps %xmm4, %xmm1, %xmm0 + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 1800 +# CHECK-NEXT: Total Cycles: 2804 +# CHECK-NEXT: Total uOps: 2000 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.71 +# CHECK-NEXT: IPC: 0.64 +# CHECK-NEXT: Block RThroughput: 28.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 3 29 28.00 vdivps %ymm0, %ymm1, %ymm3 +# CHECK-NEXT: 1 3 1.00 vaddps %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: 1 3 1.00 vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: 1 3 1.00 vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: 1 3 1.00 vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: 1 3 1.00 vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: 1 3 1.00 vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: 1 3 1.00 vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: 1 3 1.00 vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: 1 3 1.00 vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: 1 3 1.00 vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: 1 3 1.00 vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: 1 3 1.00 vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: 1 3 1.00 vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: 1 3 1.00 vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: 1 3 1.00 vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: 1 3 1.00 vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: 1 1 1.00 vandps %xmm4, %xmm1, %xmm0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 0123456789 0123456789 +# CHECK-NEXT: Index 0123456789 0123456789 0123456789 + +# CHECK: [0,0] DeeeeeeeeeeeeeeeeeeeeeeeeeeeeeER . . . . . . vdivps %ymm0, %ymm1, %ymm3 +# CHECK-NEXT: [0,1] DeeeE--------------------------R . . . . . . vaddps %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: [0,2] .D==eeeE-----------------------R . . . . . . vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: [0,3] .D===eeeE----------------------R . . . . . . vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: [0,4] .D====eeeE---------------------R . . . . . . vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: [0,5] .D=====eeeE--------------------R . . . . . . vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: [0,6] . D=====eeeE-------------------R . . . . . . vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: [0,7] . D======eeeE------------------R . . . . . . vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: [0,8] . D=======eeeE-----------------R . . . . . . vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: [0,9] . D========eeeE----------------R . . . . . . vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: [0,10] . D========eeeE---------------R . . . . . . vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: [0,11] . D=========eeeE--------------R . . . . . . vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: [0,12] . D==========eeeE-------------R . . . . . . vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: [0,13] . D===========eeeE------------R . . . . . . vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: [0,14] . D===========eeeE-----------R . . . . . . vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: [0,15] . D============eeeE----------R . . . . . . vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: [0,16] . D=============eeeE---------R . . . . . . vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: [0,17] . D================eE--------R . . . . . . vandps %xmm4, %xmm1, %xmm0 +# CHECK-NEXT: [1,0] . D=======================eeeeeeeeeeeeeeeeeeeeeeeeeeeeeER vdivps %ymm0, %ymm1, %ymm3 +# CHECK-NEXT: [1,1] . D================eeeE---------------------------------R vaddps %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: [1,2] . .D==================eeeE------------------------------R vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: [1,3] . .D===================eeeE-----------------------------R vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: [1,4] . .D====================eeeE----------------------------R vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: [1,5] . .D=====================eeeE---------------------------R vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: [1,6] . . D=====================eeeE--------------------------R vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: [1,7] . . D======================eeeE-------------------------R vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: [1,8] . . D=======================eeeE------------------------R vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: [1,9] . . D========================eeeE-----------------------R vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: [1,10] . . D========================eeeE----------------------R vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: [1,11] . . D=========================eeeE---------------------R vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: [1,12] . . D==========================eeeE--------------------R vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: [1,13] . . D===========================eeeE-------------------R vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: [1,14] . . D===========================eeeE------------------R vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: [1,15] . . D============================eeeE-----------------R vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: [1,16] . . D=============================eeeE----------------R vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: [1,17] . . D================================eE---------------R vandps %xmm4, %xmm1, %xmm0 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 12.5 4.0 0.0 vdivps %ymm0, %ymm1, %ymm3 +# CHECK-NEXT: 1. 2 9.0 0.5 29.5 vaddps %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: 2. 2 11.0 0.0 26.5 vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: 3. 2 12.0 1.0 25.5 vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: 4. 2 13.0 2.0 24.5 vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: 5. 2 14.0 3.0 23.5 vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: 6. 2 14.0 4.0 22.5 vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: 7. 2 15.0 5.0 21.5 vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: 8. 2 16.0 6.0 20.5 vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: 9. 2 17.0 7.0 19.5 vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: 10. 2 17.0 8.0 18.5 vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: 11. 2 18.0 9.0 17.5 vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: 12. 2 19.0 10.0 16.5 vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: 13. 2 20.0 11.0 15.5 vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: 14. 2 20.0 12.0 14.5 vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: 15. 2 21.0 13.0 13.5 vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: 16. 2 22.0 14.0 12.5 vaddps %ymm3, %ymm1, %ymm4 +# CHECK-NEXT: 17. 2 25.0 0.0 11.5 vandps %xmm4, %xmm1, %xmm0 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/dependency-breaking-cmp.s b/llvm/test/tools/llvm-mca/X86/BdVer2/dependency-breaking-cmp.s new file mode 100644 index 00000000000..c51fb3677dd --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/dependency-breaking-cmp.s @@ -0,0 +1,72 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -timeline -timeline-max-iterations=3 -iterations=1500 < %s | FileCheck %s + +# Perf stat reports an IPC of 1.97 for this block of code. + +# The CMP instruction doesn't depend on the value of EAX. It can set the flags +# without having to read the inputs. + +cmp %eax, %eax +cmovae %ebx, %eax + +# CHECK: Iterations: 1500 +# CHECK-NEXT: Instructions: 3000 +# CHECK-NEXT: Total Cycles: 4503 +# CHECK-NEXT: Total uOps: 4500 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.00 +# CHECK-NEXT: IPC: 0.67 +# CHECK-NEXT: Block RThroughput: 0.8 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 0.33 cmpl %eax, %eax +# CHECK-NEXT: 2 2 0.67 cmovael %ebx, %eax + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - - - 1.00 - - cmpl %eax, %eax +# CHECK-NEXT: - - 1.00 1.00 - - - - cmovael %ebx, %eax + +# CHECK: Timeline view: +# CHECK-NEXT: 01 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeER . .. cmpl %eax, %eax +# CHECK-NEXT: [0,1] D=eeER .. cmovael %ebx, %eax +# CHECK-NEXT: [1,0] D===eER .. cmpl %eax, %eax +# CHECK-NEXT: [1,1] .D===eeER .. cmovael %ebx, %eax +# CHECK-NEXT: [2,0] .D=====eER.. cmpl %eax, %eax +# CHECK-NEXT: [2,1] . D=====eeER cmovael %ebx, %eax + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 3.7 0.3 0.0 cmpl %eax, %eax +# CHECK-NEXT: 1. 3 4.0 0.0 0.0 cmovael %ebx, %eax diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/dependency-breaking-pcmpeq.s b/llvm/test/tools/llvm-mca/X86/BdVer2/dependency-breaking-pcmpeq.s new file mode 100644 index 00000000000..e72ce0c7ba5 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/dependency-breaking-pcmpeq.s @@ -0,0 +1,87 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -timeline -timeline-max-iterations=3 -iterations=1500 < %s | FileCheck %s + +# perf stat reports an IPC of 2.00 for this block of code. + +# All of the vector packed compares from this test are dependency breaking +# instructions. That means, there is no RAW dependency between any of the +# instructions, and the code can be fully parallelized in hardware. + +vpcmpeqb %xmm0, %xmm0, %xmm1 +vpcmpeqw %xmm1, %xmm1, %xmm2 +vpcmpeqd %xmm2, %xmm2, %xmm3 +vpcmpeqq %xmm3, %xmm3, %xmm0 + +# CHECK: Iterations: 1500 +# CHECK-NEXT: Instructions: 6000 +# CHECK-NEXT: Total Cycles: 6003 +# CHECK-NEXT: Total uOps: 6000 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.00 +# CHECK-NEXT: IPC: 1.00 +# CHECK-NEXT: Block RThroughput: 2.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 0.50 vpcmpeqb %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: 1 1 0.50 vpcmpeqw %xmm1, %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpcmpeqd %xmm2, %xmm2, %xmm3 +# CHECK-NEXT: 1 1 0.50 vpcmpeqq %xmm3, %xmm3, %xmm0 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - - 2.00 - 2.00 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - - - 1.00 - - vpcmpeqb %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: - - - 1.00 - - - - vpcmpeqw %xmm1, %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vpcmpeqd %xmm2, %xmm2, %xmm3 +# CHECK-NEXT: - - - 1.00 - - - - vpcmpeqq %xmm3, %xmm3, %xmm0 + +# CHECK: Timeline view: +# CHECK-NEXT: 01234 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeER . . . vpcmpeqb %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: [0,1] D=eER. . . vpcmpeqw %xmm1, %xmm1, %xmm2 +# CHECK-NEXT: [0,2] D==eER . . vpcmpeqd %xmm2, %xmm2, %xmm3 +# CHECK-NEXT: [0,3] D===eER . . vpcmpeqq %xmm3, %xmm3, %xmm0 +# CHECK-NEXT: [1,0] .D===eER . . vpcmpeqb %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: [1,1] .D====eER . . vpcmpeqw %xmm1, %xmm1, %xmm2 +# CHECK-NEXT: [1,2] .D=====eER. . vpcmpeqd %xmm2, %xmm2, %xmm3 +# CHECK-NEXT: [1,3] .D======eER . vpcmpeqq %xmm3, %xmm3, %xmm0 +# CHECK-NEXT: [2,0] . D======eER . vpcmpeqb %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: [2,1] . D=======eER . vpcmpeqw %xmm1, %xmm1, %xmm2 +# CHECK-NEXT: [2,2] . D========eER. vpcmpeqd %xmm2, %xmm2, %xmm3 +# CHECK-NEXT: [2,3] . D=========eER vpcmpeqq %xmm3, %xmm3, %xmm0 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 4.0 0.3 0.0 vpcmpeqb %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: 1. 3 5.0 0.0 0.0 vpcmpeqw %xmm1, %xmm1, %xmm2 +# CHECK-NEXT: 2. 3 6.0 0.0 0.0 vpcmpeqd %xmm2, %xmm2, %xmm3 +# CHECK-NEXT: 3. 3 7.0 0.0 0.0 vpcmpeqq %xmm3, %xmm3, %xmm0 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/dependency-breaking-pcmpgt.s b/llvm/test/tools/llvm-mca/X86/BdVer2/dependency-breaking-pcmpgt.s new file mode 100644 index 00000000000..463de0b8123 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/dependency-breaking-pcmpgt.s @@ -0,0 +1,87 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -timeline -timeline-max-iterations=3 -iterations=1500 < %s | FileCheck %s + +# perf stat reports an IPC of 2.00 for this block of code. + +# All of the vector packed compares from this test are zero idioms. These zero +# idioms are all detected and removed by the register renamer. That means, no +# uOp is executed, and there is no RAW dependency for any of the packed +# compares. + +vpcmpgtb %xmm0, %xmm0, %xmm1 +vpcmpgtw %xmm1, %xmm1, %xmm2 +vpcmpgtd %xmm2, %xmm2, %xmm3 +vpcmpgtq %xmm3, %xmm3, %xmm0 + +# CHECK: Iterations: 1500 +# CHECK-NEXT: Instructions: 6000 +# CHECK-NEXT: Total Cycles: 1501 +# CHECK-NEXT: Total uOps: 6000 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 4.00 +# CHECK-NEXT: IPC: 4.00 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 0 0.25 vpcmpgtb %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: 1 0 0.25 vpcmpgtw %xmm1, %xmm1, %xmm2 +# CHECK-NEXT: 1 0 0.25 vpcmpgtd %xmm2, %xmm2, %xmm3 +# CHECK-NEXT: 1 0 0.25 vpcmpgtq %xmm3, %xmm3, %xmm0 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - - - - - - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - - - - - - vpcmpgtb %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: - - - - - - - - vpcmpgtw %xmm1, %xmm1, %xmm2 +# CHECK-NEXT: - - - - - - - - vpcmpgtd %xmm2, %xmm2, %xmm3 +# CHECK-NEXT: - - - - - - - - vpcmpgtq %xmm3, %xmm3, %xmm0 + +# CHECK: Timeline view: +# CHECK-NEXT: Index 0123 + +# CHECK: [0,0] DR . vpcmpgtb %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: [0,1] DR . vpcmpgtw %xmm1, %xmm1, %xmm2 +# CHECK-NEXT: [0,2] DR . vpcmpgtd %xmm2, %xmm2, %xmm3 +# CHECK-NEXT: [0,3] DR . vpcmpgtq %xmm3, %xmm3, %xmm0 +# CHECK-NEXT: [1,0] .DR. vpcmpgtb %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: [1,1] .DR. vpcmpgtw %xmm1, %xmm1, %xmm2 +# CHECK-NEXT: [1,2] .DR. vpcmpgtd %xmm2, %xmm2, %xmm3 +# CHECK-NEXT: [1,3] .DR. vpcmpgtq %xmm3, %xmm3, %xmm0 +# CHECK-NEXT: [2,0] . DR vpcmpgtb %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: [2,1] . DR vpcmpgtw %xmm1, %xmm1, %xmm2 +# CHECK-NEXT: [2,2] . DR vpcmpgtd %xmm2, %xmm2, %xmm3 +# CHECK-NEXT: [2,3] . DR vpcmpgtq %xmm3, %xmm3, %xmm0 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 0.0 0.0 0.0 vpcmpgtb %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: 1. 3 0.0 0.0 0.0 vpcmpgtw %xmm1, %xmm1, %xmm2 +# CHECK-NEXT: 2. 3 0.0 0.0 0.0 vpcmpgtd %xmm2, %xmm2, %xmm3 +# CHECK-NEXT: 3. 3 0.0 0.0 0.0 vpcmpgtq %xmm3, %xmm3, %xmm0 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/dependency-breaking-sbb-1.s b/llvm/test/tools/llvm-mca/X86/BdVer2/dependency-breaking-sbb-1.s new file mode 100644 index 00000000000..68d24f52128 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/dependency-breaking-sbb-1.s @@ -0,0 +1,73 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -timeline -timeline-max-iterations=3 -iterations=1500 < %s | FileCheck %s + +# perf stat reports an IPC of 1.00 for this code block. + +# Although both SBB are dependency breaking instructions, there is still an +# implicit dependency on EFLAGS which limits the ILP. So, the hardware backend +# can only execute one instruction per cycle. + +sbb %edx, %edx +sbb %eax, %eax + +# CHECK: Iterations: 1500 +# CHECK-NEXT: Instructions: 3000 +# CHECK-NEXT: Total Cycles: 6003 +# CHECK-NEXT: Total uOps: 6000 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.00 +# CHECK-NEXT: IPC: 0.50 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 2 2 0.67 sbbl %edx, %edx +# CHECK-NEXT: 2 2 0.67 sbbl %eax, %eax + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 1.33 1.33 - 1.33 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 0.67 0.67 - 0.67 - - sbbl %edx, %edx +# CHECK-NEXT: - - 0.67 0.67 - 0.67 - - sbbl %eax, %eax + +# CHECK: Timeline view: +# CHECK-NEXT: 01234 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeeER. . . sbbl %edx, %edx +# CHECK-NEXT: [0,1] D==eeER . . sbbl %eax, %eax +# CHECK-NEXT: [1,0] .D===eeER . . sbbl %edx, %edx +# CHECK-NEXT: [1,1] .D=====eeER . sbbl %eax, %eax +# CHECK-NEXT: [2,0] . D======eeER . sbbl %edx, %edx +# CHECK-NEXT: [2,1] . D========eeER sbbl %eax, %eax + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 4.0 0.3 0.0 sbbl %edx, %edx +# CHECK-NEXT: 1. 3 6.0 0.0 0.0 sbbl %eax, %eax diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/dependency-breaking-sbb-2.s b/llvm/test/tools/llvm-mca/X86/BdVer2/dependency-breaking-sbb-2.s new file mode 100644 index 00000000000..88dd23be8f3 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/dependency-breaking-sbb-2.s @@ -0,0 +1,80 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -timeline -timeline-max-iterations=3 -iterations=1500 < %s | FileCheck %s + +# perf stat reports a throughput of 1.51 IPC for this block of code. + +# The SBB does not depend on the value of register EAX. That means, it doesn't +# have to wait for the IMUL to write-back on EAX. However, it still depends on +# the ADD for EFLAGS. + +imul %edx, %eax +add %edx, %edx +sbb %eax, %eax + +# CHECK: Iterations: 1500 +# CHECK-NEXT: Instructions: 4500 +# CHECK-NEXT: Total Cycles: 7503 +# CHECK-NEXT: Total uOps: 6000 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.80 +# CHECK-NEXT: IPC: 0.60 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 imull %edx, %eax +# CHECK-NEXT: 1 1 0.33 addl %edx, %edx +# CHECK-NEXT: 2 2 0.67 sbbl %eax, %eax + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 1.33 1.33 - 1.33 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - - - - imull %edx, %eax +# CHECK-NEXT: - - 0.33 0.33 - 0.34 - - addl %edx, %edx +# CHECK-NEXT: - - 1.00 - - 1.00 - - sbbl %eax, %eax + +# CHECK: Timeline view: +# CHECK-NEXT: 01234567 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeeeER . . . imull %edx, %eax +# CHECK-NEXT: [0,1] DeE--R . . . addl %edx, %edx +# CHECK-NEXT: [0,2] D===eeER . . . sbbl %eax, %eax +# CHECK-NEXT: [1,0] .D====eeeER . . imull %edx, %eax +# CHECK-NEXT: [1,1] .DeE------R . . addl %edx, %edx +# CHECK-NEXT: [1,2] .D=======eeER . . sbbl %eax, %eax +# CHECK-NEXT: [2,0] . D========eeeER . imull %edx, %eax +# CHECK-NEXT: [2,1] . DeE----------R . addl %edx, %edx +# CHECK-NEXT: [2,2] . D===========eeER sbbl %eax, %eax + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 5.0 0.3 0.0 imull %edx, %eax +# CHECK-NEXT: 1. 3 1.0 0.3 6.0 addl %edx, %edx +# CHECK-NEXT: 2. 3 8.0 0.0 0.0 sbbl %eax, %eax diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/dependent-pmuld-paddd.s b/llvm/test/tools/llvm-mca/X86/BdVer2/dependent-pmuld-paddd.s new file mode 100644 index 00000000000..bf0f19ad31e --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/dependent-pmuld-paddd.s @@ -0,0 +1,95 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=500 -timeline < %s | FileCheck %s + +vpmuld %xmm0, %xmm0, %xmm1 +vpaddd %xmm1, %xmm1, %xmm0 +vpaddd %xmm0, %xmm0, %xmm3 + +# CHECK: Iterations: 500 +# CHECK-NEXT: Instructions: 1500 +# CHECK-NEXT: Total Cycles: 3004 +# CHECK-NEXT: Total uOps: 1500 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.50 +# CHECK-NEXT: IPC: 0.50 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 5 1.00 vpmuldq %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: 1 1 0.50 vpaddd %xmm1, %xmm1, %xmm0 +# CHECK-NEXT: 1 1 0.50 vpaddd %xmm0, %xmm0, %xmm3 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 1.00 - - - - - vpmuldq %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: - - - - - 1.00 - - vpaddd %xmm1, %xmm1, %xmm0 +# CHECK-NEXT: - - - 1.00 - - - - vpaddd %xmm0, %xmm0, %xmm3 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 0123456789 0123456789 +# CHECK-NEXT: Index 0123456789 0123456789 0123456789 0123 + +# CHECK: [0,0] DeeeeeER . . . . . . . . . . . . vpmuldq %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: [0,1] D=====eER . . . . . . . . . . . . vpaddd %xmm1, %xmm1, %xmm0 +# CHECK-NEXT: [0,2] D======eER. . . . . . . . . . . . vpaddd %xmm0, %xmm0, %xmm3 +# CHECK-NEXT: [1,0] D======eeeeeER . . . . . . . . . . . vpmuldq %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: [1,1] .D==========eER. . . . . . . . . . . vpaddd %xmm1, %xmm1, %xmm0 +# CHECK-NEXT: [1,2] .D===========eER . . . . . . . . . . vpaddd %xmm0, %xmm0, %xmm3 +# CHECK-NEXT: [2,0] .D===========eeeeeER. . . . . . . . . . vpmuldq %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: [2,1] .D================eER . . . . . . . . . vpaddd %xmm1, %xmm1, %xmm0 +# CHECK-NEXT: [2,2] . D================eER . . . . . . . . . vpaddd %xmm0, %xmm0, %xmm3 +# CHECK-NEXT: [3,0] . D================eeeeeER . . . . . . . . vpmuldq %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: [3,1] . D=====================eER . . . . . . . . vpaddd %xmm1, %xmm1, %xmm0 +# CHECK-NEXT: [3,2] . D======================eER . . . . . . . . vpaddd %xmm0, %xmm0, %xmm3 +# CHECK-NEXT: [4,0] . D=====================eeeeeER . . . . . . . vpmuldq %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: [4,1] . D==========================eER . . . . . . . vpaddd %xmm1, %xmm1, %xmm0 +# CHECK-NEXT: [4,2] . D===========================eER . . . . . . . vpaddd %xmm0, %xmm0, %xmm3 +# CHECK-NEXT: [5,0] . D===========================eeeeeER . . . . . . vpmuldq %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: [5,1] . D===============================eER . . . . . . vpaddd %xmm1, %xmm1, %xmm0 +# CHECK-NEXT: [5,2] . D================================eER. . . . . . vpaddd %xmm0, %xmm0, %xmm3 +# CHECK-NEXT: [6,0] . D================================eeeeeER . . . . . vpmuldq %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: [6,1] . D=====================================eER. . . . . vpaddd %xmm1, %xmm1, %xmm0 +# CHECK-NEXT: [6,2] . D=====================================eER . . . . vpaddd %xmm0, %xmm0, %xmm3 +# CHECK-NEXT: [7,0] . D=====================================eeeeeER. . . . vpmuldq %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: [7,1] . D==========================================eER . . . vpaddd %xmm1, %xmm1, %xmm0 +# CHECK-NEXT: [7,2] . D===========================================eER . . . vpaddd %xmm0, %xmm0, %xmm3 +# CHECK-NEXT: [8,0] . .D==========================================eeeeeER . . vpmuldq %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: [8,1] . .D===============================================eER . . vpaddd %xmm1, %xmm1, %xmm0 +# CHECK-NEXT: [8,2] . .D================================================eER . . vpaddd %xmm0, %xmm0, %xmm3 +# CHECK-NEXT: [9,0] . .D================================================eeeeeER . vpmuldq %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: [9,1] . . D====================================================eER. vpaddd %xmm1, %xmm1, %xmm0 +# CHECK-NEXT: [9,2] . . D=====================================================eER vpaddd %xmm0, %xmm0, %xmm3 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 10 25.0 0.1 0.0 vpmuldq %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: 1. 10 29.7 0.0 0.0 vpaddd %xmm1, %xmm1, %xmm0 +# CHECK-NEXT: 2. 10 30.5 0.0 0.0 vpaddd %xmm0, %xmm0, %xmm3 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/dot-product.s b/llvm/test/tools/llvm-mca/X86/BdVer2/dot-product.s new file mode 100644 index 00000000000..079872dc2a5 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/dot-product.s @@ -0,0 +1,74 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=300 -timeline -timeline-max-iterations=3 < %s | FileCheck %s + +vmulps %xmm0, %xmm1, %xmm2 +vhaddps %xmm2, %xmm2, %xmm3 +vhaddps %xmm3, %xmm3, %xmm4 + +# CHECK: Iterations: 300 +# CHECK-NEXT: Instructions: 900 +# CHECK-NEXT: Total Cycles: 1211 +# CHECK-NEXT: Total uOps: 2100 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.73 +# CHECK-NEXT: IPC: 0.74 +# CHECK-NEXT: Block RThroughput: 4.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 5 1.00 vmulps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 3 5 2.00 vhaddps %xmm2, %xmm2, %xmm3 +# CHECK-NEXT: 3 5 2.00 vhaddps %xmm3, %xmm3, %xmm4 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 1.00 2.00 - 4.00 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 1.00 - - - - - vmulps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - 2.00 - - vhaddps %xmm2, %xmm2, %xmm3 +# CHECK-NEXT: - - - 1.00 - 2.00 - - vhaddps %xmm3, %xmm3, %xmm4 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 012 + +# CHECK: [0,0] DeeeeeER . . . . vmulps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: [0,1] D=====eeeeeER . . . vhaddps %xmm2, %xmm2, %xmm3 +# CHECK-NEXT: [0,2] .D==========eeeeeER . . vhaddps %xmm3, %xmm3, %xmm4 +# CHECK-NEXT: [1,0] .DeeeeeE----------R . . vmulps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: [1,1] . D=====eeeeeE----R . . vhaddps %xmm2, %xmm2, %xmm3 +# CHECK-NEXT: [1,2] . D==========eeeeeER . vhaddps %xmm3, %xmm3, %xmm4 +# CHECK-NEXT: [2,0] . DeeeeeE----------R . vmulps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: [2,1] . D=====eeeeeE----R . vhaddps %xmm2, %xmm2, %xmm3 +# CHECK-NEXT: [2,2] . D==========eeeeeER vhaddps %xmm3, %xmm3, %xmm4 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 1.0 1.0 6.7 vmulps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 1. 3 6.0 0.7 2.7 vhaddps %xmm2, %xmm2, %xmm3 +# CHECK-NEXT: 2. 3 11.0 1.0 0.0 vhaddps %xmm3, %xmm3, %xmm4 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/hadd-read-after-ld-1.s b/llvm/test/tools/llvm-mca/X86/BdVer2/hadd-read-after-ld-1.s new file mode 100644 index 00000000000..e5d5140242d --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/hadd-read-after-ld-1.s @@ -0,0 +1,44 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -timeline -resource-pressure=false < %s | FileCheck %s + +vshufps $0, %xmm0, %xmm1, %xmm1 +vhaddps (%rdi), %xmm1, %xmm2 + +# CHECK: Iterations: 1 +# CHECK-NEXT: Instructions: 2 +# CHECK-NEXT: Total Cycles: 15 +# CHECK-NEXT: Total uOps: 5 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.33 +# CHECK-NEXT: IPC: 0.13 +# CHECK-NEXT: Block RThroughput: 3.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 1.00 vshufps $0, %xmm0, %xmm1, %xmm1 +# CHECK-NEXT: 4 11 2.00 * vhaddps (%rdi), %xmm1, %xmm2 + +# CHECK: Timeline view: +# CHECK-NEXT: 01234 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeER . . . vshufps $0, %xmm0, %xmm1, %xmm1 +# CHECK-NEXT: [0,1] .DeeeeeeeeeeeER vhaddps (%rdi), %xmm1, %xmm2 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 1 1.0 1.0 0.0 vshufps $0, %xmm0, %xmm1, %xmm1 +# CHECK-NEXT: 1. 1 1.0 1.0 0.0 vhaddps (%rdi), %xmm1, %xmm2 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/hadd-read-after-ld-2.s b/llvm/test/tools/llvm-mca/X86/BdVer2/hadd-read-after-ld-2.s new file mode 100644 index 00000000000..08c256596f2 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/hadd-read-after-ld-2.s @@ -0,0 +1,44 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -timeline -resource-pressure=false < %s | FileCheck %s + +vshufps $0, %xmm0, %xmm1, %xmm1 +vhaddps (%rdi), %ymm1, %ymm2 + +# CHECK: Iterations: 1 +# CHECK-NEXT: Instructions: 2 +# CHECK-NEXT: Total Cycles: 16 +# CHECK-NEXT: Total uOps: 5 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.31 +# CHECK-NEXT: IPC: 0.13 +# CHECK-NEXT: Block RThroughput: 3.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 1.00 vshufps $0, %xmm0, %xmm1, %xmm1 +# CHECK-NEXT: 4 12 2.00 * vhaddps (%rdi), %ymm1, %ymm2 + +# CHECK: Timeline view: +# CHECK-NEXT: 012345 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeER . . . vshufps $0, %xmm0, %xmm1, %xmm1 +# CHECK-NEXT: [0,1] .DeeeeeeeeeeeeER vhaddps (%rdi), %ymm1, %ymm2 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 1 1.0 1.0 0.0 vshufps $0, %xmm0, %xmm1, %xmm1 +# CHECK-NEXT: 1. 1 1.0 1.0 0.0 vhaddps (%rdi), %ymm1, %ymm2 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/instruction-info-view.s b/llvm/test/tools/llvm-mca/X86/BdVer2/instruction-info-view.s new file mode 100644 index 00000000000..6a92f84c35d --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/instruction-info-view.s @@ -0,0 +1,36 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -resource-pressure=false -instruction-info=true < %s | FileCheck %s --check-prefix=ENABLED +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -resource-pressure=false -instruction-info=false < %s | FileCheck %s -check-prefix=DISABLED +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -resource-pressure=false -instruction-info < %s | FileCheck %s -check-prefix=ENABLED +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -resource-pressure=false < %s | FileCheck %s -check-prefix=ENABLED + +vmulps %xmm0, %xmm1, %xmm2 +vhaddps %xmm2, %xmm2, %xmm3 +vhaddps %xmm3, %xmm3, %xmm4 + +# DISABLED-NOT: Instruction Info: + + +# ENABLED: Iterations: 100 +# ENABLED-NEXT: Instructions: 300 +# ENABLED-NEXT: Total Cycles: 414 +# ENABLED-NEXT: Total uOps: 700 + + +# ENABLED: Dispatch Width: 4 +# ENABLED-NEXT: uOps Per Cycle: 1.69 +# ENABLED-NEXT: IPC: 0.72 +# ENABLED-NEXT: Block RThroughput: 4.0 + +# ENABLED: Instruction Info: +# ENABLED-NEXT: [1]: #uOps +# ENABLED-NEXT: [2]: Latency +# ENABLED-NEXT: [3]: RThroughput +# ENABLED-NEXT: [4]: MayLoad +# ENABLED-NEXT: [5]: MayStore +# ENABLED-NEXT: [6]: HasSideEffects (U) + +# ENABLED: [1] [2] [3] [4] [5] [6] Instructions: +# ENABLED-NEXT: 1 5 1.00 vmulps %xmm0, %xmm1, %xmm2 +# ENABLED-NEXT: 3 5 2.00 vhaddps %xmm2, %xmm2, %xmm3 +# ENABLED-NEXT: 3 5 2.00 vhaddps %xmm3, %xmm3, %xmm4 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/load-store-alias.s b/llvm/test/tools/llvm-mca/X86/BdVer2/load-store-alias.s new file mode 100644 index 00000000000..fd123844d38 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/load-store-alias.s @@ -0,0 +1,93 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=100 -timeline -timeline-max-iterations=1 -noalias=false < %s | FileCheck %s + +vmovaps (%rsi), %xmm0 +vmovaps %xmm0, (%rdi) +vmovaps 16(%rsi), %xmm0 +vmovaps %xmm0, 16(%rdi) +vmovaps 32(%rsi), %xmm0 +vmovaps %xmm0, 32(%rdi) +vmovaps 48(%rsi), %xmm0 +vmovaps %xmm0, 48(%rdi) + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 800 +# CHECK-NEXT: Total Cycles: 2803 +# CHECK-NEXT: Total uOps: 800 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.29 +# CHECK-NEXT: IPC: 0.29 +# CHECK-NEXT: Block RThroughput: 4.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 6 0.50 * vmovaps (%rsi), %xmm0 +# CHECK-NEXT: 1 1 1.00 * vmovaps %xmm0, (%rdi) +# CHECK-NEXT: 1 6 0.50 * vmovaps 16(%rsi), %xmm0 +# CHECK-NEXT: 1 1 1.00 * vmovaps %xmm0, 16(%rdi) +# CHECK-NEXT: 1 6 0.50 * vmovaps 32(%rsi), %xmm0 +# CHECK-NEXT: 1 1 1.00 * vmovaps %xmm0, 32(%rdi) +# CHECK-NEXT: 1 6 0.50 * vmovaps 48(%rsi), %xmm0 +# CHECK-NEXT: 1 1 1.00 * vmovaps %xmm0, 48(%rdi) + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - - - 4.00 - - 8.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - - - - - 1.00 vmovaps (%rsi), %xmm0 +# CHECK-NEXT: - - - - 1.00 - - 1.00 vmovaps %xmm0, (%rdi) +# CHECK-NEXT: - - - - - - - 1.00 vmovaps 16(%rsi), %xmm0 +# CHECK-NEXT: - - - - 1.00 - - 1.00 vmovaps %xmm0, 16(%rdi) +# CHECK-NEXT: - - - - - - - 1.00 vmovaps 32(%rsi), %xmm0 +# CHECK-NEXT: - - - - 1.00 - - 1.00 vmovaps %xmm0, 32(%rdi) +# CHECK-NEXT: - - - - - - - 1.00 vmovaps 48(%rsi), %xmm0 +# CHECK-NEXT: - - - - 1.00 - - 1.00 vmovaps %xmm0, 48(%rdi) + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 0 +# CHECK-NEXT: Index 0123456789 0123456789 + +# CHECK: [0,0] DeeeeeeER . . . . . vmovaps (%rsi), %xmm0 +# CHECK-NEXT: [0,1] D======eER. . . . . vmovaps %xmm0, (%rdi) +# CHECK-NEXT: [0,2] D=======eeeeeeER . . . vmovaps 16(%rsi), %xmm0 +# CHECK-NEXT: [0,3] D=============eER . . . vmovaps %xmm0, 16(%rdi) +# CHECK-NEXT: [0,4] .D=============eeeeeeER . . vmovaps 32(%rsi), %xmm0 +# CHECK-NEXT: [0,5] .D===================eER . . vmovaps %xmm0, 32(%rdi) +# CHECK-NEXT: [0,6] .D====================eeeeeeER. vmovaps 48(%rsi), %xmm0 +# CHECK-NEXT: [0,7] .D==========================eER vmovaps %xmm0, 48(%rdi) + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 1 1.0 1.0 0.0 vmovaps (%rsi), %xmm0 +# CHECK-NEXT: 1. 1 7.0 0.0 0.0 vmovaps %xmm0, (%rdi) +# CHECK-NEXT: 2. 1 8.0 0.0 0.0 vmovaps 16(%rsi), %xmm0 +# CHECK-NEXT: 3. 1 14.0 0.0 0.0 vmovaps %xmm0, 16(%rdi) +# CHECK-NEXT: 4. 1 14.0 0.0 0.0 vmovaps 32(%rsi), %xmm0 +# CHECK-NEXT: 5. 1 20.0 0.0 0.0 vmovaps %xmm0, 32(%rdi) +# CHECK-NEXT: 6. 1 21.0 0.0 0.0 vmovaps 48(%rsi), %xmm0 +# CHECK-NEXT: 7. 1 27.0 0.0 0.0 vmovaps %xmm0, 48(%rdi) diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/memcpy-like-test.s b/llvm/test/tools/llvm-mca/X86/BdVer2/memcpy-like-test.s new file mode 100644 index 00000000000..107262f9497 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/memcpy-like-test.s @@ -0,0 +1,93 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=100 -timeline -timeline-max-iterations=1 < %s | FileCheck %s + +vmovaps (%rsi), %xmm0 +vmovaps %xmm0, (%rdi) +vmovaps 16(%rsi), %xmm0 +vmovaps %xmm0, 16(%rdi) +vmovaps 32(%rsi), %xmm0 +vmovaps %xmm0, 32(%rdi) +vmovaps 48(%rsi), %xmm0 +vmovaps %xmm0, 48(%rdi) + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 800 +# CHECK-NEXT: Total Cycles: 409 +# CHECK-NEXT: Total uOps: 800 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.96 +# CHECK-NEXT: IPC: 1.96 +# CHECK-NEXT: Block RThroughput: 4.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 6 0.50 * vmovaps (%rsi), %xmm0 +# CHECK-NEXT: 1 1 1.00 * vmovaps %xmm0, (%rdi) +# CHECK-NEXT: 1 6 0.50 * vmovaps 16(%rsi), %xmm0 +# CHECK-NEXT: 1 1 1.00 * vmovaps %xmm0, 16(%rdi) +# CHECK-NEXT: 1 6 0.50 * vmovaps 32(%rsi), %xmm0 +# CHECK-NEXT: 1 1 1.00 * vmovaps %xmm0, 32(%rdi) +# CHECK-NEXT: 1 6 0.50 * vmovaps 48(%rsi), %xmm0 +# CHECK-NEXT: 1 1 1.00 * vmovaps %xmm0, 48(%rdi) + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - - - 4.00 - 3.94 4.06 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - - - - 0.97 0.03 vmovaps (%rsi), %xmm0 +# CHECK-NEXT: - - - - 1.00 - - 1.00 vmovaps %xmm0, (%rdi) +# CHECK-NEXT: - - - - - - 0.03 0.97 vmovaps 16(%rsi), %xmm0 +# CHECK-NEXT: - - - - 1.00 - 0.97 0.03 vmovaps %xmm0, 16(%rdi) +# CHECK-NEXT: - - - - - - 1.00 - vmovaps 32(%rsi), %xmm0 +# CHECK-NEXT: - - - - 1.00 - - 1.00 vmovaps %xmm0, 32(%rdi) +# CHECK-NEXT: - - - - - - - 1.00 vmovaps 48(%rsi), %xmm0 +# CHECK-NEXT: - - - - 1.00 - 0.97 0.03 vmovaps %xmm0, 48(%rdi) + +# CHECK: Timeline view: +# CHECK-NEXT: 012 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeeeeeeER . . vmovaps (%rsi), %xmm0 +# CHECK-NEXT: [0,1] D======eER. . vmovaps %xmm0, (%rdi) +# CHECK-NEXT: [0,2] DeeeeeeE-R. . vmovaps 16(%rsi), %xmm0 +# CHECK-NEXT: [0,3] D=======eER . vmovaps %xmm0, 16(%rdi) +# CHECK-NEXT: [0,4] .DeeeeeeE-R . vmovaps 32(%rsi), %xmm0 +# CHECK-NEXT: [0,5] .D=======eER. vmovaps %xmm0, 32(%rdi) +# CHECK-NEXT: [0,6] .DeeeeeeE--R. vmovaps 48(%rsi), %xmm0 +# CHECK-NEXT: [0,7] .D========eER vmovaps %xmm0, 48(%rdi) + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 1 1.0 1.0 0.0 vmovaps (%rsi), %xmm0 +# CHECK-NEXT: 1. 1 7.0 0.0 0.0 vmovaps %xmm0, (%rdi) +# CHECK-NEXT: 2. 1 1.0 1.0 1.0 vmovaps 16(%rsi), %xmm0 +# CHECK-NEXT: 3. 1 8.0 0.0 0.0 vmovaps %xmm0, 16(%rdi) +# CHECK-NEXT: 4. 1 1.0 1.0 1.0 vmovaps 32(%rsi), %xmm0 +# CHECK-NEXT: 5. 1 8.0 0.0 0.0 vmovaps %xmm0, 32(%rdi) +# CHECK-NEXT: 6. 1 1.0 1.0 2.0 vmovaps 48(%rsi), %xmm0 +# CHECK-NEXT: 7. 1 9.0 0.0 0.0 vmovaps %xmm0, 48(%rdi) diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/one-idioms.s b/llvm/test/tools/llvm-mca/X86/BdVer2/one-idioms.s new file mode 100644 index 00000000000..599f0a01548 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/one-idioms.s @@ -0,0 +1,142 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -timeline -timeline-max-iterations=1 -register-file-stats < %s | FileCheck %s + +# These are dependency-breaking one-idioms. +# Much like zero-idioms, but they produce ones, and do consume resources. + +# perf stats reports a throughput of 2.00 IPC. + +pcmpeqb %mm2, %mm2 +pcmpeqd %mm2, %mm2 +pcmpeqw %mm2, %mm2 + +pcmpeqb %xmm2, %xmm2 +pcmpeqd %xmm2, %xmm2 +pcmpeqq %xmm2, %xmm2 +pcmpeqw %xmm2, %xmm2 + +vpcmpeqb %xmm3, %xmm3, %xmm3 +vpcmpeqd %xmm3, %xmm3, %xmm3 +vpcmpeqq %xmm3, %xmm3, %xmm3 +vpcmpeqw %xmm3, %xmm3, %xmm3 + +vpcmpeqb %xmm3, %xmm3, %xmm5 +vpcmpeqd %xmm3, %xmm3, %xmm5 +vpcmpeqq %xmm3, %xmm3, %xmm5 +vpcmpeqw %xmm3, %xmm3, %xmm5 + +# FIXME: their handling is broken in llvm-mca. + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 1500 +# CHECK-NEXT: Total Cycles: 903 +# CHECK-NEXT: Total uOps: 1500 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.66 +# CHECK-NEXT: IPC: 1.66 +# CHECK-NEXT: Block RThroughput: 6.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 pcmpeqb %mm2, %mm2 +# CHECK-NEXT: 1 3 1.00 pcmpeqd %mm2, %mm2 +# CHECK-NEXT: 1 3 1.00 pcmpeqw %mm2, %mm2 +# CHECK-NEXT: 1 1 0.50 pcmpeqb %xmm2, %xmm2 +# CHECK-NEXT: 1 1 0.50 pcmpeqd %xmm2, %xmm2 +# CHECK-NEXT: 1 1 0.50 pcmpeqq %xmm2, %xmm2 +# CHECK-NEXT: 1 1 0.50 pcmpeqw %xmm2, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpcmpeqb %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 1 1 0.50 vpcmpeqd %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 1 1 0.50 vpcmpeqq %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 1 1 0.50 vpcmpeqw %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 1 1 0.50 vpcmpeqb %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 1 1 0.50 vpcmpeqd %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 1 1 0.50 vpcmpeqq %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 1 1 0.50 vpcmpeqw %xmm3, %xmm3, %xmm5 + +# CHECK: Register File statistics: +# CHECK-NEXT: Total number of mappings created: 1500 +# CHECK-NEXT: Max number of mappings used: 168 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - - 7.65 - 7.35 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - - - - pcmpeqb %mm2, %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pcmpeqd %mm2, %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pcmpeqw %mm2, %mm2 +# CHECK-NEXT: - - - 0.75 - 0.25 - - pcmpeqb %xmm2, %xmm2 +# CHECK-NEXT: - - - 0.49 - 0.51 - - pcmpeqd %xmm2, %xmm2 +# CHECK-NEXT: - - - 0.64 - 0.36 - - pcmpeqq %xmm2, %xmm2 +# CHECK-NEXT: - - - 0.21 - 0.79 - - pcmpeqw %xmm2, %xmm2 +# CHECK-NEXT: - - - 0.44 - 0.56 - - vpcmpeqb %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: - - - 0.26 - 0.74 - - vpcmpeqd %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: - - - 0.25 - 0.75 - - vpcmpeqq %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: - - - - - 1.00 - - vpcmpeqw %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: - - - 0.25 - 0.75 - - vpcmpeqb %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: - - - 0.55 - 0.45 - - vpcmpeqd %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: - - - 0.44 - 0.56 - - vpcmpeqq %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: - - - 0.37 - 0.63 - - vpcmpeqw %xmm3, %xmm3, %xmm5 + +# CHECK: Timeline view: +# CHECK-NEXT: 01 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeeeER .. pcmpeqb %mm2, %mm2 +# CHECK-NEXT: [0,1] D===eeeER .. pcmpeqd %mm2, %mm2 +# CHECK-NEXT: [0,2] D======eeeER pcmpeqw %mm2, %mm2 +# CHECK-NEXT: [0,3] DeE--------R pcmpeqb %xmm2, %xmm2 +# CHECK-NEXT: [0,4] .DeE-------R pcmpeqd %xmm2, %xmm2 +# CHECK-NEXT: [0,5] .D=eE------R pcmpeqq %xmm2, %xmm2 +# CHECK-NEXT: [0,6] .D==eE-----R pcmpeqw %xmm2, %xmm2 +# CHECK-NEXT: [0,7] .DeE-------R vpcmpeqb %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,8] . DeE------R vpcmpeqd %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,9] . D==eE----R vpcmpeqq %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,10] . D===eE---R vpcmpeqw %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,11] . D====eE--R vpcmpeqb %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,12] . D====eE-R vpcmpeqd %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,13] . D====eE-R vpcmpeqq %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,14] . D=====eER vpcmpeqw %xmm3, %xmm3, %xmm5 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 1 1.0 1.0 0.0 pcmpeqb %mm2, %mm2 +# CHECK-NEXT: 1. 1 4.0 0.0 0.0 pcmpeqd %mm2, %mm2 +# CHECK-NEXT: 2. 1 7.0 0.0 0.0 pcmpeqw %mm2, %mm2 +# CHECK-NEXT: 3. 1 1.0 1.0 8.0 pcmpeqb %xmm2, %xmm2 +# CHECK-NEXT: 4. 1 1.0 0.0 7.0 pcmpeqd %xmm2, %xmm2 +# CHECK-NEXT: 5. 1 2.0 0.0 6.0 pcmpeqq %xmm2, %xmm2 +# CHECK-NEXT: 6. 1 3.0 0.0 5.0 pcmpeqw %xmm2, %xmm2 +# CHECK-NEXT: 7. 1 1.0 1.0 7.0 vpcmpeqb %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 8. 1 1.0 0.0 6.0 vpcmpeqd %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 9. 1 3.0 1.0 4.0 vpcmpeqq %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 10. 1 4.0 0.0 3.0 vpcmpeqw %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 11. 1 5.0 0.0 2.0 vpcmpeqb %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 12. 1 5.0 1.0 1.0 vpcmpeqd %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 13. 1 5.0 1.0 1.0 vpcmpeqq %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 14. 1 6.0 2.0 0.0 vpcmpeqw %xmm3, %xmm3, %xmm5 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/partial-reg-update-2.s b/llvm/test/tools/llvm-mca/X86/BdVer2/partial-reg-update-2.s new file mode 100644 index 00000000000..91ecc93c880 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/partial-reg-update-2.s @@ -0,0 +1,47 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -resource-pressure=false -timeline < %s | FileCheck %s + +imul %rax, %rbx +lzcnt %ax, %bx +add %ecx, %ebx + +# CHECK: Iterations: 1 +# CHECK-NEXT: Instructions: 3 +# CHECK-NEXT: Total Cycles: 8 +# CHECK-NEXT: Total uOps: 3 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.38 +# CHECK-NEXT: IPC: 0.38 +# CHECK-NEXT: Block RThroughput: 2.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 imulq %rax, %rbx +# CHECK-NEXT: 1 3 1.00 lzcntw %ax, %bx +# CHECK-NEXT: 1 1 0.33 addl %ecx, %ebx + +# CHECK: Timeline view: +# CHECK-NEXT: Index 01234567 + +# CHECK: [0,0] DeeeER . imulq %rax, %rbx +# CHECK-NEXT: [0,1] D=eeeER. lzcntw %ax, %bx +# CHECK-NEXT: [0,2] D====eER addl %ecx, %ebx + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 1 1.0 1.0 0.0 imulq %rax, %rbx +# CHECK-NEXT: 1. 1 2.0 2.0 0.0 lzcntw %ax, %bx +# CHECK-NEXT: 2. 1 5.0 0.0 0.0 addl %ecx, %ebx diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/partial-reg-update-3.s b/llvm/test/tools/llvm-mca/X86/BdVer2/partial-reg-update-3.s new file mode 100644 index 00000000000..d35a195bf35 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/partial-reg-update-3.s @@ -0,0 +1,78 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1500 -timeline -timeline-max-iterations=3 < %s | FileCheck %s + +# perf stat reports a throughput of 1.00 IPC for this code snippet. + +# The ILP is limited by the false dependency on %dx. So, the mov cannot execute +# in parallel with the add. + +add %cx, %dx +mov %ax, %dx +xor %bx, %dx + +# CHECK: Iterations: 1500 +# CHECK-NEXT: Instructions: 4500 +# CHECK-NEXT: Total Cycles: 1504 +# CHECK-NEXT: Total uOps: 4500 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 2.99 +# CHECK-NEXT: IPC: 2.99 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 0.33 addw %cx, %dx +# CHECK-NEXT: 1 1 0.33 movw %ax, %dx +# CHECK-NEXT: 1 1 0.33 xorw %bx, %dx + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 0.67 - - 0.33 - - addw %cx, %dx +# CHECK-NEXT: - - - 0.67 - 0.33 - - movw %ax, %dx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorw %bx, %dx + +# CHECK: Timeline view: +# CHECK-NEXT: Index 0123456 + +# CHECK: [0,0] DeER .. addw %cx, %dx +# CHECK-NEXT: [0,1] DeER .. movw %ax, %dx +# CHECK-NEXT: [0,2] D=eER.. xorw %bx, %dx +# CHECK-NEXT: [1,0] D==eER. addw %cx, %dx +# CHECK-NEXT: [1,1] .DeE-R. movw %ax, %dx +# CHECK-NEXT: [1,2] .D=eER. xorw %bx, %dx +# CHECK-NEXT: [2,0] .D==eER addw %cx, %dx +# CHECK-NEXT: [2,1] .DeE--R movw %ax, %dx +# CHECK-NEXT: [2,2] . DeE-R xorw %bx, %dx + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 2.3 0.3 0.0 addw %cx, %dx +# CHECK-NEXT: 1. 3 1.0 1.0 1.0 movw %ax, %dx +# CHECK-NEXT: 2. 3 1.7 0.0 0.3 xorw %bx, %dx diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/partial-reg-update-4.s b/llvm/test/tools/llvm-mca/X86/BdVer2/partial-reg-update-4.s new file mode 100644 index 00000000000..7cd4eb7b6ce --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/partial-reg-update-4.s @@ -0,0 +1,79 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1500 -timeline -timeline-max-iterations=3 < %s | FileCheck %s + +# perf stat reports a throughput of 0.60 IPC for this code snippet. + +# The lzcnt cannot execute in parallel with the imul because there is a false +# dependency on %bx. + +imul %ax, %bx +lzcnt %ax, %bx +add %cx, %bx + +# CHECK: Iterations: 1500 +# CHECK-NEXT: Instructions: 4500 +# CHECK-NEXT: Total Cycles: 3005 +# CHECK-NEXT: Total uOps: 4500 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.50 +# CHECK-NEXT: IPC: 1.50 +# CHECK-NEXT: Block RThroughput: 2.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 imulw %ax, %bx +# CHECK-NEXT: 1 3 1.00 lzcntw %ax, %bx +# CHECK-NEXT: 1 1 0.33 addw %cx, %bx + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 0.50 2.00 - 0.50 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - - - - imulw %ax, %bx +# CHECK-NEXT: - - - 1.00 - - - - lzcntw %ax, %bx +# CHECK-NEXT: - - 0.50 - - 0.50 - - addw %cx, %bx + +# CHECK: Timeline view: +# CHECK-NEXT: 01 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeeeER .. imulw %ax, %bx +# CHECK-NEXT: [0,1] D=eeeER .. lzcntw %ax, %bx +# CHECK-NEXT: [0,2] D====eER .. addw %cx, %bx +# CHECK-NEXT: [1,0] D=====eeeER. imulw %ax, %bx +# CHECK-NEXT: [1,1] .D=eeeE---R. lzcntw %ax, %bx +# CHECK-NEXT: [1,2] .D====eE--R. addw %cx, %bx +# CHECK-NEXT: [2,0] .D=====eeeER imulw %ax, %bx +# CHECK-NEXT: [2,1] .D==eeeE---R lzcntw %ax, %bx +# CHECK-NEXT: [2,2] . D====eE--R addw %cx, %bx + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 4.3 0.3 0.0 imulw %ax, %bx +# CHECK-NEXT: 1. 3 2.3 2.3 2.0 lzcntw %ax, %bx +# CHECK-NEXT: 2. 3 5.0 0.0 1.3 addw %cx, %bx diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/partial-reg-update-5.s b/llvm/test/tools/llvm-mca/X86/BdVer2/partial-reg-update-5.s new file mode 100644 index 00000000000..87098f08642 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/partial-reg-update-5.s @@ -0,0 +1,61 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1500 -timeline -timeline-max-iterations=3 < %s | FileCheck %s + +# perf stat reports a throughput of 1.00 IPC for this code snippet. + +lzcnt %ax, %bx ## partial register stall. + +# CHECK: Iterations: 1500 +# CHECK-NEXT: Instructions: 1500 +# CHECK-NEXT: Total Cycles: 1505 +# CHECK-NEXT: Total uOps: 1500 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.00 +# CHECK-NEXT: IPC: 1.00 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 lzcntw %ax, %bx + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - - 1.00 - - - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - - - - lzcntw %ax, %bx + +# CHECK: Timeline view: +# CHECK-NEXT: Index 01234567 + +# CHECK: [0,0] DeeeER . lzcntw %ax, %bx +# CHECK-NEXT: [1,0] D=eeeER. lzcntw %ax, %bx +# CHECK-NEXT: [2,0] D==eeeER lzcntw %ax, %bx + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 2.0 2.0 0.0 lzcntw %ax, %bx diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/partial-reg-update-6.s b/llvm/test/tools/llvm-mca/X86/BdVer2/partial-reg-update-6.s new file mode 100644 index 00000000000..465c26c7968 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/partial-reg-update-6.s @@ -0,0 +1,80 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1500 -timeline -timeline-max-iterations=3 < %s | FileCheck %s + +# perf stat reports a throughput of 0.60 IPC for this code snippet. +# Each lzcnt has a false dependency on %ecx; the first lzcnt has to wait on the +# imul. However, the folded load can start immediately. +# The last lzcnt has a false dependency on %cx. However, even in this case, the +# folded load can start immediately. + +imul %edx, %ecx +lzcnt (%rsp), %cx +lzcnt 2(%rsp), %cx + +# CHECK: Iterations: 1500 +# CHECK-NEXT: Instructions: 4500 +# CHECK-NEXT: Total Cycles: 4510 +# CHECK-NEXT: Total uOps: 7500 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.66 +# CHECK-NEXT: IPC: 1.00 +# CHECK-NEXT: Block RThroughput: 3.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 imull %edx, %ecx +# CHECK-NEXT: 2 8 1.00 * lzcntw (%rsp), %cx +# CHECK-NEXT: 2 8 1.00 * lzcntw 2(%rsp), %cx + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - - 3.00 - - - 2.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - - - - imull %edx, %ecx +# CHECK-NEXT: - - - 1.00 - - - 1.00 lzcntw (%rsp), %cx +# CHECK-NEXT: - - - 1.00 - - - 1.00 lzcntw 2(%rsp), %cx + +# CHECK: Timeline view: +# CHECK-NEXT: 012345678 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeeeER . . . imull %edx, %ecx +# CHECK-NEXT: [0,1] D=eeeeeeeeER . . lzcntw (%rsp), %cx +# CHECK-NEXT: [0,2] .D=eeeeeeeeER . . lzcntw 2(%rsp), %cx +# CHECK-NEXT: [1,0] .D=========eeeER . imull %edx, %ecx +# CHECK-NEXT: [1,1] . D=eeeeeeeeE--R . lzcntw (%rsp), %cx +# CHECK-NEXT: [1,2] . D==eeeeeeeeE-R . lzcntw 2(%rsp), %cx +# CHECK-NEXT: [2,0] . D==========eeeER imull %edx, %ecx +# CHECK-NEXT: [2,1] . D==eeeeeeeeE---R lzcntw (%rsp), %cx +# CHECK-NEXT: [2,2] . D==eeeeeeeeE--R lzcntw 2(%rsp), %cx + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 7.3 0.3 0.0 imull %edx, %ecx +# CHECK-NEXT: 1. 3 2.3 2.3 1.7 lzcntw (%rsp), %cx +# CHECK-NEXT: 2. 3 2.7 2.7 1.0 lzcntw 2(%rsp), %cx diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/partial-reg-update.s b/llvm/test/tools/llvm-mca/X86/BdVer2/partial-reg-update.s new file mode 100644 index 00000000000..995bb35d3ac --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/partial-reg-update.s @@ -0,0 +1,47 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -resource-pressure=false -timeline < %s | FileCheck %s + +imul %ax, %cx +add %al, %cl +add %ecx, %ebx + +# CHECK: Iterations: 1 +# CHECK-NEXT: Instructions: 3 +# CHECK-NEXT: Total Cycles: 8 +# CHECK-NEXT: Total uOps: 3 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.38 +# CHECK-NEXT: IPC: 0.38 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 imulw %ax, %cx +# CHECK-NEXT: 1 1 0.33 addb %al, %cl +# CHECK-NEXT: 1 1 0.33 addl %ecx, %ebx + +# CHECK: Timeline view: +# CHECK-NEXT: Index 01234567 + +# CHECK: [0,0] DeeeER . imulw %ax, %cx +# CHECK-NEXT: [0,1] D===eER. addb %al, %cl +# CHECK-NEXT: [0,2] D====eER addl %ecx, %ebx + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 1 1.0 1.0 0.0 imulw %ax, %cx +# CHECK-NEXT: 1. 1 4.0 0.0 0.0 addb %al, %cl +# CHECK-NEXT: 2. 1 5.0 0.0 0.0 addl %ecx, %ebx diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/pipes-fpu.s b/llvm/test/tools/llvm-mca/X86/BdVer2/pipes-fpu.s new file mode 100644 index 00000000000..9ca1d880673 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/pipes-fpu.s @@ -0,0 +1,99 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -timeline -timeline-max-iterations=2 < %s | FileCheck %s + +# VALU0/VALU1 +vpmulld %xmm0, %xmm1, %xmm2 +vpand %xmm0, %xmm1, %xmm2 + +# VIMUL/STC +vcvttps2dq %xmm0, %xmm2 +vpclmulqdq $0, %xmm0, %xmm1, %xmm2 + +# FPA/FPM +vaddps %xmm0, %xmm1, %xmm2 +vsqrtps %xmm0, %xmm2 + +# FPA/FPM YMM +vaddps %ymm0, %ymm1, %ymm2 +vsqrtps %ymm0, %ymm2 + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 800 +# CHECK-NEXT: Total Cycles: 4256 +# CHECK-NEXT: Total uOps: 1000 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.23 +# CHECK-NEXT: IPC: 0.19 +# CHECK-NEXT: Block RThroughput: 42.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 5 1.00 vpmulld %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.33 vpand %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vcvttps2dq %xmm0, %xmm2 +# CHECK-NEXT: 1 14 6.00 vpclmulqdq $0, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vaddps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 1 14 14.00 vsqrtps %xmm0, %xmm2 +# CHECK-NEXT: 1 3 1.00 vaddps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 3 29 28.00 vsqrtps %ymm0, %ymm2 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - 42.00 6.03 3.96 - 17.01 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 1.00 - - - - - vpmulld %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.05 0.06 - 0.89 - - vpand %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - vcvttps2dq %xmm0, %xmm2 +# CHECK-NEXT: - - 1.98 0.90 - 15.12 - - vpclmulqdq $0, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - vaddps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - 14.00 1.00 - - - - - vsqrtps %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - vaddps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - 28.00 2.00 - - 1.00 - - vsqrtps %ymm0, %ymm2 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 0123456 +# CHECK-NEXT: Index 0123456789 0123456789 + +# CHECK: [0,0] DeeeeeER . . . . . .. vpmulld %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: [0,1] DeE----R . . . . . .. vpand %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: [0,2] DeeeE--R . . . . . .. vcvttps2dq %xmm0, %xmm2 +# CHECK-NEXT: [0,3] D=eeeeeeeeeeeeeeER . . . .. vpclmulqdq $0, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: [0,4] .DeeeE-----------R . . . .. vaddps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: [0,5] .DeeeeeeeeeeeeeeER . . . .. vsqrtps %xmm0, %xmm2 +# CHECK-NEXT: [0,6] .D=eeeE----------R . . . .. vaddps %ymm0, %ymm1, %ymm2 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 1.0 1.0 79.0 vpmulld %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 1. 2 1.0 1.0 82.5 vpand %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2. 2 1.5 1.5 80.0 vcvttps2dq %xmm0, %xmm2 +# CHECK-NEXT: 3. 2 1.5 1.5 74.0 vpclmulqdq $0, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 4. 2 2.0 2.0 84.0 vaddps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 5. 2 9.5 9.5 65.0 vsqrtps %xmm0, %xmm2 +# CHECK-NEXT: 6. 2 2.5 2.5 83.0 vaddps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 7. 2 147.5 147.5 0.0 vsqrtps %ymm0, %ymm2 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/pr37790.s b/llvm/test/tools/llvm-mca/X86/BdVer2/pr37790.s new file mode 100644 index 00000000000..2878b280a9c --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/pr37790.s @@ -0,0 +1,43 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -lqueue=2 -iterations=2 -resource-pressure=false -timeline -timeline-max-cycles=104 < %s | FileCheck %s + +int3 +stmxcsr (%rsp) + +# CHECK: Iterations: 2 +# CHECK-NEXT: Instructions: 4 +# CHECK-NEXT: Total Cycles: 213 +# CHECK-NEXT: Total uOps: 10 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.05 +# CHECK-NEXT: IPC: 0.02 +# CHECK-NEXT: Block RThroughput: 1.3 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 100 0.33 * * U int3 +# CHECK-NEXT: 4 5 1.00 * * U stmxcsr (%rsp) + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 0123456789 0123456789 0123456789 0123456789 +# CHECK-NEXT: Index 0123456789 0123456789 0123456789 0123456789 0123456789 012 + +# CHECK: [0,0] DeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeER int3 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 3.0 0.5 0.0 int3 +# CHECK-NEXT: 1. 2 100.0 0.0 0.0 stmxcsr (%rsp) diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/rank.s b/llvm/test/tools/llvm-mca/X86/BdVer2/rank.s new file mode 100644 index 00000000000..24f8c43676e --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/rank.s @@ -0,0 +1,109 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -timeline -timeline-max-iterations=3 < %s | FileCheck %s + +add %eax, %ecx +add %eax, %edx +add %eax, %ebx +add %edx, %esi +add %ebx, %eax +add %edx, %esi +add %ebx, %eax +add %ebx, %eax + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 800 +# CHECK-NEXT: Total Cycles: 403 +# CHECK-NEXT: Total uOps: 800 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.99 +# CHECK-NEXT: IPC: 1.99 +# CHECK-NEXT: Block RThroughput: 2.7 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 0.33 addl %eax, %ecx +# CHECK-NEXT: 1 1 0.33 addl %eax, %edx +# CHECK-NEXT: 1 1 0.33 addl %eax, %ebx +# CHECK-NEXT: 1 1 0.33 addl %edx, %esi +# CHECK-NEXT: 1 1 0.33 addl %ebx, %eax +# CHECK-NEXT: 1 1 0.33 addl %edx, %esi +# CHECK-NEXT: 1 1 0.33 addl %ebx, %eax +# CHECK-NEXT: 1 1 0.33 addl %ebx, %eax + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 2.66 2.67 - 2.67 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 0.33 0.33 - 0.34 - - addl %eax, %ecx +# CHECK-NEXT: - - 0.33 0.34 - 0.33 - - addl %eax, %edx +# CHECK-NEXT: - - 0.34 0.33 - 0.33 - - addl %eax, %ebx +# CHECK-NEXT: - - 0.33 0.33 - 0.34 - - addl %edx, %esi +# CHECK-NEXT: - - 0.33 0.34 - 0.33 - - addl %ebx, %eax +# CHECK-NEXT: - - 0.34 0.33 - 0.33 - - addl %edx, %esi +# CHECK-NEXT: - - 0.33 0.33 - 0.34 - - addl %ebx, %eax +# CHECK-NEXT: - - 0.33 0.34 - 0.33 - - addl %ebx, %eax + +# CHECK: Timeline view: +# CHECK-NEXT: 01234 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeER . . . addl %eax, %ecx +# CHECK-NEXT: [0,1] DeER . . . addl %eax, %edx +# CHECK-NEXT: [0,2] DeER . . . addl %eax, %ebx +# CHECK-NEXT: [0,3] D=eER. . . addl %edx, %esi +# CHECK-NEXT: [0,4] .DeER. . . addl %ebx, %eax +# CHECK-NEXT: [0,5] .D=eER . . addl %edx, %esi +# CHECK-NEXT: [0,6] .D=eER . . addl %ebx, %eax +# CHECK-NEXT: [0,7] .D==eER . . addl %ebx, %eax +# CHECK-NEXT: [1,0] . D==eER . . addl %eax, %ecx +# CHECK-NEXT: [1,1] . D==eER . . addl %eax, %edx +# CHECK-NEXT: [1,2] . D==eER . . addl %eax, %ebx +# CHECK-NEXT: [1,3] . D===eER . . addl %edx, %esi +# CHECK-NEXT: [1,4] . D==eER . . addl %ebx, %eax +# CHECK-NEXT: [1,5] . D===eER. . addl %edx, %esi +# CHECK-NEXT: [1,6] . D===eER. . addl %ebx, %eax +# CHECK-NEXT: [1,7] . D====eER . addl %ebx, %eax +# CHECK-NEXT: [2,0] . D====eER . addl %eax, %ecx +# CHECK-NEXT: [2,1] . D====eER . addl %eax, %edx +# CHECK-NEXT: [2,2] . D====eER . addl %eax, %ebx +# CHECK-NEXT: [2,3] . D=====eER . addl %edx, %esi +# CHECK-NEXT: [2,4] . D====eER . addl %ebx, %eax +# CHECK-NEXT: [2,5] . D=====eER. addl %edx, %esi +# CHECK-NEXT: [2,6] . D=====eER. addl %ebx, %eax +# CHECK-NEXT: [2,7] . D======eER addl %ebx, %eax + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 3.0 0.3 0.0 addl %eax, %ecx +# CHECK-NEXT: 1. 3 3.0 0.3 0.0 addl %eax, %edx +# CHECK-NEXT: 2. 3 3.0 0.3 0.0 addl %eax, %ebx +# CHECK-NEXT: 3. 3 4.0 0.0 0.0 addl %edx, %esi +# CHECK-NEXT: 4. 3 3.0 0.0 0.0 addl %ebx, %eax +# CHECK-NEXT: 5. 3 4.0 0.0 0.0 addl %edx, %esi +# CHECK-NEXT: 6. 3 4.0 0.0 0.0 addl %ebx, %eax +# CHECK-NEXT: 7. 3 5.0 0.0 0.0 addl %ebx, %eax diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/rcu-statistics.s b/llvm/test/tools/llvm-mca/X86/BdVer2/rcu-statistics.s new file mode 100644 index 00000000000..afa5abd1cd2 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/rcu-statistics.s @@ -0,0 +1,61 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -resource-pressure=false -retire-stats -iterations=1 < %s | FileCheck %s + + vsqrtps %xmm0, %xmm2 + vaddps %xmm0, %xmm1, %xmm2 + vaddps %xmm0, %xmm1, %xmm2 + vaddps %xmm0, %xmm1, %xmm2 + vaddps %xmm0, %xmm1, %xmm2 + vaddps %xmm0, %xmm1, %xmm2 + vaddps %xmm0, %xmm1, %xmm2 + vaddps %xmm0, %xmm1, %xmm2 + vaddps %xmm0, %xmm1, %xmm2 + vaddps %xmm0, %xmm1, %xmm2 + vaddps %xmm0, %xmm1, %xmm2 + vaddps %xmm0, %xmm1, %xmm2 + vaddps %xmm0, %xmm1, %xmm2 + vaddps %xmm0, %xmm1, %xmm2 + vaddps %xmm0, %xmm1, %xmm2 + vaddps %xmm0, %xmm1, %xmm2 + +# CHECK: Iterations: 1 +# CHECK-NEXT: Instructions: 16 +# CHECK-NEXT: Total Cycles: 20 +# CHECK-NEXT: Total uOps: 16 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.80 +# CHECK-NEXT: IPC: 0.80 +# CHECK-NEXT: Block RThroughput: 15.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 14 14.00 vsqrtps %xmm0, %xmm2 +# CHECK-NEXT: 1 3 1.00 vaddps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vaddps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vaddps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vaddps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vaddps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vaddps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vaddps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vaddps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vaddps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vaddps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vaddps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vaddps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vaddps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vaddps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vaddps %xmm0, %xmm1, %xmm2 + +# CHECK: Retire Control Unit - number of cycles where we saw N instructions retired: +# CHECK-NEXT: [# retired], [# cycles] +# CHECK-NEXT: 0, 16 (80.0%) +# CHECK-NEXT: 1, 3 (15.0%) +# CHECK-NEXT: 13, 1 (5.0%) diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/read-advance-1.s b/llvm/test/tools/llvm-mca/X86/BdVer2/read-advance-1.s new file mode 100644 index 00000000000..1c719a84a1b --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/read-advance-1.s @@ -0,0 +1,48 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -timeline -resource-pressure=false < %s | FileCheck %s + +# The vmul can start executing 3cy in advance. That is beause the first use +# operand (i.e. %xmm1) is a ReadAfterLd. That means, the memory operand is +# evaluated before %xmm1. + +vaddps %xmm0, %xmm0, %xmm1 +vmulps (%rdi), %xmm1, %xmm2 + +# CHECK: Iterations: 1 +# CHECK-NEXT: Instructions: 2 +# CHECK-NEXT: Total Cycles: 14 +# CHECK-NEXT: Total uOps: 3 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.21 +# CHECK-NEXT: IPC: 0.14 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 vaddps %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: 2 11 1.00 * vmulps (%rdi), %xmm1, %xmm2 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeeeER . . vaddps %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: [0,1] DeeeeeeeeeeeER vmulps (%rdi), %xmm1, %xmm2 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 1 1.0 1.0 0.0 vaddps %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: 1. 1 1.0 0.0 0.0 vmulps (%rdi), %xmm1, %xmm2 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/read-advance-2.s b/llvm/test/tools/llvm-mca/X86/BdVer2/read-advance-2.s new file mode 100644 index 00000000000..7814b000ee4 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/read-advance-2.s @@ -0,0 +1,47 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -resource-pressure=0 -timeline < %s | FileCheck %s + + imull %esi + imull (%rdi) + +# The second integer multiply can start at cycle 2 because the implicit reads +# can start after the load operand is evaluated. + +# CHECK: Iterations: 1 +# CHECK-NEXT: Instructions: 2 +# CHECK-NEXT: Total Cycles: 13 +# CHECK-NEXT: Total uOps: 7 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.54 +# CHECK-NEXT: IPC: 0.15 +# CHECK-NEXT: Block RThroughput: 2.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 3 4 1.00 imull %esi +# CHECK-NEXT: 4 9 1.00 * imull (%rdi) + +# CHECK: Timeline view: +# CHECK-NEXT: 012 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeeeeER . . imull %esi +# CHECK-NEXT: [0,1] .DeeeeeeeeeER imull (%rdi) + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 1 1.0 1.0 0.0 imull %esi +# CHECK-NEXT: 1. 1 1.0 1.0 0.0 imull (%rdi) diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/read-advance-3.s b/llvm/test/tools/llvm-mca/X86/BdVer2/read-advance-3.s new file mode 100644 index 00000000000..638f36c1711 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/read-advance-3.s @@ -0,0 +1,47 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -resource-pressure=0 -timeline -dispatch=3 < %s | FileCheck %s + + add %rdi, %rsi + add (%rsp), %rsi + add %rdx, %r8 + +# CHECK: Iterations: 1 +# CHECK-NEXT: Instructions: 3 +# CHECK-NEXT: Total Cycles: 9 +# CHECK-NEXT: Total uOps: 4 + +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.44 +# CHECK-NEXT: IPC: 0.33 +# CHECK-NEXT: Block RThroughput: 1.3 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 0.33 addq %rdi, %rsi +# CHECK-NEXT: 2 6 0.50 * addq (%rsp), %rsi +# CHECK-NEXT: 1 1 0.33 addq %rdx, %r8 + +# CHECK: Timeline view: +# CHECK-NEXT: Index 012345678 + +# CHECK: [0,0] DeER . . addq %rdi, %rsi +# CHECK-NEXT: [0,1] DeeeeeeER addq (%rsp), %rsi +# CHECK-NEXT: [0,2] .DeE----R addq %rdx, %r8 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 1 1.0 1.0 0.0 addq %rdi, %rsi +# CHECK-NEXT: 1. 1 1.0 0.0 0.0 addq (%rsp), %rsi +# CHECK-NEXT: 2. 1 1.0 1.0 4.0 addq %rdx, %r8 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/reg-move-elimination-1.s b/llvm/test/tools/llvm-mca/X86/BdVer2/reg-move-elimination-1.s new file mode 100644 index 00000000000..990cdc4fe31 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/reg-move-elimination-1.s @@ -0,0 +1,80 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=3 -timeline -register-file-stats < %s | FileCheck %s + +# The register move from XMM0 to XMM1 can be eliminated at register renaming +# stage. So, it should not consume pipeline resources. + +vxorps %xmm0, %xmm0, %xmm0 +vmovaps %xmm0, %xmm1 +vaddps %xmm1, %xmm1, %xmm2 + +# CHECK: Iterations: 3 +# CHECK-NEXT: Instructions: 9 +# CHECK-NEXT: Total Cycles: 9 +# CHECK-NEXT: Total uOps: 9 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.00 +# CHECK-NEXT: IPC: 1.00 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 0 0.25 vxorps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: 1 1 1.00 vmovaps %xmm0, %xmm1 +# CHECK-NEXT: 1 3 1.00 vaddps %xmm1, %xmm1, %xmm2 + +# CHECK: Register File statistics: +# CHECK-NEXT: Total number of mappings created: 9 +# CHECK-NEXT: Max number of mappings used: 8 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - - 1.00 - 1.00 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - - - - - - vxorps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: - - - - - 1.00 - - vmovaps %xmm0, %xmm1 +# CHECK-NEXT: - - - 1.00 - - - - vaddps %xmm1, %xmm1, %xmm2 + +# CHECK: Timeline view: +# CHECK-NEXT: Index 012345678 + +# CHECK: [0,0] DR . . vxorps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: [0,1] DeER . . vmovaps %xmm0, %xmm1 +# CHECK-NEXT: [0,2] D=eeeER . vaddps %xmm1, %xmm1, %xmm2 +# CHECK-NEXT: [1,0] D-----R . vxorps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: [1,1] .DeE--R . vmovaps %xmm0, %xmm1 +# CHECK-NEXT: [1,2] .D=eeeER. vaddps %xmm1, %xmm1, %xmm2 +# CHECK-NEXT: [2,0] .D-----R. vxorps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: [2,1] .D=eE--R. vmovaps %xmm0, %xmm1 +# CHECK-NEXT: [2,2] . D=eeeER vaddps %xmm1, %xmm1, %xmm2 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 0.0 0.0 3.3 vxorps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: 1. 3 1.3 1.3 1.3 vmovaps %xmm0, %xmm1 +# CHECK-NEXT: 2. 3 2.0 0.0 0.0 vaddps %xmm1, %xmm1, %xmm2 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/reg-move-elimination-2.s b/llvm/test/tools/llvm-mca/X86/BdVer2/reg-move-elimination-2.s new file mode 100644 index 00000000000..6f22cdc0b7e --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/reg-move-elimination-2.s @@ -0,0 +1,121 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=3 -timeline -register-file-stats < %s | FileCheck %s + +pxor %mm0, %mm0 +movq %mm0, %mm1 + +xorps %xmm0, %xmm0 +movaps %xmm0, %xmm1 +movups %xmm1, %xmm2 +movapd %xmm2, %xmm3 +movupd %xmm3, %xmm4 +movdqa %xmm4, %xmm5 +movdqu %xmm5, %xmm0 + +# CHECK: Iterations: 3 +# CHECK-NEXT: Instructions: 27 +# CHECK-NEXT: Total Cycles: 22 +# CHECK-NEXT: Total uOps: 27 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.23 +# CHECK-NEXT: IPC: 1.23 +# CHECK-NEXT: Block RThroughput: 4.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 0.33 pxor %mm0, %mm0 +# CHECK-NEXT: 1 1 0.50 movq %mm0, %mm1 +# CHECK-NEXT: 1 0 0.25 xorps %xmm0, %xmm0 +# CHECK-NEXT: 1 1 1.00 movaps %xmm0, %xmm1 +# CHECK-NEXT: 1 1 1.00 movups %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 movapd %xmm2, %xmm3 +# CHECK-NEXT: 1 1 1.00 movupd %xmm3, %xmm4 +# CHECK-NEXT: 1 1 0.33 movdqa %xmm4, %xmm5 +# CHECK-NEXT: 1 1 0.33 movdqu %xmm5, %xmm0 + +# CHECK: Register File statistics: +# CHECK-NEXT: Total number of mappings created: 27 +# CHECK-NEXT: Max number of mappings used: 21 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 1.67 1.67 - 4.67 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 0.67 - 0.33 - - pxor %mm0, %mm0 +# CHECK-NEXT: - - 1.00 - - - - - movq %mm0, %mm1 +# CHECK-NEXT: - - - - - - - - xorps %xmm0, %xmm0 +# CHECK-NEXT: - - - - - 1.00 - - movaps %xmm0, %xmm1 +# CHECK-NEXT: - - - - - 1.00 - - movups %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - movapd %xmm2, %xmm3 +# CHECK-NEXT: - - - - - 1.00 - - movupd %xmm3, %xmm4 +# CHECK-NEXT: - - - 1.00 - - - - movdqa %xmm4, %xmm5 +# CHECK-NEXT: - - 0.67 - - 0.33 - - movdqu %xmm5, %xmm0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 01 + +# CHECK: [0,0] DeER . . . .. pxor %mm0, %mm0 +# CHECK-NEXT: [0,1] D=eER. . . .. movq %mm0, %mm1 +# CHECK-NEXT: [0,2] D---R. . . .. xorps %xmm0, %xmm0 +# CHECK-NEXT: [0,3] D=eER. . . .. movaps %xmm0, %xmm1 +# CHECK-NEXT: [0,4] .D=eER . . .. movups %xmm1, %xmm2 +# CHECK-NEXT: [0,5] .D==eER . . .. movapd %xmm2, %xmm3 +# CHECK-NEXT: [0,6] .D===eER . . .. movupd %xmm3, %xmm4 +# CHECK-NEXT: [0,7] .D====eER . . .. movdqa %xmm4, %xmm5 +# CHECK-NEXT: [0,8] . D====eER. . .. movdqu %xmm5, %xmm0 +# CHECK-NEXT: [1,0] . DeE----R. . .. pxor %mm0, %mm0 +# CHECK-NEXT: [1,1] . D=eE---R. . .. movq %mm0, %mm1 +# CHECK-NEXT: [1,2] . D=====ER. . .. xorps %xmm0, %xmm0 +# CHECK-NEXT: [1,3] . D====eER . .. movaps %xmm0, %xmm1 +# CHECK-NEXT: [1,4] . D=====eER . .. movups %xmm1, %xmm2 +# CHECK-NEXT: [1,5] . D======eER . .. movapd %xmm2, %xmm3 +# CHECK-NEXT: [1,6] . D=======eER . .. movupd %xmm3, %xmm4 +# CHECK-NEXT: [1,7] . D=======eER. .. movdqa %xmm4, %xmm5 +# CHECK-NEXT: [1,8] . D========eER .. movdqu %xmm5, %xmm0 +# CHECK-NEXT: [2,0] . DeE--------R .. pxor %mm0, %mm0 +# CHECK-NEXT: [2,1] . D=eE-------R .. movq %mm0, %mm1 +# CHECK-NEXT: [2,2] . D========ER .. xorps %xmm0, %xmm0 +# CHECK-NEXT: [2,3] . D========eER .. movaps %xmm0, %xmm1 +# CHECK-NEXT: [2,4] . D=========eER .. movups %xmm1, %xmm2 +# CHECK-NEXT: [2,5] . D==========eER .. movapd %xmm2, %xmm3 +# CHECK-NEXT: [2,6] . .D==========eER.. movupd %xmm3, %xmm4 +# CHECK-NEXT: [2,7] . .D===========eER. movdqa %xmm4, %xmm5 +# CHECK-NEXT: [2,8] . .D============eER movdqu %xmm5, %xmm0 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 1.0 1.0 4.0 pxor %mm0, %mm0 +# CHECK-NEXT: 1. 3 2.0 0.0 3.3 movq %mm0, %mm1 +# CHECK-NEXT: 2. 3 5.0 0.0 1.0 xorps %xmm0, %xmm0 +# CHECK-NEXT: 3. 3 5.3 0.7 0.0 movaps %xmm0, %xmm1 +# CHECK-NEXT: 4. 3 6.0 0.0 0.0 movups %xmm1, %xmm2 +# CHECK-NEXT: 5. 3 7.0 0.0 0.0 movapd %xmm2, %xmm3 +# CHECK-NEXT: 6. 3 7.7 0.0 0.0 movupd %xmm3, %xmm4 +# CHECK-NEXT: 7. 3 8.3 0.0 0.0 movdqa %xmm4, %xmm5 +# CHECK-NEXT: 8. 3 9.0 0.0 0.0 movdqu %xmm5, %xmm0 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/reg-move-elimination-3.s b/llvm/test/tools/llvm-mca/X86/BdVer2/reg-move-elimination-3.s new file mode 100644 index 00000000000..202afac21ec --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/reg-move-elimination-3.s @@ -0,0 +1,106 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=3 -timeline -register-file-stats < %s | FileCheck %s + +vxorps %xmm0, %xmm0, %xmm0 +vmovaps %xmm0, %xmm1 +vmovups %xmm1, %xmm2 +vmovapd %xmm2, %xmm3 +vmovupd %xmm3, %xmm4 +vmovdqa %xmm4, %xmm5 +vmovdqu %xmm5, %xmm0 + +# CHECK: Iterations: 3 +# CHECK-NEXT: Instructions: 21 +# CHECK-NEXT: Total Cycles: 21 +# CHECK-NEXT: Total uOps: 21 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.00 +# CHECK-NEXT: IPC: 1.00 +# CHECK-NEXT: Block RThroughput: 4.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 0 0.25 vxorps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: 1 1 1.00 vmovaps %xmm0, %xmm1 +# CHECK-NEXT: 1 1 1.00 vmovups %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 vmovapd %xmm2, %xmm3 +# CHECK-NEXT: 1 1 1.00 vmovupd %xmm3, %xmm4 +# CHECK-NEXT: 1 1 0.33 vmovdqa %xmm4, %xmm5 +# CHECK-NEXT: 1 1 0.33 vmovdqu %xmm5, %xmm0 + +# CHECK: Register File statistics: +# CHECK-NEXT: Total number of mappings created: 21 +# CHECK-NEXT: Max number of mappings used: 17 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 1.00 1.00 - 4.00 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - - - - - - vxorps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: - - - - - 1.00 - - vmovaps %xmm0, %xmm1 +# CHECK-NEXT: - - - - - 1.00 - - vmovups %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vmovapd %xmm2, %xmm3 +# CHECK-NEXT: - - - - - 1.00 - - vmovupd %xmm3, %xmm4 +# CHECK-NEXT: - - - 1.00 - - - - vmovdqa %xmm4, %xmm5 +# CHECK-NEXT: - - 1.00 - - - - - vmovdqu %xmm5, %xmm0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 0 + +# CHECK: [0,0] DR . . . . vxorps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: [0,1] DeER . . . . vmovaps %xmm0, %xmm1 +# CHECK-NEXT: [0,2] D=eER. . . . vmovups %xmm1, %xmm2 +# CHECK-NEXT: [0,3] D==eER . . . vmovapd %xmm2, %xmm3 +# CHECK-NEXT: [0,4] .D==eER . . . vmovupd %xmm3, %xmm4 +# CHECK-NEXT: [0,5] .D===eER . . . vmovdqa %xmm4, %xmm5 +# CHECK-NEXT: [0,6] .D====eER . . . vmovdqu %xmm5, %xmm0 +# CHECK-NEXT: [1,0] .D=====ER . . . vxorps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: [1,1] . D====eER. . . vmovaps %xmm0, %xmm1 +# CHECK-NEXT: [1,2] . D=====eER . . vmovups %xmm1, %xmm2 +# CHECK-NEXT: [1,3] . D======eER . . vmovapd %xmm2, %xmm3 +# CHECK-NEXT: [1,4] . D=======eER . . vmovupd %xmm3, %xmm4 +# CHECK-NEXT: [1,5] . D=======eER . . vmovdqa %xmm4, %xmm5 +# CHECK-NEXT: [1,6] . D========eER. . vmovdqu %xmm5, %xmm0 +# CHECK-NEXT: [2,0] . D=========ER. . vxorps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: [2,1] . D=========eER . vmovaps %xmm0, %xmm1 +# CHECK-NEXT: [2,2] . D=========eER . vmovups %xmm1, %xmm2 +# CHECK-NEXT: [2,3] . D==========eER . vmovapd %xmm2, %xmm3 +# CHECK-NEXT: [2,4] . D===========eER . vmovupd %xmm3, %xmm4 +# CHECK-NEXT: [2,5] . D============eER. vmovdqa %xmm4, %xmm5 +# CHECK-NEXT: [2,6] . D============eER vmovdqu %xmm5, %xmm0 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 5.3 0.0 0.0 vxorps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: 1. 3 5.3 0.3 0.0 vmovaps %xmm0, %xmm1 +# CHECK-NEXT: 2. 3 6.0 0.0 0.0 vmovups %xmm1, %xmm2 +# CHECK-NEXT: 3. 3 7.0 0.0 0.0 vmovapd %xmm2, %xmm3 +# CHECK-NEXT: 4. 3 7.7 0.0 0.0 vmovupd %xmm3, %xmm4 +# CHECK-NEXT: 5. 3 8.3 0.0 0.0 vmovdqa %xmm4, %xmm5 +# CHECK-NEXT: 6. 3 9.0 0.0 0.0 vmovdqu %xmm5, %xmm0 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/reg-move-elimination-4.s b/llvm/test/tools/llvm-mca/X86/BdVer2/reg-move-elimination-4.s new file mode 100644 index 00000000000..339ec06bcc8 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/reg-move-elimination-4.s @@ -0,0 +1,92 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=3 -timeline -register-file-stats < %s | FileCheck %s + +xor %eax, %eax +mov %eax, %ebx +mov %ebx, %ecx +mov %ecx, %edx +mov %edx, %eax + +# CHECK: Iterations: 3 +# CHECK-NEXT: Instructions: 15 +# CHECK-NEXT: Total Cycles: 15 +# CHECK-NEXT: Total uOps: 15 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.00 +# CHECK-NEXT: IPC: 1.00 +# CHECK-NEXT: Block RThroughput: 1.3 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 0 0.25 xorl %eax, %eax +# CHECK-NEXT: 1 1 0.33 movl %eax, %ebx +# CHECK-NEXT: 1 1 0.33 movl %ebx, %ecx +# CHECK-NEXT: 1 1 0.33 movl %ecx, %edx +# CHECK-NEXT: 1 1 0.33 movl %edx, %eax + +# CHECK: Register File statistics: +# CHECK-NEXT: Total number of mappings created: 18 +# CHECK-NEXT: Max number of mappings used: 15 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 1.33 1.33 - 1.33 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - - - - - - xorl %eax, %eax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movl %eax, %ebx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movl %ebx, %ecx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movl %ecx, %edx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movl %edx, %eax + +# CHECK: Timeline view: +# CHECK-NEXT: 01234 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DR . . . xorl %eax, %eax +# CHECK-NEXT: [0,1] DeER . . . movl %eax, %ebx +# CHECK-NEXT: [0,2] D=eER. . . movl %ebx, %ecx +# CHECK-NEXT: [0,3] D==eER . . movl %ecx, %edx +# CHECK-NEXT: [0,4] .D==eER . . movl %edx, %eax +# CHECK-NEXT: [1,0] .D===ER . . xorl %eax, %eax +# CHECK-NEXT: [1,1] .D===eER . . movl %eax, %ebx +# CHECK-NEXT: [1,2] .D====eER . . movl %ebx, %ecx +# CHECK-NEXT: [1,3] . D====eER. . movl %ecx, %edx +# CHECK-NEXT: [1,4] . D=====eER . movl %edx, %eax +# CHECK-NEXT: [2,0] . D======ER . xorl %eax, %eax +# CHECK-NEXT: [2,1] . D======eER . movl %eax, %ebx +# CHECK-NEXT: [2,2] . D======eER . movl %ebx, %ecx +# CHECK-NEXT: [2,3] . D=======eER. movl %ecx, %edx +# CHECK-NEXT: [2,4] . D========eER movl %edx, %eax + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 3.7 0.0 0.0 xorl %eax, %eax +# CHECK-NEXT: 1. 3 4.0 0.3 0.0 movl %eax, %ebx +# CHECK-NEXT: 2. 3 4.7 0.0 0.0 movl %ebx, %ecx +# CHECK-NEXT: 3. 3 5.3 0.0 0.0 movl %ecx, %edx +# CHECK-NEXT: 4. 3 6.0 0.0 0.0 movl %edx, %eax diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/reg-move-elimination-5.s b/llvm/test/tools/llvm-mca/X86/BdVer2/reg-move-elimination-5.s new file mode 100644 index 00000000000..66ce02cb0fc --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/reg-move-elimination-5.s @@ -0,0 +1,92 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=3 -timeline -register-file-stats < %s | FileCheck %s + +xor %rax, %rax +mov %rax, %rbx +mov %rbx, %rcx +mov %rcx, %rdx +mov %rdx, %rax + +# CHECK: Iterations: 3 +# CHECK-NEXT: Instructions: 15 +# CHECK-NEXT: Total Cycles: 15 +# CHECK-NEXT: Total uOps: 15 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.00 +# CHECK-NEXT: IPC: 1.00 +# CHECK-NEXT: Block RThroughput: 1.3 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 0 0.25 xorq %rax, %rax +# CHECK-NEXT: 1 1 0.33 movq %rax, %rbx +# CHECK-NEXT: 1 1 0.33 movq %rbx, %rcx +# CHECK-NEXT: 1 1 0.33 movq %rcx, %rdx +# CHECK-NEXT: 1 1 0.33 movq %rdx, %rax + +# CHECK: Register File statistics: +# CHECK-NEXT: Total number of mappings created: 18 +# CHECK-NEXT: Max number of mappings used: 15 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 1.33 1.33 - 1.33 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - - - - - - xorq %rax, %rax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movq %rax, %rbx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movq %rbx, %rcx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movq %rcx, %rdx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movq %rdx, %rax + +# CHECK: Timeline view: +# CHECK-NEXT: 01234 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DR . . . xorq %rax, %rax +# CHECK-NEXT: [0,1] DeER . . . movq %rax, %rbx +# CHECK-NEXT: [0,2] D=eER. . . movq %rbx, %rcx +# CHECK-NEXT: [0,3] D==eER . . movq %rcx, %rdx +# CHECK-NEXT: [0,4] .D==eER . . movq %rdx, %rax +# CHECK-NEXT: [1,0] .D===ER . . xorq %rax, %rax +# CHECK-NEXT: [1,1] .D===eER . . movq %rax, %rbx +# CHECK-NEXT: [1,2] .D====eER . . movq %rbx, %rcx +# CHECK-NEXT: [1,3] . D====eER. . movq %rcx, %rdx +# CHECK-NEXT: [1,4] . D=====eER . movq %rdx, %rax +# CHECK-NEXT: [2,0] . D======ER . xorq %rax, %rax +# CHECK-NEXT: [2,1] . D======eER . movq %rax, %rbx +# CHECK-NEXT: [2,2] . D======eER . movq %rbx, %rcx +# CHECK-NEXT: [2,3] . D=======eER. movq %rcx, %rdx +# CHECK-NEXT: [2,4] . D========eER movq %rdx, %rax + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 3.7 0.0 0.0 xorq %rax, %rax +# CHECK-NEXT: 1. 3 4.0 0.3 0.0 movq %rax, %rbx +# CHECK-NEXT: 2. 3 4.7 0.0 0.0 movq %rbx, %rcx +# CHECK-NEXT: 3. 3 5.3 0.0 0.0 movq %rcx, %rdx +# CHECK-NEXT: 4. 3 6.0 0.0 0.0 movq %rdx, %rax diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/register-files-1.s b/llvm/test/tools/llvm-mca/X86/BdVer2/register-files-1.s new file mode 100644 index 00000000000..d20b50dbec1 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/register-files-1.s @@ -0,0 +1,77 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=5 -instruction-info=false -dispatch-stats -register-file-stats -timeline < %s | FileCheck %s + +vaddps %xmm0, %xmm0, %xmm0 +vmulps %xmm0, %xmm0, %xmm0 + +# CHECK: Iterations: 5 +# CHECK-NEXT: Instructions: 10 +# CHECK-NEXT: Total Cycles: 43 +# CHECK-NEXT: Total uOps: 10 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.23 +# CHECK-NEXT: IPC: 0.23 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Dynamic Dispatch Stall Cycles: +# CHECK-NEXT: RAT - Register unavailable: 0 +# CHECK-NEXT: RCU - Retire tokens unavailable: 0 +# CHECK-NEXT: SCHEDQ - Scheduler full: 0 +# CHECK-NEXT: LQ - Load queue full: 0 +# CHECK-NEXT: SQ - Store queue full: 0 +# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 + +# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: +# CHECK-NEXT: [# dispatched], [# cycles] +# CHECK-NEXT: 0, 40 (93.0%) +# CHECK-NEXT: 2, 1 (2.3%) +# CHECK-NEXT: 4, 2 (4.7%) + +# CHECK: Register File statistics: +# CHECK-NEXT: Total number of mappings created: 10 +# CHECK-NEXT: Max number of mappings used: 10 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 1.00 1.00 - - - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - - - - vaddps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: - - 1.00 - - - - - vmulps %xmm0, %xmm0, %xmm0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 0123456789 +# CHECK-NEXT: Index 0123456789 0123456789 012 + +# CHECK: [0,0] DeeeER . . . . . . . . vaddps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: [0,1] D===eeeeeER . . . . . . . vmulps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: [1,0] D========eeeER . . . . . . . vaddps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: [1,1] D===========eeeeeER . . . . . . vmulps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: [2,0] .D===============eeeER . . . . . vaddps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: [2,1] .D==================eeeeeER . . . . vmulps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: [3,0] .D=======================eeeER. . . . vaddps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: [3,1] .D==========================eeeeeER. . . vmulps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: [4,0] . D==============================eeeER . . vaddps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: [4,1] . D=================================eeeeeER vmulps %xmm0, %xmm0, %xmm0 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 5 16.2 0.2 0.0 vaddps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: 1. 5 19.2 0.0 0.0 vmulps %xmm0, %xmm0, %xmm0 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/register-files-2.s b/llvm/test/tools/llvm-mca/X86/BdVer2/register-files-2.s new file mode 100644 index 00000000000..bcf2a08bc02 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/register-files-2.s @@ -0,0 +1,77 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -register-file-size=5 -iterations=5 -instruction-info=false -dispatch-stats -register-file-stats -timeline < %s | FileCheck %s + +vaddps %xmm0, %xmm0, %xmm0 +vmulps %xmm0, %xmm0, %xmm0 + +# CHECK: Iterations: 5 +# CHECK-NEXT: Instructions: 10 +# CHECK-NEXT: Total Cycles: 43 +# CHECK-NEXT: Total uOps: 10 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.23 +# CHECK-NEXT: IPC: 0.23 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Dynamic Dispatch Stall Cycles: +# CHECK-NEXT: RAT - Register unavailable: 20 (46.5%) +# CHECK-NEXT: RCU - Retire tokens unavailable: 0 +# CHECK-NEXT: SCHEDQ - Scheduler full: 0 +# CHECK-NEXT: LQ - Load queue full: 0 +# CHECK-NEXT: SQ - Store queue full: 0 +# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 + +# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: +# CHECK-NEXT: [# dispatched], [# cycles] +# CHECK-NEXT: 0, 36 (83.7%) +# CHECK-NEXT: 1, 6 (14.0%) +# CHECK-NEXT: 4, 1 (2.3%) + +# CHECK: Register File statistics: +# CHECK-NEXT: Total number of mappings created: 10 +# CHECK-NEXT: Max number of mappings used: 5 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 1.00 1.00 - - - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - - - - vaddps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: - - 1.00 - - - - - vmulps %xmm0, %xmm0, %xmm0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 0123456789 +# CHECK-NEXT: Index 0123456789 0123456789 012 + +# CHECK: [0,0] DeeeER . . . . . . . . vaddps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: [0,1] D===eeeeeER . . . . . . . vmulps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: [1,0] D========eeeER . . . . . . . vaddps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: [1,1] D===========eeeeeER . . . . . . vmulps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: [2,0] .D===============eeeER . . . . . vaddps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: [2,1] . D==============eeeeeER . . . . vmulps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: [3,0] . . D==============eeeER. . . . vaddps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: [3,1] . . . D==============eeeeeER. . . vmulps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: [4,0] . . . . D==============eeeER . . vaddps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: [4,1] . . . . .D==============eeeeeER vmulps %xmm0, %xmm0, %xmm0 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 5 11.2 0.2 0.0 vaddps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: 1. 5 12.2 0.0 0.0 vmulps %xmm0, %xmm0, %xmm0 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/register-files-3.s b/llvm/test/tools/llvm-mca/X86/BdVer2/register-files-3.s new file mode 100644 index 00000000000..0be7dd3978e --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/register-files-3.s @@ -0,0 +1,76 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -register-file-size=5 -iterations=2 -dispatch-stats -register-file-stats -timeline < %s | FileCheck %s + +idiv %eax + +# CHECK: Iterations: 2 +# CHECK-NEXT: Instructions: 2 +# CHECK-NEXT: Total Cycles: 55 +# CHECK-NEXT: Total uOps: 2 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.04 +# CHECK-NEXT: IPC: 0.04 +# CHECK-NEXT: Block RThroughput: 10.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 25 10.00 U idivl %eax + +# CHECK: Dynamic Dispatch Stall Cycles: +# CHECK-NEXT: RAT - Register unavailable: 27 (49.1%) +# CHECK-NEXT: RCU - Retire tokens unavailable: 0 +# CHECK-NEXT: SCHEDQ - Scheduler full: 0 +# CHECK-NEXT: LQ - Load queue full: 0 +# CHECK-NEXT: SQ - Store queue full: 0 +# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 + +# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: +# CHECK-NEXT: [# dispatched], [# cycles] +# CHECK-NEXT: 0, 53 (96.4%) +# CHECK-NEXT: 1, 2 (3.6%) + +# CHECK: Register File statistics: +# CHECK-NEXT: Total number of mappings created: 6 +# CHECK-NEXT: Max number of mappings used: 3 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: 10.00 - 1.00 - - - - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: 10.00 - 1.00 - - - - - idivl %eax + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 0123456789 01234 +# CHECK-NEXT: Index 0123456789 0123456789 0123456789 + +# CHECK: [0,0] DeeeeeeeeeeeeeeeeeeeeeeeeeER . . . . . . idivl %eax +# CHECK-NEXT: [1,0] . . . . . . DeeeeeeeeeeeeeeeeeeeeeeeeeER idivl %eax + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 1.0 1.0 0.0 idivl %eax diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/register-files-4.s b/llvm/test/tools/llvm-mca/X86/BdVer2/register-files-4.s new file mode 100644 index 00000000000..8ad203d0151 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/register-files-4.s @@ -0,0 +1,60 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=22 -dispatch-stats -register-file-stats -resource-pressure=false -timeline -timeline-max-iterations=3 < %s | FileCheck %s + +idiv %eax + +# CHECK: Iterations: 22 +# CHECK-NEXT: Instructions: 22 +# CHECK-NEXT: Total Cycles: 553 +# CHECK-NEXT: Total uOps: 22 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.04 +# CHECK-NEXT: IPC: 0.04 +# CHECK-NEXT: Block RThroughput: 10.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 25 10.00 U idivl %eax + +# CHECK: Dynamic Dispatch Stall Cycles: +# CHECK-NEXT: RAT - Register unavailable: 0 +# CHECK-NEXT: RCU - Retire tokens unavailable: 0 +# CHECK-NEXT: SCHEDQ - Scheduler full: 0 +# CHECK-NEXT: LQ - Load queue full: 0 +# CHECK-NEXT: SQ - Store queue full: 0 +# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 + +# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: +# CHECK-NEXT: [# dispatched], [# cycles] +# CHECK-NEXT: 0, 547 (98.9%) +# CHECK-NEXT: 2, 1 (0.2%) +# CHECK-NEXT: 4, 5 (0.9%) + +# CHECK: Register File statistics: +# CHECK-NEXT: Total number of mappings created: 66 +# CHECK-NEXT: Max number of mappings used: 66 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 0123456789 0123456789 01234567 +# CHECK-NEXT: Index 0123456789 0123456789 0123456789 0123456789 + +# CHECK: [0,0] DeeeeeeeeeeeeeeeeeeeeeeeeeER . . . . . . . . . . . idivl %eax +# CHECK-NEXT: [1,0] D=========================eeeeeeeeeeeeeeeeeeeeeeeeeER . . . . . . idivl %eax +# CHECK-NEXT: [2,0] D==================================================eeeeeeeeeeeeeeeeeeeeeeeeeER idivl %eax + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 26.0 0.3 0.0 idivl %eax diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/register-files-5.s b/llvm/test/tools/llvm-mca/X86/BdVer2/register-files-5.s new file mode 100644 index 00000000000..31696730fd2 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/register-files-5.s @@ -0,0 +1,143 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -resource-pressure=false -instruction-info=false -dispatch-stats -register-file-stats -timeline < %s | FileCheck %s + + vdivps %ymm0, %ymm0, %ymm1 + vaddps %ymm0, %ymm0, %ymm2 + vaddps %ymm0, %ymm0, %ymm3 + vaddps %ymm0, %ymm0, %ymm4 + vaddps %ymm0, %ymm0, %ymm5 + vaddps %ymm0, %ymm0, %ymm6 + vaddps %ymm0, %ymm0, %ymm7 + vaddps %ymm0, %ymm0, %ymm8 + vaddps %ymm0, %ymm0, %ymm9 + vaddps %ymm0, %ymm0, %ymm10 + vaddps %ymm0, %ymm0, %ymm11 + vaddps %ymm0, %ymm0, %ymm12 + vaddps %ymm0, %ymm0, %ymm13 + vaddps %ymm0, %ymm0, %ymm14 + vaddps %ymm0, %ymm0, %ymm15 + vaddps %ymm2, %ymm0, %ymm0 + vaddps %ymm2, %ymm0, %ymm3 + vaddps %ymm2, %ymm0, %ymm4 + vaddps %ymm2, %ymm0, %ymm5 + vaddps %ymm2, %ymm0, %ymm6 + vaddps %ymm2, %ymm0, %ymm7 + vaddps %ymm2, %ymm0, %ymm8 + vaddps %ymm2, %ymm0, %ymm9 + vaddps %ymm2, %ymm0, %ymm10 + vaddps %ymm2, %ymm0, %ymm11 + vaddps %ymm2, %ymm0, %ymm12 + vaddps %ymm2, %ymm0, %ymm13 + vaddps %ymm2, %ymm0, %ymm14 + vaddps %ymm2, %ymm0, %ymm15 + vaddps %ymm3, %ymm0, %ymm2 + vaddps %ymm3, %ymm0, %ymm4 + vaddps %ymm3, %ymm0, %ymm5 + vaddps %ymm3, %ymm0, %ymm6 + +# CHECK: Iterations: 1 +# CHECK-NEXT: Instructions: 33 +# CHECK-NEXT: Total Cycles: 37 +# CHECK-NEXT: Total uOps: 35 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.95 +# CHECK-NEXT: IPC: 0.89 +# CHECK-NEXT: Block RThroughput: 32.0 + +# CHECK: Dynamic Dispatch Stall Cycles: +# CHECK-NEXT: RAT - Register unavailable: 0 +# CHECK-NEXT: RCU - Retire tokens unavailable: 0 +# CHECK-NEXT: SCHEDQ - Scheduler full: 0 +# CHECK-NEXT: LQ - Load queue full: 0 +# CHECK-NEXT: SQ - Store queue full: 0 +# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 + +# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: +# CHECK-NEXT: [# dispatched], [# cycles] +# CHECK-NEXT: 0, 28 (75.7%) +# CHECK-NEXT: 3, 1 (2.7%) +# CHECK-NEXT: 4, 8 (21.6%) + +# CHECK: Register File statistics: +# CHECK-NEXT: Total number of mappings created: 33 +# CHECK-NEXT: Max number of mappings used: 33 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 0123456 +# CHECK-NEXT: Index 0123456789 0123456789 + +# CHECK: [0,0] DeeeeeeeeeeeeeeeeeeeeeeeeeeeeeER .. vdivps %ymm0, %ymm0, %ymm1 +# CHECK-NEXT: [0,1] DeeeE--------------------------R .. vaddps %ymm0, %ymm0, %ymm2 +# CHECK-NEXT: [0,2] .DeeeE-------------------------R .. vaddps %ymm0, %ymm0, %ymm3 +# CHECK-NEXT: [0,3] .D=eeeE------------------------R .. vaddps %ymm0, %ymm0, %ymm4 +# CHECK-NEXT: [0,4] .D==eeeE-----------------------R .. vaddps %ymm0, %ymm0, %ymm5 +# CHECK-NEXT: [0,5] .D===eeeE----------------------R .. vaddps %ymm0, %ymm0, %ymm6 +# CHECK-NEXT: [0,6] . D===eeeE---------------------R .. vaddps %ymm0, %ymm0, %ymm7 +# CHECK-NEXT: [0,7] . D=====eeeE-------------------R .. vaddps %ymm0, %ymm0, %ymm8 +# CHECK-NEXT: [0,8] . D======eeeE------------------R .. vaddps %ymm0, %ymm0, %ymm9 +# CHECK-NEXT: [0,9] . D=======eeeE-----------------R .. vaddps %ymm0, %ymm0, %ymm10 +# CHECK-NEXT: [0,10] . D=======eeeE----------------R .. vaddps %ymm0, %ymm0, %ymm11 +# CHECK-NEXT: [0,11] . D========eeeE---------------R .. vaddps %ymm0, %ymm0, %ymm12 +# CHECK-NEXT: [0,12] . D=========eeeE--------------R .. vaddps %ymm0, %ymm0, %ymm13 +# CHECK-NEXT: [0,13] . D===========eeeE------------R .. vaddps %ymm0, %ymm0, %ymm14 +# CHECK-NEXT: [0,14] . D===========eeeE-----------R .. vaddps %ymm0, %ymm0, %ymm15 +# CHECK-NEXT: [0,15] . D==eeeE--------------------R .. vaddps %ymm2, %ymm0, %ymm0 +# CHECK-NEXT: [0,16] . D=========eeeE-------------R .. vaddps %ymm2, %ymm0, %ymm3 +# CHECK-NEXT: [0,17] . D============eeeE----------R .. vaddps %ymm2, %ymm0, %ymm4 +# CHECK-NEXT: [0,18] . D============eeeE---------R .. vaddps %ymm2, %ymm0, %ymm5 +# CHECK-NEXT: [0,19] . D=============eeeE--------R .. vaddps %ymm2, %ymm0, %ymm6 +# CHECK-NEXT: [0,20] . D==============eeeE-------R .. vaddps %ymm2, %ymm0, %ymm7 +# CHECK-NEXT: [0,21] . D===============eeeE------R .. vaddps %ymm2, %ymm0, %ymm8 +# CHECK-NEXT: [0,22] . .D===============eeeE-----R .. vaddps %ymm2, %ymm0, %ymm9 +# CHECK-NEXT: [0,23] . .D================eeeE----R .. vaddps %ymm2, %ymm0, %ymm10 +# CHECK-NEXT: [0,24] . .D=================eeeE---R .. vaddps %ymm2, %ymm0, %ymm11 +# CHECK-NEXT: [0,25] . .D==================eeeE--R .. vaddps %ymm2, %ymm0, %ymm12 +# CHECK-NEXT: [0,26] . . D==================eeeE-R .. vaddps %ymm2, %ymm0, %ymm13 +# CHECK-NEXT: [0,27] . . D===================eeeER .. vaddps %ymm2, %ymm0, %ymm14 +# CHECK-NEXT: [0,28] . . D====================eeeER .. vaddps %ymm2, %ymm0, %ymm15 +# CHECK-NEXT: [0,29] . . D=====================eeeER .. vaddps %ymm3, %ymm0, %ymm2 +# CHECK-NEXT: [0,30] . . D=====================eeeER.. vaddps %ymm3, %ymm0, %ymm4 +# CHECK-NEXT: [0,31] . . D======================eeeER. vaddps %ymm3, %ymm0, %ymm5 +# CHECK-NEXT: [0,32] . . D=======================eeeER vaddps %ymm3, %ymm0, %ymm6 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 1 1.0 1.0 0.0 vdivps %ymm0, %ymm0, %ymm1 +# CHECK-NEXT: 1. 1 1.0 1.0 26.0 vaddps %ymm0, %ymm0, %ymm2 +# CHECK-NEXT: 2. 1 1.0 1.0 25.0 vaddps %ymm0, %ymm0, %ymm3 +# CHECK-NEXT: 3. 1 2.0 2.0 24.0 vaddps %ymm0, %ymm0, %ymm4 +# CHECK-NEXT: 4. 1 3.0 3.0 23.0 vaddps %ymm0, %ymm0, %ymm5 +# CHECK-NEXT: 5. 1 4.0 4.0 22.0 vaddps %ymm0, %ymm0, %ymm6 +# CHECK-NEXT: 6. 1 4.0 4.0 21.0 vaddps %ymm0, %ymm0, %ymm7 +# CHECK-NEXT: 7. 1 6.0 6.0 19.0 vaddps %ymm0, %ymm0, %ymm8 +# CHECK-NEXT: 8. 1 7.0 7.0 18.0 vaddps %ymm0, %ymm0, %ymm9 +# CHECK-NEXT: 9. 1 8.0 8.0 17.0 vaddps %ymm0, %ymm0, %ymm10 +# CHECK-NEXT: 10. 1 8.0 8.0 16.0 vaddps %ymm0, %ymm0, %ymm11 +# CHECK-NEXT: 11. 1 9.0 9.0 15.0 vaddps %ymm0, %ymm0, %ymm12 +# CHECK-NEXT: 12. 1 10.0 10.0 14.0 vaddps %ymm0, %ymm0, %ymm13 +# CHECK-NEXT: 13. 1 12.0 12.0 12.0 vaddps %ymm0, %ymm0, %ymm14 +# CHECK-NEXT: 14. 1 12.0 12.0 11.0 vaddps %ymm0, %ymm0, %ymm15 +# CHECK-NEXT: 15. 1 3.0 3.0 20.0 vaddps %ymm2, %ymm0, %ymm0 +# CHECK-NEXT: 16. 1 10.0 4.0 13.0 vaddps %ymm2, %ymm0, %ymm3 +# CHECK-NEXT: 17. 1 13.0 7.0 10.0 vaddps %ymm2, %ymm0, %ymm4 +# CHECK-NEXT: 18. 1 13.0 8.0 9.0 vaddps %ymm2, %ymm0, %ymm5 +# CHECK-NEXT: 19. 1 14.0 9.0 8.0 vaddps %ymm2, %ymm0, %ymm6 +# CHECK-NEXT: 20. 1 15.0 10.0 7.0 vaddps %ymm2, %ymm0, %ymm7 +# CHECK-NEXT: 21. 1 16.0 11.0 6.0 vaddps %ymm2, %ymm0, %ymm8 +# CHECK-NEXT: 22. 1 16.0 12.0 5.0 vaddps %ymm2, %ymm0, %ymm9 +# CHECK-NEXT: 23. 1 17.0 13.0 4.0 vaddps %ymm2, %ymm0, %ymm10 +# CHECK-NEXT: 24. 1 18.0 14.0 3.0 vaddps %ymm2, %ymm0, %ymm11 +# CHECK-NEXT: 25. 1 19.0 15.0 2.0 vaddps %ymm2, %ymm0, %ymm12 +# CHECK-NEXT: 26. 1 19.0 16.0 1.0 vaddps %ymm2, %ymm0, %ymm13 +# CHECK-NEXT: 27. 1 20.0 17.0 0.0 vaddps %ymm2, %ymm0, %ymm14 +# CHECK-NEXT: 28. 1 21.0 18.0 0.0 vaddps %ymm2, %ymm0, %ymm15 +# CHECK-NEXT: 29. 1 22.0 12.0 0.0 vaddps %ymm3, %ymm0, %ymm2 +# CHECK-NEXT: 30. 1 22.0 13.0 0.0 vaddps %ymm3, %ymm0, %ymm4 +# CHECK-NEXT: 31. 1 23.0 14.0 0.0 vaddps %ymm3, %ymm0, %ymm5 +# CHECK-NEXT: 32. 1 24.0 15.0 0.0 vaddps %ymm3, %ymm0, %ymm6 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/resources-3dnow.s b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-3dnow.s new file mode 100644 index 00000000000..52a0968d1fd --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-3dnow.s @@ -0,0 +1,208 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +femms + +pavgusb %mm0, %mm2 +pavgusb (%rax), %mm2 + +pf2id %mm0, %mm2 +pf2id (%rax), %mm2 + +pf2iw %mm0, %mm2 +pf2iw (%rax), %mm2 + +pfacc %mm0, %mm2 +pfacc (%rax), %mm2 + +pfadd %mm0, %mm2 +pfadd (%rax), %mm2 + +pfcmpeq %mm0, %mm2 +pfcmpeq (%rax), %mm2 + +pfcmpge %mm0, %mm2 +pfcmpge (%rax), %mm2 + +pfcmpgt %mm0, %mm2 +pfcmpgt (%rax), %mm2 + +pfmax %mm0, %mm2 +pfmax (%rax), %mm2 + +pfmin %mm0, %mm2 +pfmin (%rax), %mm2 + +pfmul %mm0, %mm2 +pfmul (%rax), %mm2 + +pfnacc %mm0, %mm2 +pfnacc (%rax), %mm2 + +pfpnacc %mm0, %mm2 +pfpnacc (%rax), %mm2 + +pfrcp %mm0, %mm2 +pfrcp (%rax), %mm2 + +pfrcpit1 %mm0, %mm2 +pfrcpit1 (%rax), %mm2 + +pfrcpit2 %mm0, %mm2 +pfrcpit2 (%rax), %mm2 + +pfrsqit1 %mm0, %mm2 +pfrsqit1 (%rax), %mm2 + +pfrsqrt %mm0, %mm2 +pfrsqrt (%rax), %mm2 + +pfsub %mm0, %mm2 +pfsub (%rax), %mm2 + +pfsubr %mm0, %mm2 +pfsubr (%rax), %mm2 + +pi2fd %mm0, %mm2 +pi2fd (%rax), %mm2 + +pi2fw %mm0, %mm2 +pi2fw (%rax), %mm2 + +pmulhrw %mm0, %mm2 +pmulhrw (%rax), %mm2 + +prefetch (%rax) +prefetchw (%rax) + +pswapd %mm0, %mm2 +pswapd (%rax), %mm2 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 31 31 10.33 * * U femms +# CHECK-NEXT: 1 3 1.00 pavgusb %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * pavgusb (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pf2id %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pf2id (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pf2iw %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pf2iw (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pfacc %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pfacc (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pfadd %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pfadd (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pfcmpeq %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pfcmpeq (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pfcmpge %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pfcmpge (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pfcmpgt %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pfcmpgt (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pfmax %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pfmax (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pfmin %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pfmin (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pfmul %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pfmul (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pfnacc %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pfnacc (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pfpnacc %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pfpnacc (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pfrcp %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pfrcp (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pfrcpit1 %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pfrcpit1 (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pfrcpit2 %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pfrcpit2 (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pfrsqit1 %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pfrsqit1 (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pfrsqrt %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pfrsqrt (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pfsub %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pfsub (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pfsubr %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pfsubr (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pi2fd %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pi2fd (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pi2fw %mm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * pi2fw (%rax), %mm2 +# CHECK-NEXT: 1 5 1.00 pmulhrw %mm0, %mm2 +# CHECK-NEXT: 2 10 1.00 * pmulhrw (%rax), %mm2 +# CHECK-NEXT: 1 5 0.50 * * prefetch (%rax) +# CHECK-NEXT: 1 5 0.50 * * prefetchw (%rax) +# CHECK-NEXT: 1 1 1.00 pswapd %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * pswapd (%rax), %mm2 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 12.33 54.33 - 12.33 13.00 13.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 10.33 10.33 - 10.33 - - femms +# CHECK-NEXT: - - - 1.00 - - - - pavgusb %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pavgusb (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pf2id %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pf2id (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pf2iw %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pf2iw (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pfacc %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfacc (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pfadd %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfadd (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pfcmpeq %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfcmpeq (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pfcmpge %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfcmpge (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pfcmpgt %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfcmpgt (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pfmax %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfmax (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pfmin %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfmin (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pfmul %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfmul (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pfnacc %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfnacc (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pfpnacc %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfpnacc (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pfrcp %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfrcp (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pfrcpit1 %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfrcpit1 (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pfrcpit2 %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfrcpit2 (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pfrsqit1 %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfrsqit1 (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pfrsqrt %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfrsqrt (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pfsub %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfsub (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pfsubr %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfsubr (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pi2fd %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pi2fd (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pi2fw %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pi2fw (%rax), %mm2 +# CHECK-NEXT: - - 1.00 - - - - - pmulhrw %mm0, %mm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmulhrw (%rax), %mm2 +# CHECK-NEXT: - - - - - - 0.50 0.50 prefetch (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 prefetchw (%rax) +# CHECK-NEXT: - - - - - 1.00 - - pswapd %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 pswapd (%rax), %mm2 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/resources-adx.s b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-adx.s new file mode 100644 index 00000000000..25f08545e4a --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-adx.s @@ -0,0 +1,55 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +adcx %ebx, %ecx +adcx (%rbx), %ecx +adcx %rbx, %rcx +adcx (%rbx), %rcx + +adox %ebx, %ecx +adox (%rbx), %ecx +adox %rbx, %rcx +adox (%rbx), %rcx + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 2 2 0.67 adcxl %ebx, %ecx +# CHECK-NEXT: 3 7 0.67 * adcxl (%rbx), %ecx +# CHECK-NEXT: 2 2 0.67 adcxq %rbx, %rcx +# CHECK-NEXT: 3 7 0.67 * adcxq (%rbx), %rcx +# CHECK-NEXT: 2 2 0.67 adoxl %ebx, %ecx +# CHECK-NEXT: 3 7 0.67 * adoxl (%rbx), %ecx +# CHECK-NEXT: 2 2 0.67 adoxq %rbx, %rcx +# CHECK-NEXT: 3 7 0.67 * adoxq (%rbx), %rcx + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 6.67 2.67 - 6.67 2.00 2.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcxl %ebx, %ecx +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 adcxl (%rbx), %ecx +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcxq %rbx, %rcx +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 adcxq (%rbx), %rcx +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adoxl %ebx, %ecx +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 adoxl (%rbx), %ecx +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adoxq %rbx, %rcx +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 adoxq (%rbx), %rcx diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/resources-aes.s b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-aes.s new file mode 100644 index 00000000000..5720f208ecb --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-aes.s @@ -0,0 +1,71 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +aesdec %xmm0, %xmm2 +aesdec (%rax), %xmm2 + +aesdeclast %xmm0, %xmm2 +aesdeclast (%rax), %xmm2 + +aesenc %xmm0, %xmm2 +aesenc (%rax), %xmm2 + +aesenclast %xmm0, %xmm2 +aesenclast (%rax), %xmm2 + +aesimc %xmm0, %xmm2 +aesimc (%rax), %xmm2 + +aeskeygenassist $22, %xmm0, %xmm2 +aeskeygenassist $22, (%rax), %xmm2 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 2 7 1.00 aesdec %xmm0, %xmm2 +# CHECK-NEXT: 3 13 1.00 * aesdec (%rax), %xmm2 +# CHECK-NEXT: 2 7 1.00 aesdeclast %xmm0, %xmm2 +# CHECK-NEXT: 3 13 1.00 * aesdeclast (%rax), %xmm2 +# CHECK-NEXT: 2 7 1.00 aesenc %xmm0, %xmm2 +# CHECK-NEXT: 3 13 1.00 * aesenc (%rax), %xmm2 +# CHECK-NEXT: 2 7 1.00 aesenclast %xmm0, %xmm2 +# CHECK-NEXT: 3 13 1.00 * aesenclast (%rax), %xmm2 +# CHECK-NEXT: 2 12 2.00 aesimc %xmm0, %xmm2 +# CHECK-NEXT: 3 18 2.00 * aesimc (%rax), %xmm2 +# CHECK-NEXT: 1 8 3.67 aeskeygenassist $22, %xmm0, %xmm2 +# CHECK-NEXT: 1 8 3.33 * aeskeygenassist $22, (%rax), %xmm2 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 9.67 9.67 - 21.67 3.00 3.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 0.33 0.33 - 1.33 - - aesdec %xmm0, %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 1.33 0.50 0.50 aesdec (%rax), %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 1.33 - - aesdeclast %xmm0, %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 1.33 0.50 0.50 aesdeclast (%rax), %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 1.33 - - aesenc %xmm0, %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 1.33 0.50 0.50 aesenc (%rax), %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 1.33 - - aesenclast %xmm0, %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 1.33 0.50 0.50 aesenclast (%rax), %xmm2 +# CHECK-NEXT: - - - - - 2.00 - - aesimc %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 2.00 0.50 0.50 aesimc (%rax), %xmm2 +# CHECK-NEXT: - - 3.67 3.67 - 3.67 - - aeskeygenassist $22, %xmm0, %xmm2 +# CHECK-NEXT: - - 3.33 3.33 - 3.33 0.50 0.50 aeskeygenassist $22, (%rax), %xmm2 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/resources-avx1.s b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-avx1.s new file mode 100644 index 00000000000..f0bf9e27294 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-avx1.s @@ -0,0 +1,2431 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +vaddpd %xmm0, %xmm1, %xmm2 +vaddpd (%rax), %xmm1, %xmm2 + +vaddpd %ymm0, %ymm1, %ymm2 +vaddpd (%rax), %ymm1, %ymm2 + +vaddps %xmm0, %xmm1, %xmm2 +vaddps (%rax), %xmm1, %xmm2 + +vaddps %ymm0, %ymm1, %ymm2 +vaddps (%rax), %ymm1, %ymm2 + +vaddsd %xmm0, %xmm1, %xmm2 +vaddsd (%rax), %xmm1, %xmm2 + +vaddss %xmm0, %xmm1, %xmm2 +vaddss (%rax), %xmm1, %xmm2 + +vaddsubpd %xmm0, %xmm1, %xmm2 +vaddsubpd (%rax), %xmm1, %xmm2 + +vaddsubpd %ymm0, %ymm1, %ymm2 +vaddsubpd (%rax), %ymm1, %ymm2 + +vaddsubps %xmm0, %xmm1, %xmm2 +vaddsubps (%rax), %xmm1, %xmm2 + +vaddsubps %ymm0, %ymm1, %ymm2 +vaddsubps (%rax), %ymm1, %ymm2 + +vaesdec %xmm0, %xmm1, %xmm2 +vaesdec (%rax), %xmm1, %xmm2 + +vaesdeclast %xmm0, %xmm1, %xmm2 +vaesdeclast (%rax), %xmm1, %xmm2 + +vaesenc %xmm0, %xmm1, %xmm2 +vaesenc (%rax), %xmm1, %xmm2 + +vaesenclast %xmm0, %xmm1, %xmm2 +vaesenclast (%rax), %xmm1, %xmm2 + +vaesimc %xmm0, %xmm2 +vaesimc (%rax), %xmm2 + +vaeskeygenassist $22, %xmm0, %xmm2 +vaeskeygenassist $22, (%rax), %xmm2 + +vandnpd %xmm0, %xmm1, %xmm2 +vandnpd (%rax), %xmm1, %xmm2 + +vandnpd %ymm0, %ymm1, %ymm2 +vandnpd (%rax), %ymm1, %ymm2 + +vandnps %xmm0, %xmm1, %xmm2 +vandnps (%rax), %xmm1, %xmm2 + +vandnps %ymm0, %ymm1, %ymm2 +vandnps (%rax), %ymm1, %ymm2 + +vandpd %xmm0, %xmm1, %xmm2 +vandpd (%rax), %xmm1, %xmm2 + +vandpd %ymm0, %ymm1, %ymm2 +vandpd (%rax), %ymm1, %ymm2 + +vandps %xmm0, %xmm1, %xmm2 +vandps (%rax), %xmm1, %xmm2 + +vandps %ymm0, %ymm1, %ymm2 +vandps (%rax), %ymm1, %ymm2 + +vblendpd $11, %xmm0, %xmm1, %xmm2 +vblendpd $11, (%rax), %xmm1, %xmm2 + +vblendpd $11, %ymm0, %ymm1, %ymm2 +vblendpd $11, (%rax), %ymm1, %ymm2 + +vblendps $11, %xmm0, %xmm1, %xmm2 +vblendps $11, (%rax), %xmm1, %xmm2 + +vblendps $11, %ymm0, %ymm1, %ymm2 +vblendps $11, (%rax), %ymm1, %ymm2 + +vblendvpd %xmm3, %xmm0, %xmm1, %xmm2 +vblendvpd %xmm3, (%rax), %xmm1, %xmm2 + +vblendvpd %ymm3, %ymm0, %ymm1, %ymm2 +vblendvpd %ymm3, (%rax), %ymm1, %ymm2 + +vblendvps %xmm3, %xmm0, %xmm1, %xmm2 +vblendvps %xmm3, (%rax), %xmm1, %xmm2 + +vblendvps %ymm3, %ymm0, %ymm1, %ymm2 +vblendvps %ymm3, (%rax), %ymm1, %ymm2 + +vbroadcastf128 (%rax), %ymm2 + +vbroadcastsd (%rax), %ymm2 + +vbroadcastss (%rax), %xmm2 +vbroadcastss (%rax), %ymm2 + +vcmppd $0, %xmm0, %xmm1, %xmm2 +vcmppd $0, (%rax), %xmm1, %xmm2 + +vcmppd $0, %ymm0, %ymm1, %ymm2 +vcmppd $0, (%rax), %ymm1, %ymm2 + +vcmpps $0, %xmm0, %xmm1, %xmm2 +vcmpps $0, (%rax), %xmm1, %xmm2 + +vcmpps $0, %ymm0, %ymm1, %ymm2 +vcmpps $0, (%rax), %ymm1, %ymm2 + +vcmpsd $0, %xmm0, %xmm1, %xmm2 +vcmpsd $0, (%rax), %xmm1, %xmm2 + +vcmpss $0, %xmm0, %xmm1, %xmm2 +vcmpss $0, (%rax), %xmm1, %xmm2 + +vcomisd %xmm0, %xmm1 +vcomisd (%rax), %xmm1 + +vcomiss %xmm0, %xmm1 +vcomiss (%rax), %xmm1 + +vcvtdq2pd %xmm0, %xmm2 +vcvtdq2pd (%rax), %xmm2 + +vcvtdq2pd %xmm0, %ymm2 +vcvtdq2pd (%rax), %ymm2 + +vcvtdq2ps %xmm0, %xmm2 +vcvtdq2ps (%rax), %xmm2 + +vcvtdq2ps %ymm0, %ymm2 +vcvtdq2ps (%rax), %ymm2 + +vcvtpd2dqx %xmm0, %xmm2 +vcvtpd2dqx (%rax), %xmm2 + +vcvtpd2dqy %ymm0, %xmm2 +vcvtpd2dqy (%rax), %xmm2 + +vcvtpd2psx %xmm0, %xmm2 +vcvtpd2psx (%rax), %xmm2 + +vcvtpd2psy %ymm0, %xmm2 +vcvtpd2psy (%rax), %xmm2 + +vcvtps2dq %xmm0, %xmm2 +vcvtps2dq (%rax), %xmm2 + +vcvtps2dq %ymm0, %ymm2 +vcvtps2dq (%rax), %ymm2 + +vcvtps2pd %xmm0, %xmm2 +vcvtps2pd (%rax), %xmm2 + +vcvtps2pd %xmm0, %ymm2 +vcvtps2pd (%rax), %ymm2 + +vcvtsd2si %xmm0, %ecx +vcvtsd2si %xmm0, %rcx +vcvtsd2si (%rax), %ecx +vcvtsd2si (%rax), %rcx + +vcvtsd2ss %xmm0, %xmm1, %xmm2 +vcvtsd2ss (%rax), %xmm1, %xmm2 + +vcvtsi2sdl %ecx, %xmm0, %xmm2 +vcvtsi2sdq %rcx, %xmm0, %xmm2 +vcvtsi2sdl (%rax), %xmm0, %xmm2 +vcvtsi2sdq (%rax), %xmm0, %xmm2 + +vcvtsi2ssl %ecx, %xmm0, %xmm2 +vcvtsi2ssq %rcx, %xmm0, %xmm2 +vcvtsi2ssl (%rax), %xmm0, %xmm2 +vcvtsi2ssq (%rax), %xmm0, %xmm2 + +vcvtss2sd %xmm0, %xmm1, %xmm2 +vcvtss2sd (%rax), %xmm1, %xmm2 + +vcvtss2si %xmm0, %ecx +vcvtss2si %xmm0, %rcx +vcvtss2si (%rax), %ecx +vcvtss2si (%rax), %rcx + +vcvttpd2dqx %xmm0, %xmm2 +vcvttpd2dqx (%rax), %xmm2 + +vcvttpd2dqy %ymm0, %xmm2 +vcvttpd2dqy (%rax), %xmm2 + +vcvttps2dq %xmm0, %xmm2 +vcvttps2dq (%rax), %xmm2 + +vcvttps2dq %ymm0, %ymm2 +vcvttps2dq (%rax), %ymm2 + +vcvttsd2si %xmm0, %ecx +vcvttsd2si %xmm0, %rcx +vcvttsd2si (%rax), %ecx +vcvttsd2si (%rax), %rcx + +vcvttss2si %xmm0, %ecx +vcvttss2si %xmm0, %rcx +vcvttss2si (%rax), %ecx +vcvttss2si (%rax), %rcx + +vdivpd %xmm0, %xmm1, %xmm2 +vdivpd (%rax), %xmm1, %xmm2 + +vdivpd %ymm0, %ymm1, %ymm2 +vdivpd (%rax), %ymm1, %ymm2 + +vdivps %xmm0, %xmm1, %xmm2 +vdivps (%rax), %xmm1, %xmm2 + +vdivps %ymm0, %ymm1, %ymm2 +vdivps (%rax), %ymm1, %ymm2 + +vdivsd %xmm0, %xmm1, %xmm2 +vdivsd (%rax), %xmm1, %xmm2 + +vdivss %xmm0, %xmm1, %xmm2 +vdivss (%rax), %xmm1, %xmm2 + +vdppd $22, %xmm0, %xmm1, %xmm2 +vdppd $22, (%rax), %xmm1, %xmm2 + +vdpps $22, %xmm0, %xmm1, %xmm2 +vdpps $22, (%rax), %xmm1, %xmm2 + +vdpps $22, %ymm0, %ymm1, %ymm2 +vdpps $22, (%rax), %ymm1, %ymm2 + +vextractf128 $1, %ymm0, %xmm2 +vextractf128 $1, %ymm0, (%rax) + +vextractps $1, %xmm0, %rcx +vextractps $1, %xmm0, (%rax) + +vhaddpd %xmm0, %xmm1, %xmm2 +vhaddpd (%rax), %xmm1, %xmm2 + +vhaddpd %ymm0, %ymm1, %ymm2 +vhaddpd (%rax), %ymm1, %ymm2 + +vhaddps %xmm0, %xmm1, %xmm2 +vhaddps (%rax), %xmm1, %xmm2 + +vhaddps %ymm0, %ymm1, %ymm2 +vhaddps (%rax), %ymm1, %ymm2 + +vhsubpd %xmm0, %xmm1, %xmm2 +vhsubpd (%rax), %xmm1, %xmm2 + +vhsubpd %ymm0, %ymm1, %ymm2 +vhsubpd (%rax), %ymm1, %ymm2 + +vhsubps %xmm0, %xmm1, %xmm2 +vhsubps (%rax), %xmm1, %xmm2 + +vhsubps %ymm0, %ymm1, %ymm2 +vhsubps (%rax), %ymm1, %ymm2 + +vinsertf128 $1, %xmm0, %ymm1, %ymm2 +vinsertf128 $1, (%rax), %ymm1, %ymm2 + +vinsertps $1, %xmm0, %xmm1, %xmm2 +vinsertps $1, (%rax), %xmm1, %xmm2 + +vlddqu (%rax), %xmm2 +vlddqu (%rax), %ymm2 + +vldmxcsr (%rax) + +vmaskmovdqu %xmm0, %xmm1 + +vmaskmovpd (%rax), %xmm0, %xmm2 +vmaskmovpd (%rax), %ymm0, %ymm2 + +vmaskmovpd %xmm0, %xmm1, (%rax) +vmaskmovpd %ymm0, %ymm1, (%rax) + +vmaskmovps (%rax), %xmm0, %xmm2 +vmaskmovps (%rax), %ymm0, %ymm2 + +vmaskmovps %xmm0, %xmm1, (%rax) +vmaskmovps %ymm0, %ymm1, (%rax) + +vmaxpd %xmm0, %xmm1, %xmm2 +vmaxpd (%rax), %xmm1, %xmm2 + +vmaxpd %ymm0, %ymm1, %ymm2 +vmaxpd (%rax), %ymm1, %ymm2 + +vmaxps %xmm0, %xmm1, %xmm2 +vmaxps (%rax), %xmm1, %xmm2 + +vmaxps %ymm0, %ymm1, %ymm2 +vmaxps (%rax), %ymm1, %ymm2 + +vmaxsd %xmm0, %xmm1, %xmm2 +vmaxsd (%rax), %xmm1, %xmm2 + +vmaxss %xmm0, %xmm1, %xmm2 +vmaxss (%rax), %xmm1, %xmm2 + +vminpd %xmm0, %xmm1, %xmm2 +vminpd (%rax), %xmm1, %xmm2 + +vminpd %ymm0, %ymm1, %ymm2 +vminpd (%rax), %ymm1, %ymm2 + +vminps %xmm0, %xmm1, %xmm2 +vminps (%rax), %xmm1, %xmm2 + +vminps %ymm0, %ymm1, %ymm2 +vminps (%rax), %ymm1, %ymm2 + +vminsd %xmm0, %xmm1, %xmm2 +vminsd (%rax), %xmm1, %xmm2 + +vminss %xmm0, %xmm1, %xmm2 +vminss (%rax), %xmm1, %xmm2 + +vmovapd %xmm0, %xmm2 +vmovapd %xmm0, (%rax) +vmovapd (%rax), %xmm2 + +vmovapd %ymm0, %ymm2 +vmovapd %ymm0, (%rax) +vmovapd (%rax), %ymm2 + +vmovaps %xmm0, %xmm2 +vmovaps %xmm0, (%rax) +vmovaps (%rax), %xmm2 + +vmovaps %ymm0, %ymm2 +vmovaps %ymm0, (%rax) +vmovaps (%rax), %ymm2 + +vmovd %eax, %xmm2 +vmovd (%rax), %xmm2 + +vmovd %xmm0, %ecx +vmovd %xmm0, (%rax) + +vmovddup %xmm0, %xmm2 +vmovddup (%rax), %xmm2 + +vmovddup %ymm0, %ymm2 +vmovddup (%rax), %ymm2 + +vmovdqa %xmm0, %xmm2 +vmovdqa %xmm0, (%rax) +vmovdqa (%rax), %xmm2 + +vmovdqa %ymm0, %ymm2 +vmovdqa %ymm0, (%rax) +vmovdqa (%rax), %ymm2 + +vmovdqu %xmm0, %xmm2 +vmovdqu %xmm0, (%rax) +vmovdqu (%rax), %xmm2 + +vmovdqu %ymm0, %ymm2 +vmovdqu %ymm0, (%rax) +vmovdqu (%rax), %ymm2 + +vmovhlps %xmm0, %xmm1, %xmm2 +vmovlhps %xmm0, %xmm1, %xmm2 + +vmovhpd %xmm0, (%rax) +vmovhpd (%rax), %xmm1, %xmm2 + +vmovhps %xmm0, (%rax) +vmovhps (%rax), %xmm1, %xmm2 + +vmovlpd %xmm0, (%rax) +vmovlpd (%rax), %xmm1, %xmm2 + +vmovlps %xmm0, (%rax) +vmovlps (%rax), %xmm1, %xmm2 + +vmovmskpd %xmm0, %rcx +vmovmskpd %ymm0, %rcx + +vmovmskps %xmm0, %rcx +vmovmskps %ymm0, %rcx + +vmovntdq %xmm0, (%rax) +vmovntdq %ymm0, (%rax) + +vmovntdqa (%rax), %xmm2 +vmovntdqa (%rax), %ymm2 + +vmovntpd %xmm0, (%rax) +vmovntpd %ymm0, (%rax) + +vmovntps %xmm0, (%rax) +vmovntps %ymm0, (%rax) + +vmovq %xmm0, %xmm2 + +vmovq %rax, %xmm2 +vmovq (%rax), %xmm2 + +vmovq %xmm0, %rcx +vmovq %xmm0, (%rax) + +vmovsd %xmm0, %xmm1, %xmm2 +vmovsd %xmm0, (%rax) +vmovsd (%rax), %xmm2 + +vmovshdup %xmm0, %xmm2 +vmovshdup (%rax), %xmm2 + +vmovshdup %ymm0, %ymm2 +vmovshdup (%rax), %ymm2 + +vmovsldup %xmm0, %xmm2 +vmovsldup (%rax), %xmm2 + +vmovsldup %ymm0, %ymm2 +vmovsldup (%rax), %ymm2 + +vmovss %xmm0, %xmm1, %xmm2 +vmovss %xmm0, (%rax) +vmovss (%rax), %xmm2 + +vmovupd %xmm0, %xmm2 +vmovupd %xmm0, (%rax) +vmovupd (%rax), %xmm2 + +vmovupd %ymm0, %ymm2 +vmovupd %ymm0, (%rax) +vmovupd (%rax), %ymm2 + +vmovups %xmm0, %xmm2 +vmovups %xmm0, (%rax) +vmovups (%rax), %xmm2 + +vmovups %ymm0, %ymm2 +vmovups %ymm0, (%rax) +vmovups (%rax), %ymm2 + +vmpsadbw $1, %xmm0, %xmm1, %xmm2 +vmpsadbw $1, (%rax), %xmm1, %xmm2 + +vmulpd %xmm0, %xmm1, %xmm2 +vmulpd (%rax), %xmm1, %xmm2 + +vmulpd %ymm0, %ymm1, %ymm2 +vmulpd (%rax), %ymm1, %ymm2 + +vmulps %xmm0, %xmm1, %xmm2 +vmulps (%rax), %xmm1, %xmm2 + +vmulps %ymm0, %ymm1, %ymm2 +vmulps (%rax), %ymm1, %ymm2 + +vmulsd %xmm0, %xmm1, %xmm2 +vmulsd (%rax), %xmm1, %xmm2 + +vmulss %xmm0, %xmm1, %xmm2 +vmulss (%rax), %xmm1, %xmm2 + +vorpd %xmm0, %xmm1, %xmm2 +vorpd (%rax), %xmm1, %xmm2 + +vorpd %ymm0, %ymm1, %ymm2 +vorpd (%rax), %ymm1, %ymm2 + +vorps %xmm0, %xmm1, %xmm2 +vorps (%rax), %xmm1, %xmm2 + +vorps %ymm0, %ymm1, %ymm2 +vorps (%rax), %ymm1, %ymm2 + +vpabsb %xmm0, %xmm2 +vpabsb (%rax), %xmm2 + +vpabsd %xmm0, %xmm2 +vpabsd (%rax), %xmm2 + +vpabsw %xmm0, %xmm2 +vpabsw (%rax), %xmm2 + +vpackssdw %xmm0, %xmm1, %xmm2 +vpackssdw (%rax), %xmm1, %xmm2 + +vpacksswb %xmm0, %xmm1, %xmm2 +vpacksswb (%rax), %xmm1, %xmm2 + +vpackusdw %xmm0, %xmm1, %xmm2 +vpackusdw (%rax), %xmm1, %xmm2 + +vpackuswb %xmm0, %xmm1, %xmm2 +vpackuswb (%rax), %xmm1, %xmm2 + +vpaddb %xmm0, %xmm1, %xmm2 +vpaddb (%rax), %xmm1, %xmm2 + +vpaddd %xmm0, %xmm1, %xmm2 +vpaddd (%rax), %xmm1, %xmm2 + +vpaddq %xmm0, %xmm1, %xmm2 +vpaddq (%rax), %xmm1, %xmm2 + +vpaddsb %xmm0, %xmm1, %xmm2 +vpaddsb (%rax), %xmm1, %xmm2 + +vpaddsw %xmm0, %xmm1, %xmm2 +vpaddsw (%rax), %xmm1, %xmm2 + +vpaddusb %xmm0, %xmm1, %xmm2 +vpaddusb (%rax), %xmm1, %xmm2 + +vpaddusw %xmm0, %xmm1, %xmm2 +vpaddusw (%rax), %xmm1, %xmm2 + +vpaddw %xmm0, %xmm1, %xmm2 +vpaddw (%rax), %xmm1, %xmm2 + +vpalignr $1, %xmm0, %xmm1, %xmm2 +vpalignr $1, (%rax), %xmm1, %xmm2 + +vpand %xmm0, %xmm1, %xmm2 +vpand (%rax), %xmm1, %xmm2 + +vpandn %xmm0, %xmm1, %xmm2 +vpandn (%rax), %xmm1, %xmm2 + +vpavgb %xmm0, %xmm1, %xmm2 +vpavgb (%rax), %xmm1, %xmm2 + +vpavgw %xmm0, %xmm1, %xmm2 +vpavgw (%rax), %xmm1, %xmm2 + +vpblendvb %xmm3, %xmm0, %xmm1, %xmm2 +vpblendvb %xmm3, (%rax), %xmm1, %xmm2 + +vpblendw $11, %xmm0, %xmm1, %xmm2 +vpblendw $11, (%rax), %xmm1, %xmm2 + +vpclmulqdq $11, %xmm0, %xmm1, %xmm2 +vpclmulqdq $11, (%rax), %xmm1, %xmm2 + +vpcmpeqb %xmm0, %xmm1, %xmm2 +vpcmpeqb (%rax), %xmm1, %xmm2 + +vpcmpeqd %xmm0, %xmm1, %xmm2 +vpcmpeqd (%rax), %xmm1, %xmm2 + +vpcmpeqq %xmm0, %xmm1, %xmm2 +vpcmpeqq (%rax), %xmm1, %xmm2 + +vpcmpeqw %xmm0, %xmm1, %xmm2 +vpcmpeqw (%rax), %xmm1, %xmm2 + +vpcmpestri $1, %xmm0, %xmm2 +vpcmpestri $1, (%rax), %xmm2 + +vpcmpestrm $1, %xmm0, %xmm2 +vpcmpestrm $1, (%rax), %xmm2 + +vpcmpgtb %xmm0, %xmm1, %xmm2 +vpcmpgtb (%rax), %xmm1, %xmm2 + +vpcmpgtd %xmm0, %xmm1, %xmm2 +vpcmpgtd (%rax), %xmm1, %xmm2 + +vpcmpgtq %xmm0, %xmm1, %xmm2 +vpcmpgtq (%rax), %xmm1, %xmm2 + +vpcmpgtw %xmm0, %xmm1, %xmm2 +vpcmpgtw (%rax), %xmm1, %xmm2 + +vpcmpistri $1, %xmm0, %xmm2 +vpcmpistri $1, (%rax), %xmm2 + +vpcmpistrm $1, %xmm0, %xmm2 +vpcmpistrm $1, (%rax), %xmm2 + +vperm2f128 $1, %ymm0, %ymm1, %ymm2 +vperm2f128 $1, (%rax), %ymm1, %ymm2 + +vpermilpd $1, %xmm0, %xmm2 +vpermilpd $1, (%rax), %xmm2 +vpermilpd %xmm0, %xmm1, %xmm2 +vpermilpd (%rax), %xmm1, %xmm2 + +vpermilpd $1, %ymm0, %ymm2 +vpermilpd $1, (%rax), %ymm2 +vpermilpd %ymm0, %ymm1, %ymm2 +vpermilpd (%rax), %ymm1, %ymm2 + +vpermilps $1, %xmm0, %xmm2 +vpermilps $1, (%rax), %xmm2 +vpermilps %xmm0, %xmm1, %xmm2 +vpermilps (%rax), %xmm1, %xmm2 + +vpermilps $1, %ymm0, %ymm2 +vpermilps $1, (%rax), %ymm2 +vpermilps %ymm0, %ymm1, %ymm2 +vpermilps (%rax), %ymm1, %ymm2 + +vpextrb $1, %xmm0, %ecx +vpextrb $1, %xmm0, (%rax) + +vpextrd $1, %xmm0, %ecx +vpextrd $1, %xmm0, (%rax) + +vpextrq $1, %xmm0, %rcx +vpextrq $1, %xmm0, (%rax) + +vpextrw $1, %xmm0, %ecx +vpextrw $1, %xmm0, (%rax) + +vphaddd %xmm0, %xmm1, %xmm2 +vphaddd (%rax), %xmm1, %xmm2 + +vphaddsw %xmm0, %xmm1, %xmm2 +vphaddsw (%rax), %xmm1, %xmm2 + +vphaddw %xmm0, %xmm1, %xmm2 +vphaddw (%rax), %xmm1, %xmm2 + +vphminposuw %xmm0, %xmm2 +vphminposuw (%rax), %xmm2 + +vphsubd %xmm0, %xmm1, %xmm2 +vphsubd (%rax), %xmm1, %xmm2 + +vphsubsw %xmm0, %xmm1, %xmm2 +vphsubsw (%rax), %xmm1, %xmm2 + +vphsubw %xmm0, %xmm1, %xmm2 +vphsubw (%rax), %xmm1, %xmm2 + +vpinsrb $1, %eax, %xmm1, %xmm2 +vpinsrb $1, (%rax), %xmm1, %xmm2 + +vpinsrd $1, %eax, %xmm1, %xmm2 +vpinsrd $1, (%rax), %xmm1, %xmm2 + +vpinsrq $1, %rax, %xmm1, %xmm2 +vpinsrq $1, (%rax), %xmm1, %xmm2 + +vpinsrw $1, %eax, %xmm1, %xmm2 +vpinsrw $1, (%rax), %xmm1, %xmm2 + +vpmaddubsw %xmm0, %xmm1, %xmm2 +vpmaddubsw (%rax), %xmm1, %xmm2 + +vpmaddwd %xmm0, %xmm1, %xmm2 +vpmaddwd (%rax), %xmm1, %xmm2 + +vpmaxsb %xmm0, %xmm1, %xmm2 +vpmaxsb (%rax), %xmm1, %xmm2 + +vpmaxsd %xmm0, %xmm1, %xmm2 +vpmaxsd (%rax), %xmm1, %xmm2 + +vpmaxsw %xmm0, %xmm1, %xmm2 +vpmaxsw (%rax), %xmm1, %xmm2 + +vpmaxub %xmm0, %xmm1, %xmm2 +vpmaxub (%rax), %xmm1, %xmm2 + +vpmaxud %xmm0, %xmm1, %xmm2 +vpmaxud (%rax), %xmm1, %xmm2 + +vpmaxuw %xmm0, %xmm1, %xmm2 +vpmaxuw (%rax), %xmm1, %xmm2 + +vpminsb %xmm0, %xmm1, %xmm2 +vpminsb (%rax), %xmm1, %xmm2 + +vpminsd %xmm0, %xmm1, %xmm2 +vpminsd (%rax), %xmm1, %xmm2 + +vpminsw %xmm0, %xmm1, %xmm2 +vpminsw (%rax), %xmm1, %xmm2 + +vpminub %xmm0, %xmm1, %xmm2 +vpminub (%rax), %xmm1, %xmm2 + +vpminud %xmm0, %xmm1, %xmm2 +vpminud (%rax), %xmm1, %xmm2 + +vpminuw %xmm0, %xmm1, %xmm2 +vpminuw (%rax), %xmm1, %xmm2 + +vpmovmskb %xmm0, %rcx + +vpmovsxbd %xmm0, %xmm2 +vpmovsxbd (%rax), %xmm2 + +vpmovsxbq %xmm0, %xmm2 +vpmovsxbq (%rax), %xmm2 + +vpmovsxbw %xmm0, %xmm2 +vpmovsxbw (%rax), %xmm2 + +vpmovsxdq %xmm0, %xmm2 +vpmovsxdq (%rax), %xmm2 + +vpmovsxwd %xmm0, %xmm2 +vpmovsxwd (%rax), %xmm2 + +vpmovsxwq %xmm0, %xmm2 +vpmovsxwq (%rax), %xmm2 + +vpmovzxbd %xmm0, %xmm2 +vpmovzxbd (%rax), %xmm2 + +vpmovzxbq %xmm0, %xmm2 +vpmovzxbq (%rax), %xmm2 + +vpmovzxbw %xmm0, %xmm2 +vpmovzxbw (%rax), %xmm2 + +vpmovzxdq %xmm0, %xmm2 +vpmovzxdq (%rax), %xmm2 + +vpmovzxwd %xmm0, %xmm2 +vpmovzxwd (%rax), %xmm2 + +vpmovzxwq %xmm0, %xmm2 +vpmovzxwq (%rax), %xmm2 + +vpmuldq %xmm0, %xmm1, %xmm2 +vpmuldq (%rax), %xmm1, %xmm2 + +vpmulhrsw %xmm0, %xmm1, %xmm2 +vpmulhrsw (%rax), %xmm1, %xmm2 + +vpmulhuw %xmm0, %xmm1, %xmm2 +vpmulhuw (%rax), %xmm1, %xmm2 + +vpmulhw %xmm0, %xmm1, %xmm2 +vpmulhw (%rax), %xmm1, %xmm2 + +vpmulld %xmm0, %xmm1, %xmm2 +vpmulld (%rax), %xmm1, %xmm2 + +vpmullw %xmm0, %xmm1, %xmm2 +vpmullw (%rax), %xmm1, %xmm2 + +vpmuludq %xmm0, %xmm1, %xmm2 +vpmuludq (%rax), %xmm1, %xmm2 + +vpor %xmm0, %xmm1, %xmm2 +vpor (%rax), %xmm1, %xmm2 + +vpsadbw %xmm0, %xmm1, %xmm2 +vpsadbw (%rax), %xmm1, %xmm2 + +vpshufb %xmm0, %xmm1, %xmm2 +vpshufb (%rax), %xmm1, %xmm2 + +vpshufd $1, %xmm0, %xmm2 +vpshufd $1, (%rax), %xmm2 + +vpshufhw $1, %xmm0, %xmm2 +vpshufhw $1, (%rax), %xmm2 + +vpshuflw $1, %xmm0, %xmm2 +vpshuflw $1, (%rax), %xmm2 + +vpsignb %xmm0, %xmm1, %xmm2 +vpsignb (%rax), %xmm1, %xmm2 + +vpsignd %xmm0, %xmm1, %xmm2 +vpsignd (%rax), %xmm1, %xmm2 + +vpsignw %xmm0, %xmm1, %xmm2 +vpsignw (%rax), %xmm1, %xmm2 + +vpslld $1, %xmm0, %xmm2 +vpslld %xmm0, %xmm1, %xmm2 +vpslld (%rax), %xmm1, %xmm2 + +vpslldq $1, %xmm1, %xmm2 + +vpsllq $1, %xmm0, %xmm2 +vpsllq %xmm0, %xmm1, %xmm2 +vpsllq (%rax), %xmm1, %xmm2 + +vpsllw $1, %xmm0, %xmm2 +vpsllw %xmm0, %xmm1, %xmm2 +vpsllw (%rax), %xmm1, %xmm2 + +vpsrad $1, %xmm0, %xmm2 +vpsrad %xmm0, %xmm1, %xmm2 +vpsrad (%rax), %xmm1, %xmm2 + +vpsraw $1, %xmm0, %xmm2 +vpsraw %xmm0, %xmm1, %xmm2 +vpsraw (%rax), %xmm1, %xmm2 + +vpsrld $1, %xmm0, %xmm2 +vpsrld %xmm0, %xmm1, %xmm2 +vpsrld (%rax), %xmm1, %xmm2 + +vpsrldq $1, %xmm1, %xmm2 + +vpsrlq $1, %xmm0, %xmm2 +vpsrlq %xmm0, %xmm1, %xmm2 +vpsrlq (%rax), %xmm1, %xmm2 + +vpsrlw $1, %xmm0, %xmm2 +vpsrlw %xmm0, %xmm1, %xmm2 +vpsrlw (%rax), %xmm1, %xmm2 + +vpsubb %xmm0, %xmm1, %xmm2 +vpsubb (%rax), %xmm1, %xmm2 + +vpsubd %xmm0, %xmm1, %xmm2 +vpsubd (%rax), %xmm1, %xmm2 + +vpsubq %xmm0, %xmm1, %xmm2 +vpsubq (%rax), %xmm1, %xmm2 + +vpsubsb %xmm0, %xmm1, %xmm2 +vpsubsb (%rax), %xmm1, %xmm2 + +vpsubsw %xmm0, %xmm1, %xmm2 +vpsubsw (%rax), %xmm1, %xmm2 + +vpsubusb %xmm0, %xmm1, %xmm2 +vpsubusb (%rax), %xmm1, %xmm2 + +vpsubusw %xmm0, %xmm1, %xmm2 +vpsubusw (%rax), %xmm1, %xmm2 + +vpsubw %xmm0, %xmm1, %xmm2 +vpsubw (%rax), %xmm1, %xmm2 + +vptest %xmm0, %xmm1 +vptest (%rax), %xmm1 + +vptest %ymm0, %ymm1 +vptest (%rax), %ymm1 + +vpunpckhbw %xmm0, %xmm1, %xmm2 +vpunpckhbw (%rax), %xmm1, %xmm2 + +vpunpckhdq %xmm0, %xmm1, %xmm2 +vpunpckhdq (%rax), %xmm1, %xmm2 + +vpunpckhqdq %xmm0, %xmm1, %xmm2 +vpunpckhqdq (%rax), %xmm1, %xmm2 + +vpunpckhwd %xmm0, %xmm1, %xmm2 +vpunpckhwd (%rax), %xmm1, %xmm2 + +vpunpcklbw %xmm0, %xmm1, %xmm2 +vpunpcklbw (%rax), %xmm1, %xmm2 + +vpunpckldq %xmm0, %xmm1, %xmm2 +vpunpckldq (%rax), %xmm1, %xmm2 + +vpunpcklqdq %xmm0, %xmm1, %xmm2 +vpunpcklqdq (%rax), %xmm1, %xmm2 + +vpunpcklwd %xmm0, %xmm1, %xmm2 +vpunpcklwd (%rax), %xmm1, %xmm2 + +vpxor %xmm0, %xmm1, %xmm2 +vpxor (%rax), %xmm1, %xmm2 + +vrcpps %xmm0, %xmm2 +vrcpps (%rax), %xmm2 + +vrcpps %ymm0, %ymm2 +vrcpps (%rax), %ymm2 + +vrcpss %xmm0, %xmm1, %xmm2 +vrcpss (%rax), %xmm1, %xmm2 + +vroundpd $1, %xmm0, %xmm2 +vroundpd $1, (%rax), %xmm2 + +vroundpd $1, %ymm0, %ymm2 +vroundpd $1, (%rax), %ymm2 + +vroundps $1, %xmm0, %xmm2 +vroundps $1, (%rax), %xmm2 + +vroundps $1, %ymm0, %ymm2 +vroundps $1, (%rax), %ymm2 + +vroundsd $1, %xmm0, %xmm1, %xmm2 +vroundsd $1, (%rax), %xmm1, %xmm2 + +vroundss $1, %xmm0, %xmm1, %xmm2 +vroundss $1, (%rax), %xmm1, %xmm2 + +vrsqrtps %xmm0, %xmm2 +vrsqrtps (%rax), %xmm2 + +vrsqrtps %ymm0, %ymm2 +vrsqrtps (%rax), %ymm2 + +vrsqrtss %xmm0, %xmm1, %xmm2 +vrsqrtss (%rax), %xmm1, %xmm2 + +vshufpd $1, %xmm0, %xmm1, %xmm2 +vshufpd $1, (%rax), %xmm1, %xmm2 + +vshufpd $1, %ymm0, %ymm1, %ymm2 +vshufpd $1, (%rax), %ymm1, %ymm2 + +vshufps $1, %xmm0, %xmm1, %xmm2 +vshufps $1, (%rax), %xmm1, %xmm2 + +vshufps $1, %ymm0, %ymm1, %ymm2 +vshufps $1, (%rax), %ymm1, %ymm2 + +vsqrtpd %xmm0, %xmm2 +vsqrtpd (%rax), %xmm2 + +vsqrtpd %ymm0, %ymm2 +vsqrtpd (%rax), %ymm2 + +vsqrtps %xmm0, %xmm2 +vsqrtps (%rax), %xmm2 + +vsqrtps %ymm0, %ymm2 +vsqrtps (%rax), %ymm2 + +vsqrtsd %xmm0, %xmm1, %xmm2 +vsqrtsd (%rax), %xmm1, %xmm2 + +vsqrtss %xmm0, %xmm1, %xmm2 +vsqrtss (%rax), %xmm1, %xmm2 + +vstmxcsr (%rax) + +vsubpd %xmm0, %xmm1, %xmm2 +vsubpd (%rax), %xmm1, %xmm2 + +vsubpd %ymm0, %ymm1, %ymm2 +vsubpd (%rax), %ymm1, %ymm2 + +vsubps %xmm0, %xmm1, %xmm2 +vsubps (%rax), %xmm1, %xmm2 + +vsubps %ymm0, %ymm1, %ymm2 +vsubps (%rax), %ymm1, %ymm2 + +vsubsd %xmm0, %xmm1, %xmm2 +vsubsd (%rax), %xmm1, %xmm2 + +vsubss %xmm0, %xmm1, %xmm2 +vsubss (%rax), %xmm1, %xmm2 + +vtestpd %xmm0, %xmm1 +vtestpd (%rax), %xmm1 + +vtestpd %ymm0, %ymm1 +vtestpd (%rax), %ymm1 + +vtestps %xmm0, %xmm1 +vtestps (%rax), %xmm1 + +vtestps %ymm0, %ymm1 +vtestps (%rax), %ymm1 + +vucomisd %xmm0, %xmm1 +vucomisd (%rax), %xmm1 + +vucomiss %xmm0, %xmm1 +vucomiss (%rax), %xmm1 + +vunpckhpd %xmm0, %xmm1, %xmm2 +vunpckhpd (%rax), %xmm1, %xmm2 + +vunpckhpd %ymm0, %ymm1, %ymm2 +vunpckhpd (%rax), %ymm1, %ymm2 + +vunpckhps %xmm0, %xmm1, %xmm2 +vunpckhps (%rax), %xmm1, %xmm2 + +vunpckhps %ymm0, %ymm1, %ymm2 +vunpckhps (%rax), %ymm1, %ymm2 + +vunpcklpd %xmm0, %xmm1, %xmm2 +vunpcklpd (%rax), %xmm1, %xmm2 + +vunpcklpd %ymm0, %ymm1, %ymm2 +vunpcklpd (%rax), %ymm1, %ymm2 + +vunpcklps %xmm0, %xmm1, %xmm2 +vunpcklps (%rax), %xmm1, %xmm2 + +vunpcklps %ymm0, %ymm1, %ymm2 +vunpcklps (%rax), %ymm1, %ymm2 + +vxorpd %xmm0, %xmm1, %xmm2 +vxorpd (%rax), %xmm1, %xmm2 + +vxorpd %ymm0, %ymm1, %ymm2 +vxorpd (%rax), %ymm1, %ymm2 + +vxorps %xmm0, %xmm1, %xmm2 +vxorps (%rax), %xmm1, %xmm2 + +vxorps %ymm0, %ymm1, %ymm2 +vxorps (%rax), %ymm1, %ymm2 + +vzeroall +vzeroupper + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 vaddpd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 9 1.00 * vaddpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vaddpd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 1.00 * vaddpd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 3 1.00 vaddps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 9 1.00 * vaddps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vaddps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 1.00 * vaddps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 3 1.00 vaddsd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 9 1.00 * vaddsd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vaddss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 9 1.00 * vaddss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vaddsubpd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 9 1.00 * vaddsubpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vaddsubpd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 1.00 * vaddsubpd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 3 1.00 vaddsubps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 9 1.00 * vaddsubps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vaddsubps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 1.00 * vaddsubps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 2 7 1.00 vaesdec %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 3 13 1.00 * vaesdec (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 2 7 1.00 vaesdeclast %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 3 13 1.00 * vaesdeclast (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 2 7 1.00 vaesenc %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 3 13 1.00 * vaesenc (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 2 7 1.00 vaesenclast %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 3 13 1.00 * vaesenclast (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 2 12 2.00 vaesimc %xmm0, %xmm2 +# CHECK-NEXT: 3 18 2.00 * vaesimc (%rax), %xmm2 +# CHECK-NEXT: 1 8 3.67 vaeskeygenassist $22, %xmm0, %xmm2 +# CHECK-NEXT: 1 8 3.33 * vaeskeygenassist $22, (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 vandnpd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 1.00 * vandnpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 vandnpd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 8 1.00 * vandnpd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 1 1.00 vandnps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 1.00 * vandnps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 vandnps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 8 1.00 * vandnps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 1 1.00 vandpd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 1.00 * vandpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 vandpd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 8 1.00 * vandpd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 1 1.00 vandps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 1.00 * vandps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 vandps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 8 1.00 * vandps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 1 0.50 vblendpd $11, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vblendpd $11, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vblendpd $11, %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 8 0.50 * vblendpd $11, (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 1 0.50 vblendps $11, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vblendps $11, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vblendps $11, %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 8 0.50 * vblendps $11, (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 2 2 1.00 vblendvpd %xmm3, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 3 8 1.00 * vblendvpd %xmm3, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 2 2 1.00 vblendvpd %ymm3, %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 3 9 1.00 * vblendvpd %ymm3, (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 2 2 1.00 vblendvps %xmm3, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 3 8 1.00 * vblendvps %xmm3, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 2 2 1.00 vblendvps %ymm3, %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 3 9 1.00 * vblendvps %ymm3, (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 2 7 1.00 * vbroadcastf128 (%rax), %ymm2 +# CHECK-NEXT: 1 7 0.50 * vbroadcastsd (%rax), %ymm2 +# CHECK-NEXT: 1 6 0.50 * vbroadcastss (%rax), %xmm2 +# CHECK-NEXT: 1 7 0.50 * vbroadcastss (%rax), %ymm2 +# CHECK-NEXT: 1 3 1.00 vcmppd $0, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 9 1.00 * vcmppd $0, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vcmppd $0, %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 1.00 * vcmppd $0, (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 3 1.00 vcmpps $0, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 9 1.00 * vcmpps $0, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vcmpps $0, %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 1.00 * vcmpps $0, (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 3 1.00 vcmpsd $0, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 9 1.00 * vcmpsd $0, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vcmpss $0, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 9 1.00 * vcmpss $0, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 2 2 1.00 vcomisd %xmm0, %xmm1 +# CHECK-NEXT: 3 8 1.00 * vcomisd (%rax), %xmm1 +# CHECK-NEXT: 2 2 1.00 vcomiss %xmm0, %xmm1 +# CHECK-NEXT: 3 8 1.00 * vcomiss (%rax), %xmm1 +# CHECK-NEXT: 2 4 1.00 vcvtdq2pd %xmm0, %xmm2 +# CHECK-NEXT: 3 10 1.00 * vcvtdq2pd (%rax), %xmm2 +# CHECK-NEXT: 2 4 1.00 vcvtdq2pd %xmm0, %ymm2 +# CHECK-NEXT: 3 10 1.00 * vcvtdq2pd (%rax), %ymm2 +# CHECK-NEXT: 1 3 1.00 vcvtdq2ps %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * vcvtdq2ps (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 vcvtdq2ps %ymm0, %ymm2 +# CHECK-NEXT: 2 10 1.00 * vcvtdq2ps (%rax), %ymm2 +# CHECK-NEXT: 2 4 1.00 vcvtpd2dq %xmm0, %xmm2 +# CHECK-NEXT: 3 10 1.00 * vcvtpd2dqx (%rax), %xmm2 +# CHECK-NEXT: 2 4 1.00 vcvtpd2dq %ymm0, %xmm2 +# CHECK-NEXT: 3 11 1.00 * vcvtpd2dqy (%rax), %xmm2 +# CHECK-NEXT: 2 4 1.00 vcvtpd2ps %xmm0, %xmm2 +# CHECK-NEXT: 3 10 1.00 * vcvtpd2psx (%rax), %xmm2 +# CHECK-NEXT: 2 4 1.00 vcvtpd2ps %ymm0, %xmm2 +# CHECK-NEXT: 3 11 1.00 * vcvtpd2psy (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 vcvtps2dq %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * vcvtps2dq (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 vcvtps2dq %ymm0, %ymm2 +# CHECK-NEXT: 2 10 1.00 * vcvtps2dq (%rax), %ymm2 +# CHECK-NEXT: 2 2 1.00 vcvtps2pd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * vcvtps2pd (%rax), %xmm2 +# CHECK-NEXT: 2 2 1.00 vcvtps2pd %xmm0, %ymm2 +# CHECK-NEXT: 2 7 1.00 * vcvtps2pd (%rax), %ymm2 +# CHECK-NEXT: 2 5 1.00 vcvtsd2si %xmm0, %ecx +# CHECK-NEXT: 2 5 1.00 vcvtsd2si %xmm0, %rcx +# CHECK-NEXT: 3 10 1.00 * vcvtsd2si (%rax), %ecx +# CHECK-NEXT: 3 10 1.00 * vcvtsd2si (%rax), %rcx +# CHECK-NEXT: 2 4 1.00 vcvtsd2ss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 3 10 1.00 * vcvtsd2ss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 2 4 1.00 vcvtsi2sdl %ecx, %xmm0, %xmm2 +# CHECK-NEXT: 2 4 1.00 vcvtsi2sdq %rcx, %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * vcvtsi2sdl (%rax), %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * vcvtsi2sdq (%rax), %xmm0, %xmm2 +# CHECK-NEXT: 3 5 2.00 vcvtsi2ssl %ecx, %xmm0, %xmm2 +# CHECK-NEXT: 3 5 2.00 vcvtsi2ssq %rcx, %xmm0, %xmm2 +# CHECK-NEXT: 3 10 1.00 * vcvtsi2ssl (%rax), %xmm0, %xmm2 +# CHECK-NEXT: 3 10 1.00 * vcvtsi2ssq (%rax), %xmm0, %xmm2 +# CHECK-NEXT: 1 1 1.00 vcvtss2sd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 1.00 * vcvtss2sd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 2 5 1.00 vcvtss2si %xmm0, %ecx +# CHECK-NEXT: 2 5 1.00 vcvtss2si %xmm0, %rcx +# CHECK-NEXT: 3 10 1.00 * vcvtss2si (%rax), %ecx +# CHECK-NEXT: 3 10 1.00 * vcvtss2si (%rax), %rcx +# CHECK-NEXT: 2 4 1.00 vcvttpd2dq %xmm0, %xmm2 +# CHECK-NEXT: 3 10 1.00 * vcvttpd2dqx (%rax), %xmm2 +# CHECK-NEXT: 2 4 1.00 vcvttpd2dq %ymm0, %xmm2 +# CHECK-NEXT: 3 11 1.00 * vcvttpd2dqy (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 vcvttps2dq %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * vcvttps2dq (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 vcvttps2dq %ymm0, %ymm2 +# CHECK-NEXT: 2 10 1.00 * vcvttps2dq (%rax), %ymm2 +# CHECK-NEXT: 2 5 1.00 vcvttsd2si %xmm0, %ecx +# CHECK-NEXT: 2 5 1.00 vcvttsd2si %xmm0, %rcx +# CHECK-NEXT: 3 10 1.00 * vcvttsd2si (%rax), %ecx +# CHECK-NEXT: 3 10 1.00 * vcvttsd2si (%rax), %rcx +# CHECK-NEXT: 2 5 1.00 vcvttss2si %xmm0, %ecx +# CHECK-NEXT: 2 5 1.00 vcvttss2si %xmm0, %rcx +# CHECK-NEXT: 3 10 1.00 * vcvttss2si (%rax), %ecx +# CHECK-NEXT: 3 10 1.00 * vcvttss2si (%rax), %rcx +# CHECK-NEXT: 1 22 22.00 vdivpd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 28 22.00 * vdivpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 3 45 44.00 vdivpd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 4 52 44.00 * vdivpd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 14 14.00 vdivps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 20 14.00 * vdivps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 3 29 28.00 vdivps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 4 36 28.00 * vdivps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 22 22.00 vdivsd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 28 22.00 * vdivsd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 14 14.00 vdivss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 20 14.00 * vdivss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 3 9 1.00 vdppd $22, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 4 15 1.00 * vdppd $22, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 4 12 2.00 vdpps $22, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 5 18 2.00 * vdpps $22, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 4 12 2.00 vdpps $22, %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 5 19 2.00 * vdpps $22, (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 1 1.00 vextractf128 $1, %ymm0, %xmm2 +# CHECK-NEXT: 1 1 1.00 * vextractf128 $1, %ymm0, (%rax) +# CHECK-NEXT: 2 3 1.00 vextractps $1, %xmm0, %ecx +# CHECK-NEXT: 3 5 1.00 * vextractps $1, %xmm0, (%rax) +# CHECK-NEXT: 3 5 2.00 vhaddpd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 4 11 2.00 * vhaddpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 3 5 2.00 vhaddpd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 4 12 2.00 * vhaddpd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 3 5 2.00 vhaddps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 4 11 2.00 * vhaddps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 3 5 2.00 vhaddps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 4 12 2.00 * vhaddps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 3 5 2.00 vhsubpd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 4 11 2.00 * vhsubpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 3 5 2.00 vhsubpd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 4 12 2.00 * vhsubpd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 3 5 2.00 vhsubps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 4 11 2.00 * vhsubps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 3 5 2.00 vhsubps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 4 12 2.00 * vhsubps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 1 1.00 vinsertf128 $1, %xmm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 7 0.50 * vinsertf128 $1, (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 1 1.00 vinsertps $1, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 1.00 * vinsertps $1, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 6 0.50 * vlddqu (%rax), %xmm2 +# CHECK-NEXT: 1 7 0.50 * vlddqu (%rax), %ymm2 +# CHECK-NEXT: 4 5 1.00 * * U vldmxcsr (%rax) +# CHECK-NEXT: 1 1 1.00 * * U vmaskmovdqu %xmm0, %xmm1 +# CHECK-NEXT: 3 8 1.00 * vmaskmovpd (%rax), %xmm0, %xmm2 +# CHECK-NEXT: 3 9 1.00 * vmaskmovpd (%rax), %ymm0, %ymm2 +# CHECK-NEXT: 3 5 1.00 * * vmaskmovpd %xmm0, %xmm1, (%rax) +# CHECK-NEXT: 3 5 1.00 * * vmaskmovpd %ymm0, %ymm1, (%rax) +# CHECK-NEXT: 3 8 1.00 * vmaskmovps (%rax), %xmm0, %xmm2 +# CHECK-NEXT: 3 9 1.00 * vmaskmovps (%rax), %ymm0, %ymm2 +# CHECK-NEXT: 3 5 1.00 * * vmaskmovps %xmm0, %xmm1, (%rax) +# CHECK-NEXT: 3 5 1.00 * * vmaskmovps %ymm0, %ymm1, (%rax) +# CHECK-NEXT: 1 3 1.00 vmaxpd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 9 1.00 * vmaxpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vmaxpd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 1.00 * vmaxpd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 3 1.00 vmaxps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 9 1.00 * vmaxps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vmaxps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 1.00 * vmaxps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 3 1.00 vmaxsd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 9 1.00 * vmaxsd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vmaxss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 9 1.00 * vmaxss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vminpd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 9 1.00 * vminpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vminpd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 1.00 * vminpd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 3 1.00 vminps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 9 1.00 * vminps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vminps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 1.00 * vminps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 3 1.00 vminsd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 9 1.00 * vminsd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vminss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 9 1.00 * vminss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 vmovapd %xmm0, %xmm2 +# CHECK-NEXT: 1 1 1.00 * vmovapd %xmm0, (%rax) +# CHECK-NEXT: 1 6 0.50 * vmovapd (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 vmovapd %ymm0, %ymm2 +# CHECK-NEXT: 1 1 1.00 * vmovapd %ymm0, (%rax) +# CHECK-NEXT: 1 7 0.50 * vmovapd (%rax), %ymm2 +# CHECK-NEXT: 1 1 1.00 vmovaps %xmm0, %xmm2 +# CHECK-NEXT: 1 1 1.00 * vmovaps %xmm0, (%rax) +# CHECK-NEXT: 1 6 0.50 * vmovaps (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 vmovaps %ymm0, %ymm2 +# CHECK-NEXT: 1 1 1.00 * vmovaps %ymm0, (%rax) +# CHECK-NEXT: 1 7 0.50 * vmovaps (%rax), %ymm2 +# CHECK-NEXT: 1 1 1.00 vmovd %eax, %xmm2 +# CHECK-NEXT: 1 6 0.50 * vmovd (%rax), %xmm2 +# CHECK-NEXT: 1 2 1.00 vmovd %xmm0, %ecx +# CHECK-NEXT: 1 1 1.00 * vmovd %xmm0, (%rax) +# CHECK-NEXT: 1 1 1.00 vmovddup %xmm0, %xmm2 +# CHECK-NEXT: 1 6 0.50 * vmovddup (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 vmovddup %ymm0, %ymm2 +# CHECK-NEXT: 1 7 0.50 * vmovddup (%rax), %ymm2 +# CHECK-NEXT: 1 1 0.33 vmovdqa %xmm0, %xmm2 +# CHECK-NEXT: 1 1 1.00 * vmovdqa %xmm0, (%rax) +# CHECK-NEXT: 1 6 0.50 * vmovdqa (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 vmovdqa %ymm0, %ymm2 +# CHECK-NEXT: 1 1 1.00 * vmovdqa %ymm0, (%rax) +# CHECK-NEXT: 1 7 0.50 * vmovdqa (%rax), %ymm2 +# CHECK-NEXT: 1 1 0.33 vmovdqu %xmm0, %xmm2 +# CHECK-NEXT: 1 1 1.00 * vmovdqu %xmm0, (%rax) +# CHECK-NEXT: 1 6 0.50 * vmovdqu (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 vmovdqu %ymm0, %ymm2 +# CHECK-NEXT: 1 1 1.00 * vmovdqu %ymm0, (%rax) +# CHECK-NEXT: 1 7 0.50 * vmovdqu (%rax), %ymm2 +# CHECK-NEXT: 1 1 1.00 vmovhlps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 vmovlhps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 * vmovhpd %xmm0, (%rax) +# CHECK-NEXT: 2 7 1.00 * vmovhpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 * vmovhps %xmm0, (%rax) +# CHECK-NEXT: 2 7 1.00 * vmovhps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 * vmovlpd %xmm0, (%rax) +# CHECK-NEXT: 2 7 1.00 * vmovlpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 * vmovlps %xmm0, (%rax) +# CHECK-NEXT: 2 7 1.00 * vmovlps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 2 1.00 vmovmskpd %xmm0, %ecx +# CHECK-NEXT: 1 2 1.00 vmovmskpd %ymm0, %ecx +# CHECK-NEXT: 1 2 1.00 vmovmskps %xmm0, %ecx +# CHECK-NEXT: 1 2 1.00 vmovmskps %ymm0, %ecx +# CHECK-NEXT: 1 1 1.00 * vmovntdq %xmm0, (%rax) +# CHECK-NEXT: 1 1 1.00 * vmovntdq %ymm0, (%rax) +# CHECK-NEXT: 1 6 0.50 * vmovntdqa (%rax), %xmm2 +# CHECK-NEXT: 1 7 0.50 * vmovntdqa (%rax), %ymm2 +# CHECK-NEXT: 1 1 1.00 * vmovntpd %xmm0, (%rax) +# CHECK-NEXT: 1 1 1.00 * vmovntpd %ymm0, (%rax) +# CHECK-NEXT: 1 1 1.00 * vmovntps %xmm0, (%rax) +# CHECK-NEXT: 1 1 1.00 * vmovntps %ymm0, (%rax) +# CHECK-NEXT: 1 1 0.33 vmovq %xmm0, %xmm2 +# CHECK-NEXT: 1 1 1.00 vmovq %rax, %xmm2 +# CHECK-NEXT: 1 6 0.50 * vmovq (%rax), %xmm2 +# CHECK-NEXT: 1 2 1.00 vmovq %xmm0, %rcx +# CHECK-NEXT: 1 1 1.00 * vmovq %xmm0, (%rax) +# CHECK-NEXT: 1 1 1.00 vmovsd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 * vmovsd %xmm0, (%rax) +# CHECK-NEXT: 1 6 0.50 * vmovsd (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 vmovshdup %xmm0, %xmm2 +# CHECK-NEXT: 1 6 0.50 * vmovshdup (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 vmovshdup %ymm0, %ymm2 +# CHECK-NEXT: 1 7 0.50 * vmovshdup (%rax), %ymm2 +# CHECK-NEXT: 1 1 1.00 vmovsldup %xmm0, %xmm2 +# CHECK-NEXT: 1 6 0.50 * vmovsldup (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 vmovsldup %ymm0, %ymm2 +# CHECK-NEXT: 1 7 0.50 * vmovsldup (%rax), %ymm2 +# CHECK-NEXT: 1 1 1.00 vmovss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 * vmovss %xmm0, (%rax) +# CHECK-NEXT: 1 6 0.50 * vmovss (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 vmovupd %xmm0, %xmm2 +# CHECK-NEXT: 1 1 1.00 * vmovupd %xmm0, (%rax) +# CHECK-NEXT: 1 6 0.50 * vmovupd (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 vmovupd %ymm0, %ymm2 +# CHECK-NEXT: 1 1 1.00 * vmovupd %ymm0, (%rax) +# CHECK-NEXT: 1 7 0.50 * vmovupd (%rax), %ymm2 +# CHECK-NEXT: 1 1 1.00 vmovups %xmm0, %xmm2 +# CHECK-NEXT: 1 1 1.00 * vmovups %xmm0, (%rax) +# CHECK-NEXT: 1 6 0.50 * vmovups (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 vmovups %ymm0, %ymm2 +# CHECK-NEXT: 1 1 1.00 * vmovups %ymm0, (%rax) +# CHECK-NEXT: 1 7 0.50 * vmovups (%rax), %ymm2 +# CHECK-NEXT: 3 7 1.00 vmpsadbw $1, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 4 13 1.00 * vmpsadbw $1, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 1.00 vmulpd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 1.00 * vmulpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 1.00 vmulpd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 12 1.00 * vmulpd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 1.00 vmulps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 1.00 * vmulps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 1.00 vmulps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 12 1.00 * vmulps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 1.00 vmulsd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 1.00 * vmulsd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 1.00 vmulss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 1.00 * vmulss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 vorpd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 1.00 * vorpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 vorpd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 8 1.00 * vorpd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 1 1.00 vorps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 1.00 * vorps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 vorps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 8 1.00 * vorps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 1 0.50 vpabsb %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpabsb (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 vpabsd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpabsd (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 vpabsw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpabsw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 vpackssdw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpackssdw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpacksswb %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpacksswb (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpackusdw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpackusdw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpackuswb %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpackuswb (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpaddb %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpaddb (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpaddd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpaddd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpaddq %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpaddq (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpaddsb %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpaddsb (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpaddsw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpaddsw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpaddusb %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpaddusb (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpaddusw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpaddusw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpaddw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpaddw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpalignr $1, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpalignr $1, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.33 vpand %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpand (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.33 vpandn %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpandn (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpavgb %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpavgb (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpavgw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpavgw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 2 2 1.00 vpblendvb %xmm3, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 3 8 1.00 * vpblendvb %xmm3, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpblendw $11, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpblendw $11, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 14 6.00 vpclmulqdq $11, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 1 14 5.67 * vpclmulqdq $11, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpcmpeqb %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpcmpeqb (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpcmpeqd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpcmpeqd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpcmpeqq %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpcmpeqq (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpcmpeqw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpcmpeqw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 4 2.67 vpcmpestri $1, %xmm0, %xmm2 +# CHECK-NEXT: 1 4 2.33 * vpcmpestri $1, (%rax), %xmm2 +# CHECK-NEXT: 1 11 2.67 vpcmpestrm $1, %xmm0, %xmm2 +# CHECK-NEXT: 1 11 2.33 * vpcmpestrm $1, (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 vpcmpgtb %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpcmpgtb (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpcmpgtd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpcmpgtd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 1.00 vpcmpgtq %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 1.00 * vpcmpgtq (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpcmpgtw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpcmpgtw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 3 11 3.00 vpcmpistri $1, %xmm0, %xmm2 +# CHECK-NEXT: 4 17 3.00 * vpcmpistri $1, (%rax), %xmm2 +# CHECK-NEXT: 3 11 3.00 vpcmpistrm $1, %xmm0, %xmm2 +# CHECK-NEXT: 4 17 3.00 * vpcmpistrm $1, (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 vperm2f128 $1, %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 8 1.00 * vperm2f128 $1, (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 1 1.00 vpermilpd $1, %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * vpermilpd $1, (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 vpermilpd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 1.00 * vpermilpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 vpermilpd $1, %ymm0, %ymm2 +# CHECK-NEXT: 2 8 1.00 * vpermilpd $1, (%rax), %ymm2 +# CHECK-NEXT: 1 1 1.00 vpermilpd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 8 1.00 * vpermilpd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 1 1.00 vpermilps $1, %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * vpermilps $1, (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 vpermilps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 1.00 * vpermilps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 vpermilps $1, %ymm0, %ymm2 +# CHECK-NEXT: 2 8 1.00 * vpermilps $1, (%rax), %ymm2 +# CHECK-NEXT: 1 1 1.00 vpermilps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 8 1.00 * vpermilps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 2 3 1.00 vpextrb $1, %xmm0, %ecx +# CHECK-NEXT: 3 5 1.00 * vpextrb $1, %xmm0, (%rax) +# CHECK-NEXT: 2 3 1.00 vpextrd $1, %xmm0, %ecx +# CHECK-NEXT: 4 5 1.00 * vpextrd $1, %xmm0, (%rax) +# CHECK-NEXT: 2 3 1.00 vpextrq $1, %xmm0, %rcx +# CHECK-NEXT: 4 5 1.00 * vpextrq $1, %xmm0, (%rax) +# CHECK-NEXT: 2 3 1.00 vpextrw $1, %xmm0, %ecx +# CHECK-NEXT: 3 5 1.00 * vpextrw $1, %xmm0, (%rax) +# CHECK-NEXT: 3 3 1.50 vphaddd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 4 9 1.50 * vphaddd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 3 3 1.50 vphaddsw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 4 9 1.50 * vphaddsw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 3 3 1.50 vphaddw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 4 9 1.50 * vphaddw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 1.00 vphminposuw %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * vphminposuw (%rax), %xmm2 +# CHECK-NEXT: 3 3 1.50 vphsubd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 4 9 1.50 * vphsubd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 3 3 1.50 vphsubsw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 4 9 1.50 * vphsubsw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 3 3 1.50 vphsubw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 4 9 1.50 * vphsubw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 2 2 1.00 vpinsrb $1, %eax, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpinsrb $1, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 2 2 1.00 vpinsrd $1, %eax, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpinsrd $1, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 2 2 1.00 vpinsrq $1, %rax, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpinsrq $1, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 2 2 1.00 vpinsrw $1, %eax, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpinsrw $1, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 1.00 vpmaddubsw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 1.00 * vpmaddubsw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 1.00 vpmaddwd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 1.00 * vpmaddwd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpmaxsb %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpmaxsb (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpmaxsd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpmaxsd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpmaxsw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpmaxsw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpmaxub %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpmaxub (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpmaxud %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpmaxud (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpmaxuw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpmaxuw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpminsb %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpminsb (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpminsd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpminsd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpminsw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpminsw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpminub %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpminub (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpminud %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpminud (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpminuw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpminuw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 2 1.00 vpmovmskb %xmm0, %ecx +# CHECK-NEXT: 1 1 0.50 vpmovsxbd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpmovsxbd (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 vpmovsxbq %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpmovsxbq (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 vpmovsxbw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpmovsxbw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 vpmovsxdq %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpmovsxdq (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 vpmovsxwd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpmovsxwd (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 vpmovsxwq %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpmovsxwq (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 vpmovzxbd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpmovzxbd (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 vpmovzxbq %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpmovzxbq (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 vpmovzxbw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpmovzxbw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 vpmovzxdq %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpmovzxdq (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 vpmovzxwd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpmovzxwd (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 vpmovzxwq %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpmovzxwq (%rax), %xmm2 +# CHECK-NEXT: 1 5 1.00 vpmuldq %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 1.00 * vpmuldq (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 1.00 vpmulhrsw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 1.00 * vpmulhrsw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 1.00 vpmulhuw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 1.00 * vpmulhuw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 1.00 vpmulhw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 1.00 * vpmulhw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 1.00 vpmulld %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 1.00 * vpmulld (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 1.00 vpmullw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 1.00 * vpmullw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 1.00 vpmuludq %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 1.00 * vpmuludq (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.33 vpor %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpor (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 1.00 vpsadbw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 1.00 * vpsadbw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpshufb %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpshufb (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpshufd $1, %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpshufd $1, (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 vpshufhw $1, %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpshufhw $1, (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 vpshuflw $1, %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpshuflw $1, (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 vpsignb %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpsignb (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpsignd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpsignd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpsignw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpsignw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 vpslld $1, %xmm0, %xmm2 +# CHECK-NEXT: 2 2 1.00 vpslld %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 3 8 1.00 * vpslld (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpslldq $1, %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 vpsllq $1, %xmm0, %xmm2 +# CHECK-NEXT: 2 2 1.00 vpsllq %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 3 8 1.00 * vpsllq (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 vpsllw $1, %xmm0, %xmm2 +# CHECK-NEXT: 2 2 1.00 vpsllw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 3 8 1.00 * vpsllw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 vpsrad $1, %xmm0, %xmm2 +# CHECK-NEXT: 2 2 1.00 vpsrad %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 3 8 1.00 * vpsrad (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 vpsraw $1, %xmm0, %xmm2 +# CHECK-NEXT: 2 2 1.00 vpsraw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 3 8 1.00 * vpsraw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 vpsrld $1, %xmm0, %xmm2 +# CHECK-NEXT: 2 2 1.00 vpsrld %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 3 8 1.00 * vpsrld (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpsrldq $1, %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 vpsrlq $1, %xmm0, %xmm2 +# CHECK-NEXT: 2 2 1.00 vpsrlq %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 3 8 1.00 * vpsrlq (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 vpsrlw $1, %xmm0, %xmm2 +# CHECK-NEXT: 2 2 1.00 vpsrlw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 3 8 1.00 * vpsrlw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpsubb %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpsubb (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpsubd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpsubd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpsubq %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpsubq (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpsubsb %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpsubsb (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpsubsw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpsubsw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpsubusb %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpsubusb (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpsubusw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpsubusw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpsubw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpsubw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 2 2 1.00 vptest %xmm0, %xmm1 +# CHECK-NEXT: 3 8 1.00 * vptest (%rax), %xmm1 +# CHECK-NEXT: 2 2 1.00 vptest %ymm0, %ymm1 +# CHECK-NEXT: 3 9 1.00 * vptest (%rax), %ymm1 +# CHECK-NEXT: 1 1 0.50 vpunpckhbw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpunpckhbw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpunpckhdq %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpunpckhdq (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpunpckhqdq %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpunpckhqdq (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpunpckhwd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpunpckhwd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpunpcklbw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpunpcklbw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpunpckldq %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpunpckldq (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpunpcklqdq %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpunpcklqdq (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpunpcklwd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpunpcklwd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 0.33 vpxor %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 0.50 * vpxor (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 1.00 vrcpps %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * vrcpps (%rax), %xmm2 +# CHECK-NEXT: 3 7 2.00 vrcpps %ymm0, %ymm2 +# CHECK-NEXT: 4 14 2.00 * vrcpps (%rax), %ymm2 +# CHECK-NEXT: 1 5 1.00 vrcpss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 1.00 * vrcpss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vroundpd $1, %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * vroundpd $1, (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 vroundpd $1, %ymm0, %ymm2 +# CHECK-NEXT: 2 10 1.00 * vroundpd $1, (%rax), %ymm2 +# CHECK-NEXT: 1 3 1.00 vroundps $1, %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * vroundps $1, (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 vroundps $1, %ymm0, %ymm2 +# CHECK-NEXT: 2 10 1.00 * vroundps $1, (%rax), %ymm2 +# CHECK-NEXT: 1 3 1.00 vroundsd $1, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 9 1.00 * vroundsd $1, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vroundss $1, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 9 1.00 * vroundss $1, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 1.00 vrsqrtps %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * vrsqrtps (%rax), %xmm2 +# CHECK-NEXT: 3 7 2.00 vrsqrtps %ymm0, %ymm2 +# CHECK-NEXT: 4 14 2.00 * vrsqrtps (%rax), %ymm2 +# CHECK-NEXT: 1 5 1.00 vrsqrtss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 1.00 * vrsqrtss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 vshufpd $1, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 1.00 * vshufpd $1, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 vshufpd $1, %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 8 1.00 * vshufpd $1, (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 1 1.00 vshufps $1, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 1.00 * vshufps $1, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 vshufps $1, %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 8 1.00 * vshufps $1, (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 21 21.00 vsqrtpd %xmm0, %xmm2 +# CHECK-NEXT: 2 27 21.00 * vsqrtpd (%rax), %xmm2 +# CHECK-NEXT: 3 45 44.00 vsqrtpd %ymm0, %ymm2 +# CHECK-NEXT: 4 52 44.00 * vsqrtpd (%rax), %ymm2 +# CHECK-NEXT: 1 14 14.00 vsqrtps %xmm0, %xmm2 +# CHECK-NEXT: 2 20 14.00 * vsqrtps (%rax), %xmm2 +# CHECK-NEXT: 3 29 28.00 vsqrtps %ymm0, %ymm2 +# CHECK-NEXT: 4 36 28.00 * vsqrtps (%rax), %ymm2 +# CHECK-NEXT: 1 21 21.00 vsqrtsd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 27 21.00 * vsqrtsd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 14 14.00 vsqrtss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 20 14.00 * vsqrtss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 4 5 1.00 * * U vstmxcsr (%rax) +# CHECK-NEXT: 1 3 1.00 vsubpd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 9 1.00 * vsubpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vsubpd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 1.00 * vsubpd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 3 1.00 vsubps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 9 1.00 * vsubps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vsubps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 1.00 * vsubps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 3 1.00 vsubsd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 9 1.00 * vsubsd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.00 vsubss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 9 1.00 * vsubss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 vtestpd %xmm0, %xmm1 +# CHECK-NEXT: 2 7 1.00 * vtestpd (%rax), %xmm1 +# CHECK-NEXT: 1 1 1.00 vtestpd %ymm0, %ymm1 +# CHECK-NEXT: 2 8 1.00 * vtestpd (%rax), %ymm1 +# CHECK-NEXT: 1 1 1.00 vtestps %xmm0, %xmm1 +# CHECK-NEXT: 2 7 1.00 * vtestps (%rax), %xmm1 +# CHECK-NEXT: 1 1 1.00 vtestps %ymm0, %ymm1 +# CHECK-NEXT: 2 8 1.00 * vtestps (%rax), %ymm1 +# CHECK-NEXT: 2 2 1.00 vucomisd %xmm0, %xmm1 +# CHECK-NEXT: 3 8 1.00 * vucomisd (%rax), %xmm1 +# CHECK-NEXT: 2 2 1.00 vucomiss %xmm0, %xmm1 +# CHECK-NEXT: 3 8 1.00 * vucomiss (%rax), %xmm1 +# CHECK-NEXT: 1 1 1.00 vunpckhpd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 1.00 * vunpckhpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 vunpckhpd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 8 1.00 * vunpckhpd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 1 1.00 vunpckhps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 1.00 * vunpckhps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 vunpckhps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 8 1.00 * vunpckhps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 1 1.00 vunpcklpd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 1.00 * vunpcklpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 vunpcklpd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 8 1.00 * vunpcklpd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 1 1.00 vunpcklps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 1.00 * vunpcklps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 vunpcklps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 8 1.00 * vunpcklps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 1 1.00 vxorpd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 1.00 * vxorpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 vxorpd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 8 1.00 * vxorpd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 1 1.00 vxorps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 7 1.00 * vxorps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 1 1.00 vxorps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 8 1.00 * vxorps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 20 9 2.00 * * U vzeroall +# CHECK-NEXT: 1 100 0.33 * * U vzeroupper + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - 572.00 246.83 317.33 39.00 365.83 179.50 179.50 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - - - - vaddpd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vaddpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - vaddpd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vaddpd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - 1.00 - - - - vaddps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vaddps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - vaddps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vaddps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - 1.00 - - - - vaddsd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vaddsd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - vaddss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vaddss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - vaddsubpd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vaddsubpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - vaddsubpd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vaddsubpd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - 1.00 - - - - vaddsubps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vaddsubps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - vaddsubps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vaddsubps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.33 0.33 - 1.33 - - vaesdec %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 1.33 0.50 0.50 vaesdec (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 1.33 - - vaesdeclast %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 1.33 0.50 0.50 vaesdeclast (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 1.33 - - vaesenc %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 1.33 0.50 0.50 vaesenc (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 1.33 - - vaesenclast %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 1.33 0.50 0.50 vaesenclast (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 2.00 - - vaesimc %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 2.00 0.50 0.50 vaesimc (%rax), %xmm2 +# CHECK-NEXT: - - 3.67 3.67 - 3.67 - - vaeskeygenassist $22, %xmm0, %xmm2 +# CHECK-NEXT: - - 3.33 3.33 - 3.33 0.50 0.50 vaeskeygenassist $22, (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vandnpd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vandnpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vandnpd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vandnpd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 - - vandnps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vandnps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vandnps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vandnps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 - - vandpd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vandpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vandpd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vandpd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 - - vandps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vandps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vandps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vandps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 - - 0.50 - - vblendpd $11, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 - - 0.50 0.50 0.50 vblendpd $11, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 - - 0.50 - - vblendpd $11, %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 - - 0.50 0.50 0.50 vblendpd $11, (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 - - 0.50 - - vblendps $11, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 - - 0.50 0.50 0.50 vblendps $11, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 - - 0.50 - - vblendps $11, %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 - - 0.50 0.50 0.50 vblendps $11, (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 1.00 - - 1.00 - - vblendvpd %xmm3, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - 1.00 0.50 0.50 vblendvpd %xmm3, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - 1.00 - - vblendvpd %ymm3, %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 1.00 - - 1.00 0.50 0.50 vblendvpd %ymm3, (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 1.00 - - 1.00 - - vblendvps %xmm3, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - 1.00 0.50 0.50 vblendvps %xmm3, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - 1.00 - - vblendvps %ymm3, %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 1.00 - - 1.00 0.50 0.50 vblendvps %ymm3, (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vbroadcastf128 (%rax), %ymm2 +# CHECK-NEXT: - - - - - - 0.50 0.50 vbroadcastsd (%rax), %ymm2 +# CHECK-NEXT: - - - - - - 0.50 0.50 vbroadcastss (%rax), %xmm2 +# CHECK-NEXT: - - - - - - 0.50 0.50 vbroadcastss (%rax), %ymm2 +# CHECK-NEXT: - - - 1.00 - - - - vcmppd $0, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vcmppd $0, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - vcmppd $0, %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vcmppd $0, (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - 1.00 - - - - vcmpps $0, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vcmpps $0, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - vcmpps $0, %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vcmpps $0, (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - 1.00 - - - - vcmpsd $0, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vcmpsd $0, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - vcmpss $0, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vcmpss $0, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 1.00 - - - - vcomisd %xmm0, %xmm1 +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 vcomisd (%rax), %xmm1 +# CHECK-NEXT: - - 1.00 1.00 - - - - vcomiss %xmm0, %xmm1 +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 vcomiss (%rax), %xmm1 +# CHECK-NEXT: - - - 1.00 - 1.00 - - vcvtdq2pd %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 vcvtdq2pd (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 - - vcvtdq2pd %xmm0, %ymm2 +# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 vcvtdq2pd (%rax), %ymm2 +# CHECK-NEXT: - - - 1.00 - - - - vcvtdq2ps %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vcvtdq2ps (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - vcvtdq2ps %ymm0, %ymm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vcvtdq2ps (%rax), %ymm2 +# CHECK-NEXT: - - - 1.00 - 1.00 - - vcvtpd2dq %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 vcvtpd2dqx (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 - - vcvtpd2dq %ymm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 vcvtpd2dqy (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 - - vcvtpd2ps %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 vcvtpd2psx (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 - - vcvtpd2ps %ymm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 vcvtpd2psy (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - vcvtps2dq %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vcvtps2dq (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - vcvtps2dq %ymm0, %ymm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vcvtps2dq (%rax), %ymm2 +# CHECK-NEXT: - - 1.00 - - 1.00 - - vcvtps2pd %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vcvtps2pd (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - 1.00 - - vcvtps2pd %xmm0, %ymm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vcvtps2pd (%rax), %ymm2 +# CHECK-NEXT: - - 1.00 1.00 - - - - vcvtsd2si %xmm0, %ecx +# CHECK-NEXT: - - 1.00 1.00 - - - - vcvtsd2si %xmm0, %rcx +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 vcvtsd2si (%rax), %ecx +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 vcvtsd2si (%rax), %rcx +# CHECK-NEXT: - - - 1.00 - 1.00 - - vcvtsd2ss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 vcvtsd2ss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 - - vcvtsi2sdl %ecx, %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 - - vcvtsi2sdq %rcx, %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vcvtsi2sdl (%rax), %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vcvtsi2sdq (%rax), %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - 2.00 - - vcvtsi2ssl %ecx, %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - 2.00 - - vcvtsi2ssq %rcx, %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 vcvtsi2ssl (%rax), %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 vcvtsi2ssq (%rax), %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - vcvtss2sd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vcvtss2sd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 1.00 - - - - vcvtss2si %xmm0, %ecx +# CHECK-NEXT: - - 1.00 1.00 - - - - vcvtss2si %xmm0, %rcx +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 vcvtss2si (%rax), %ecx +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 vcvtss2si (%rax), %rcx +# CHECK-NEXT: - - - 1.00 - 1.00 - - vcvttpd2dq %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 vcvttpd2dqx (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 - - vcvttpd2dq %ymm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 vcvttpd2dqy (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - vcvttps2dq %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vcvttps2dq (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - vcvttps2dq %ymm0, %ymm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vcvttps2dq (%rax), %ymm2 +# CHECK-NEXT: - - 1.00 1.00 - - - - vcvttsd2si %xmm0, %ecx +# CHECK-NEXT: - - 1.00 1.00 - - - - vcvttsd2si %xmm0, %rcx +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 vcvttsd2si (%rax), %ecx +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 vcvttsd2si (%rax), %rcx +# CHECK-NEXT: - - 1.00 1.00 - - - - vcvttss2si %xmm0, %ecx +# CHECK-NEXT: - - 1.00 1.00 - - - - vcvttss2si %xmm0, %rcx +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 vcvttss2si (%rax), %ecx +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 vcvttss2si (%rax), %rcx +# CHECK-NEXT: - 22.00 1.00 - - - - - vdivpd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - 22.00 1.00 - - - 0.50 0.50 vdivpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - 44.00 2.50 - - 0.50 - - vdivpd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - 44.00 2.50 - - 0.50 0.50 0.50 vdivpd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - 14.00 1.00 - - - - - vdivps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - 14.00 1.00 - - - 0.50 0.50 vdivps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - 28.00 2.50 - - 0.50 - - vdivps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - 28.00 2.50 - - 0.50 0.50 0.50 vdivps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - 22.00 1.00 - - - - - vdivsd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - 22.00 1.00 - - - 0.50 0.50 vdivsd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - 14.00 1.00 - - - - - vdivss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - 14.00 1.00 - - - 0.50 0.50 vdivss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - vdppd $22, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 1.00 - 1.00 0.50 0.50 vdppd $22, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 2.00 - 1.00 - - vdpps $22, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 2.00 - 1.00 0.50 0.50 vdpps $22, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 2.00 - 1.00 - - vdpps $22, %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 1.00 2.00 - 1.00 0.50 0.50 vdpps $22, (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 - - vextractf128 $1, %ymm0, %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 vextractf128 $1, %ymm0, (%rax) +# CHECK-NEXT: - - 1.00 - - 1.00 - - vextractps $1, %xmm0, %ecx +# CHECK-NEXT: - - - - 1.00 1.00 0.50 0.50 vextractps $1, %xmm0, (%rax) +# CHECK-NEXT: - - - 1.00 - 2.00 - - vhaddpd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - 2.00 0.50 0.50 vhaddpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - 2.00 - - vhaddpd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - 1.00 - 2.00 0.50 0.50 vhaddpd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - 1.00 - 2.00 - - vhaddps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - 2.00 0.50 0.50 vhaddps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - 2.00 - - vhaddps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - 1.00 - 2.00 0.50 0.50 vhaddps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - 1.00 - 2.00 - - vhsubpd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - 2.00 0.50 0.50 vhsubpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - 2.00 - - vhsubpd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - 1.00 - 2.00 0.50 0.50 vhsubpd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - 1.00 - 2.00 - - vhsubps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - 2.00 0.50 0.50 vhsubps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - 2.00 - - vhsubps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - 1.00 - 2.00 0.50 0.50 vhsubps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 - - vinsertf128 $1, %xmm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 - - 0.50 0.50 0.50 vinsertf128 $1, (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 - - vinsertps $1, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vinsertps $1, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - - - - 0.50 0.50 vlddqu (%rax), %xmm2 +# CHECK-NEXT: - - - - - - 0.50 0.50 vlddqu (%rax), %ymm2 +# CHECK-NEXT: - - 1.00 - 1.00 1.00 0.50 0.50 vldmxcsr (%rax) +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 vmaskmovdqu %xmm0, %xmm1 +# CHECK-NEXT: - - 1.00 - - 1.00 0.50 0.50 vmaskmovpd (%rax), %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - 1.00 0.50 0.50 vmaskmovpd (%rax), %ymm0, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 1.00 - 0.50 0.50 vmaskmovpd %xmm0, %xmm1, (%rax) +# CHECK-NEXT: - - 0.50 0.50 1.00 - 0.50 0.50 vmaskmovpd %ymm0, %ymm1, (%rax) +# CHECK-NEXT: - - 1.00 - - 1.00 0.50 0.50 vmaskmovps (%rax), %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - 1.00 0.50 0.50 vmaskmovps (%rax), %ymm0, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 1.00 - 0.50 0.50 vmaskmovps %xmm0, %xmm1, (%rax) +# CHECK-NEXT: - - 0.50 0.50 1.00 - 0.50 0.50 vmaskmovps %ymm0, %ymm1, (%rax) +# CHECK-NEXT: - - - 1.00 - - - - vmaxpd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vmaxpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - vmaxpd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vmaxpd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - 1.00 - - - - vmaxps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vmaxps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - vmaxps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vmaxps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - 1.00 - - - - vmaxsd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vmaxsd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - vmaxss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vmaxss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - vminpd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vminpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - vminpd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vminpd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - 1.00 - - - - vminps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vminps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - vminps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vminps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - 1.00 - - - - vminsd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vminsd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - vminss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vminss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vmovapd %xmm0, %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 vmovapd %xmm0, (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 vmovapd (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vmovapd %ymm0, %ymm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 vmovapd %ymm0, (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 vmovapd (%rax), %ymm2 +# CHECK-NEXT: - - - - - 1.00 - - vmovaps %xmm0, %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 vmovaps %xmm0, (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 vmovaps (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vmovaps %ymm0, %ymm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 vmovaps %ymm0, (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 vmovaps (%rax), %ymm2 +# CHECK-NEXT: - - - - - 1.00 - - vmovd %eax, %xmm2 +# CHECK-NEXT: - - - - - - 0.50 0.50 vmovd (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - vmovd %xmm0, %ecx +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 vmovd %xmm0, (%rax) +# CHECK-NEXT: - - - - - 1.00 - - vmovddup %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - 0.50 0.50 vmovddup (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vmovddup %ymm0, %ymm2 +# CHECK-NEXT: - - - - - - 0.50 0.50 vmovddup (%rax), %ymm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - vmovdqa %xmm0, %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 vmovdqa %xmm0, (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 vmovdqa (%rax), %xmm2 +# CHECK-NEXT: - - 0.50 - - 0.50 - - vmovdqa %ymm0, %ymm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 vmovdqa %ymm0, (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 vmovdqa (%rax), %ymm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - vmovdqu %xmm0, %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 vmovdqu %xmm0, (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 vmovdqu (%rax), %xmm2 +# CHECK-NEXT: - - 0.50 - - 0.50 - - vmovdqu %ymm0, %ymm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 vmovdqu %ymm0, (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 vmovdqu (%rax), %ymm2 +# CHECK-NEXT: - - - - - 1.00 - - vmovhlps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vmovlhps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 vmovhpd %xmm0, (%rax) +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vmovhpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 vmovhps %xmm0, (%rax) +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vmovhps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 vmovlpd %xmm0, (%rax) +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vmovlpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 vmovlps %xmm0, (%rax) +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vmovlps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - vmovmskpd %xmm0, %ecx +# CHECK-NEXT: - - 1.00 - - - - - vmovmskpd %ymm0, %ecx +# CHECK-NEXT: - - 1.00 - - - - - vmovmskps %xmm0, %ecx +# CHECK-NEXT: - - 1.00 - - - - - vmovmskps %ymm0, %ecx +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 vmovntdq %xmm0, (%rax) +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 vmovntdq %ymm0, (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 vmovntdqa (%rax), %xmm2 +# CHECK-NEXT: - - - - - - 0.50 0.50 vmovntdqa (%rax), %ymm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 vmovntpd %xmm0, (%rax) +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 vmovntpd %ymm0, (%rax) +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 vmovntps %xmm0, (%rax) +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 vmovntps %ymm0, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - vmovq %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vmovq %rax, %xmm2 +# CHECK-NEXT: - - - - - - 0.50 0.50 vmovq (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - vmovq %xmm0, %rcx +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 vmovq %xmm0, (%rax) +# CHECK-NEXT: - - - - - 1.00 - - vmovsd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 vmovsd %xmm0, (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 vmovsd (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vmovshdup %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - 0.50 0.50 vmovshdup (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vmovshdup %ymm0, %ymm2 +# CHECK-NEXT: - - - - - - 0.50 0.50 vmovshdup (%rax), %ymm2 +# CHECK-NEXT: - - - - - 1.00 - - vmovsldup %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - 0.50 0.50 vmovsldup (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vmovsldup %ymm0, %ymm2 +# CHECK-NEXT: - - - - - - 0.50 0.50 vmovsldup (%rax), %ymm2 +# CHECK-NEXT: - - - - - 1.00 - - vmovss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 vmovss %xmm0, (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 vmovss (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vmovupd %xmm0, %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 vmovupd %xmm0, (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 vmovupd (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vmovupd %ymm0, %ymm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 vmovupd %ymm0, (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 vmovupd (%rax), %ymm2 +# CHECK-NEXT: - - - - - 1.00 - - vmovups %xmm0, %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 vmovups %xmm0, (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 vmovups (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vmovups %ymm0, %ymm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 vmovups %ymm0, (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 vmovups (%rax), %ymm2 +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - vmpsadbw $1, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 1.00 - 1.00 0.50 0.50 vmpsadbw $1, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - vmulpd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vmulpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - vmulpd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vmulpd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 1.00 - - - - - vmulps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vmulps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - vmulps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vmulps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 1.00 - - - - - vmulsd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vmulsd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - vmulss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vmulss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vorpd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vorpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vorpd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vorpd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 - - vorps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vorps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vorps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vorps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpabsb %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpabsb (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpabsd %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpabsd (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpabsw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpabsw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpackssdw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpackssdw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpacksswb %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpacksswb (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpackusdw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpackusdw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpackuswb %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpackuswb (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpaddb %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpaddb (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpaddd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpaddd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpaddq %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpaddq (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpaddsb %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpaddsb (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpaddsw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpaddsw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpaddusb %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpaddusb (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpaddusw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpaddusw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpaddw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpaddw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpalignr $1, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpalignr $1, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - vpand %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 vpand (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - vpandn %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 vpandn (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpavgb %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpavgb (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpavgw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpavgw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 - - vpblendvb %xmm3, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 vpblendvb %xmm3, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpblendw $11, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpblendw $11, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 6.00 6.00 - 6.00 - - vpclmulqdq $11, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 5.67 5.67 - 5.67 0.50 0.50 vpclmulqdq $11, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpcmpeqb %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpcmpeqb (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpcmpeqd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpcmpeqd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpcmpeqq %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpcmpeqq (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpcmpeqw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpcmpeqw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 2.67 2.67 - 2.67 - - vpcmpestri $1, %xmm0, %xmm2 +# CHECK-NEXT: - - 2.33 2.33 - 2.33 0.50 0.50 vpcmpestri $1, (%rax), %xmm2 +# CHECK-NEXT: - - 2.67 2.67 - 2.67 - - vpcmpestrm $1, %xmm0, %xmm2 +# CHECK-NEXT: - - 2.33 2.33 - 2.33 0.50 0.50 vpcmpestrm $1, (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpcmpgtb %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpcmpgtb (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpcmpgtd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpcmpgtd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - vpcmpgtq %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpcmpgtq (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpcmpgtw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpcmpgtw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 3.00 - - - - - vpcmpistri $1, %xmm0, %xmm2 +# CHECK-NEXT: - - 3.00 - - - 0.50 0.50 vpcmpistri $1, (%rax), %xmm2 +# CHECK-NEXT: - - 3.00 - - - - - vpcmpistrm $1, %xmm0, %xmm2 +# CHECK-NEXT: - - 3.00 - - - 0.50 0.50 vpcmpistrm $1, (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vperm2f128 $1, %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vperm2f128 $1, (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 - - vpermilpd $1, %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vpermilpd $1, (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vpermilpd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vpermilpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vpermilpd $1, %ymm0, %ymm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vpermilpd $1, (%rax), %ymm2 +# CHECK-NEXT: - - - - - 1.00 - - vpermilpd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vpermilpd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 - - vpermilps $1, %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vpermilps $1, (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vpermilps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vpermilps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vpermilps $1, %ymm0, %ymm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vpermilps $1, (%rax), %ymm2 +# CHECK-NEXT: - - - - - 1.00 - - vpermilps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vpermilps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - vpextrb $1, %xmm0, %ecx +# CHECK-NEXT: - - - 0.50 1.00 0.50 0.50 0.50 vpextrb $1, %xmm0, (%rax) +# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - vpextrd $1, %xmm0, %ecx +# CHECK-NEXT: - - 1.00 0.50 1.00 0.50 0.50 0.50 vpextrd $1, %xmm0, (%rax) +# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - vpextrq $1, %xmm0, %rcx +# CHECK-NEXT: - - 1.00 0.50 1.00 0.50 0.50 0.50 vpextrq $1, %xmm0, (%rax) +# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - vpextrw $1, %xmm0, %ecx +# CHECK-NEXT: - - - 0.50 1.00 0.50 0.50 0.50 vpextrw $1, %xmm0, (%rax) +# CHECK-NEXT: - - - 1.50 - 1.50 - - vphaddd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.50 - 1.50 0.50 0.50 vphaddd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.50 - 1.50 - - vphaddsw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.50 - 1.50 0.50 0.50 vphaddsw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.50 - 1.50 - - vphaddw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.50 - 1.50 0.50 0.50 vphaddw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - vphminposuw %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vphminposuw (%rax), %xmm2 +# CHECK-NEXT: - - - 1.50 - 1.50 - - vphsubd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.50 - 1.50 0.50 0.50 vphsubd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.50 - 1.50 - - vphsubsw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.50 - 1.50 0.50 0.50 vphsubsw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.50 - 1.50 - - vphsubw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.50 - 1.50 0.50 0.50 vphsubw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 1.50 - - vpinsrb $1, %eax, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpinsrb $1, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 1.50 - - vpinsrd $1, %eax, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpinsrd $1, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 1.50 - - vpinsrq $1, %rax, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpinsrq $1, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 1.50 - - vpinsrw $1, %eax, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpinsrw $1, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - vpmaddubsw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpmaddubsw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - vpmaddwd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpmaddwd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpmaxsb %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpmaxsb (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpmaxsd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpmaxsd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpmaxsw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpmaxsw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpmaxub %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpmaxub (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpmaxud %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpmaxud (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpmaxuw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpmaxuw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpminsb %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpminsb (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpminsd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpminsd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpminsw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpminsw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpminub %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpminub (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpminud %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpminud (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpminuw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpminuw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - vpmovmskb %xmm0, %ecx +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpmovsxbd %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpmovsxbd (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpmovsxbq %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpmovsxbq (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpmovsxbw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpmovsxbw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpmovsxdq %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpmovsxdq (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpmovsxwd %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpmovsxwd (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpmovsxwq %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpmovsxwq (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpmovzxbd %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpmovzxbd (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpmovzxbq %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpmovzxbq (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpmovzxbw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpmovzxbw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpmovzxdq %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpmovzxdq (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpmovzxwd %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpmovzxwd (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpmovzxwq %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpmovzxwq (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - vpmuldq %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpmuldq (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - vpmulhrsw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpmulhrsw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - vpmulhuw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpmulhuw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - vpmulhw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpmulhw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - vpmulld %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpmulld (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - vpmullw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpmullw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - vpmuludq %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpmuludq (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - vpor %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 vpor (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - vpsadbw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpsadbw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpshufb %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpshufb (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpshufd $1, %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpshufd $1, (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpshufhw $1, %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpshufhw $1, (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpshuflw $1, %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpshuflw $1, (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpsignb %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpsignb (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpsignd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpsignd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpsignw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpsignw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - vpslld $1, %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - vpslld %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 0.50 0.50 vpslld (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpslldq $1, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - vpsllq $1, %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - vpsllq %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 0.50 0.50 vpsllq (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - vpsllw $1, %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - vpsllw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 0.50 0.50 vpsllw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - vpsrad $1, %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - vpsrad %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 0.50 0.50 vpsrad (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - vpsraw $1, %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - vpsraw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 0.50 0.50 vpsraw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - vpsrld $1, %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - vpsrld %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 0.50 0.50 vpsrld (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpsrldq $1, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - vpsrlq $1, %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - vpsrlq %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 0.50 0.50 vpsrlq (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - vpsrlw $1, %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - vpsrlw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 0.50 0.50 vpsrlw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpsubb %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpsubb (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpsubd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpsubd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpsubq %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpsubq (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpsubsb %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpsubsb (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpsubsw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpsubsw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpsubusb %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpsubusb (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpsubusw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpsubusw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpsubw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpsubw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - 1.00 - - vptest %xmm0, %xmm1 +# CHECK-NEXT: - - 1.00 - - 1.00 0.50 0.50 vptest (%rax), %xmm1 +# CHECK-NEXT: - - 1.00 - - 1.00 - - vptest %ymm0, %ymm1 +# CHECK-NEXT: - - 1.00 - - 1.00 0.50 0.50 vptest (%rax), %ymm1 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpunpckhbw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpunpckhbw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpunpckhdq %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpunpckhdq (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpunpckhqdq %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpunpckhqdq (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpunpckhwd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpunpckhwd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpunpcklbw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpunpcklbw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpunpckldq %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpunpckldq (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpunpcklqdq %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpunpcklqdq (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpunpcklwd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpunpcklwd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - vpxor %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 vpxor (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - vrcpps %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vrcpps (%rax), %xmm2 +# CHECK-NEXT: - - 2.50 - - 0.50 - - vrcpps %ymm0, %ymm2 +# CHECK-NEXT: - - 2.50 - - 0.50 0.50 0.50 vrcpps (%rax), %ymm2 +# CHECK-NEXT: - - 1.00 - - - - - vrcpss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vrcpss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - vroundpd $1, %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vroundpd $1, (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - vroundpd $1, %ymm0, %ymm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vroundpd $1, (%rax), %ymm2 +# CHECK-NEXT: - - - 1.00 - - - - vroundps $1, %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vroundps $1, (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - vroundps $1, %ymm0, %ymm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vroundps $1, (%rax), %ymm2 +# CHECK-NEXT: - - - 1.00 - - - - vroundsd $1, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vroundsd $1, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - vroundss $1, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vroundss $1, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - vrsqrtps %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vrsqrtps (%rax), %xmm2 +# CHECK-NEXT: - - 2.50 - - 0.50 - - vrsqrtps %ymm0, %ymm2 +# CHECK-NEXT: - - 2.50 - - 0.50 0.50 0.50 vrsqrtps (%rax), %ymm2 +# CHECK-NEXT: - - 1.00 - - - - - vrsqrtss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vrsqrtss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vshufpd $1, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vshufpd $1, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vshufpd $1, %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vshufpd $1, (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 - - vshufps $1, %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vshufps $1, (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vshufps $1, %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vshufps $1, (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - 21.00 1.00 - - - - - vsqrtpd %xmm0, %xmm2 +# CHECK-NEXT: - 21.00 1.00 - - - 0.50 0.50 vsqrtpd (%rax), %xmm2 +# CHECK-NEXT: - 44.00 2.50 - - 0.50 - - vsqrtpd %ymm0, %ymm2 +# CHECK-NEXT: - 44.00 2.50 - - 0.50 0.50 0.50 vsqrtpd (%rax), %ymm2 +# CHECK-NEXT: - 14.00 1.00 - - - - - vsqrtps %xmm0, %xmm2 +# CHECK-NEXT: - 14.00 1.00 - - - 0.50 0.50 vsqrtps (%rax), %xmm2 +# CHECK-NEXT: - 28.00 2.50 - - 0.50 - - vsqrtps %ymm0, %ymm2 +# CHECK-NEXT: - 28.00 2.50 - - 0.50 0.50 0.50 vsqrtps (%rax), %ymm2 +# CHECK-NEXT: - 21.00 1.00 - - - - - vsqrtsd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - 21.00 1.00 - - - 0.50 0.50 vsqrtsd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - 14.00 1.00 - - - - - vsqrtss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - 14.00 1.00 - - - 0.50 0.50 vsqrtss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - 1.00 1.00 0.50 0.50 vstmxcsr (%rax) +# CHECK-NEXT: - - - 1.00 - - - - vsubpd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vsubpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - vsubpd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vsubpd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - 1.00 - - - - vsubps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vsubps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - vsubps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vsubps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - 1.00 - - - - vsubsd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vsubsd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - vsubss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vsubss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - vtestpd %xmm0, %xmm1 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vtestpd (%rax), %xmm1 +# CHECK-NEXT: - - 1.00 - - - - - vtestpd %ymm0, %ymm1 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vtestpd (%rax), %ymm1 +# CHECK-NEXT: - - 1.00 - - - - - vtestps %xmm0, %xmm1 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vtestps (%rax), %xmm1 +# CHECK-NEXT: - - 1.00 - - - - - vtestps %ymm0, %ymm1 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vtestps (%rax), %ymm1 +# CHECK-NEXT: - - 1.00 1.00 - - - - vucomisd %xmm0, %xmm1 +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 vucomisd (%rax), %xmm1 +# CHECK-NEXT: - - 1.00 1.00 - - - - vucomiss %xmm0, %xmm1 +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 vucomiss (%rax), %xmm1 +# CHECK-NEXT: - - - - - 1.00 - - vunpckhpd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vunpckhpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vunpckhpd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vunpckhpd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 - - vunpckhps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vunpckhps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vunpckhps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vunpckhps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 - - vunpcklpd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vunpcklpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vunpcklpd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vunpcklpd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 - - vunpcklps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vunpcklps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vunpcklps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vunpcklps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 - - vxorpd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vxorpd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vxorpd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vxorpd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 - - vxorps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vxorps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vxorps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vxorps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 2.00 - - vzeroall +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - vzeroupper diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/resources-bmi1.s b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-bmi1.s new file mode 100644 index 00000000000..193f5537c7c --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-bmi1.s @@ -0,0 +1,113 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +andn %eax, %ebx, %ecx +andn (%rax), %ebx, %ecx + +andn %rax, %rbx, %rcx +andn (%rax), %rbx, %rcx + +bextr %eax, %ebx, %ecx +bextr %eax, (%rbx), %ecx + +bextr %rax, %rbx, %rcx +bextr %rax, (%rbx), %rcx + +blsi %eax, %ecx +blsi (%rax), %ecx + +blsi %rax, %rcx +blsi (%rax), %rcx + +blsmsk %eax, %ecx +blsmsk (%rax), %ecx + +blsmsk %rax, %rcx +blsmsk (%rax), %rcx + +blsr %eax, %ecx +blsr (%rax), %ecx + +blsr %rax, %rcx +blsr (%rax), %rcx + +tzcnt %eax, %ecx +tzcnt (%rax), %ecx + +tzcnt %rax, %rcx +tzcnt (%rax), %rcx + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 0.33 andnl %eax, %ebx, %ecx +# CHECK-NEXT: 2 6 0.50 * andnl (%rax), %ebx, %ecx +# CHECK-NEXT: 1 1 0.33 andnq %rax, %rbx, %rcx +# CHECK-NEXT: 2 6 0.50 * andnq (%rax), %rbx, %rcx +# CHECK-NEXT: 2 2 1.00 bextrl %eax, %ebx, %ecx +# CHECK-NEXT: 3 7 1.00 * bextrl %eax, (%rbx), %ecx +# CHECK-NEXT: 2 2 1.00 bextrq %rax, %rbx, %rcx +# CHECK-NEXT: 3 7 1.00 * bextrq %rax, (%rbx), %rcx +# CHECK-NEXT: 1 1 0.33 blsil %eax, %ecx +# CHECK-NEXT: 2 6 0.50 * blsil (%rax), %ecx +# CHECK-NEXT: 1 1 0.33 blsiq %rax, %rcx +# CHECK-NEXT: 2 6 0.50 * blsiq (%rax), %rcx +# CHECK-NEXT: 1 1 0.33 blsmskl %eax, %ecx +# CHECK-NEXT: 2 6 0.50 * blsmskl (%rax), %ecx +# CHECK-NEXT: 1 1 0.33 blsmskq %rax, %rcx +# CHECK-NEXT: 2 6 0.50 * blsmskq (%rax), %rcx +# CHECK-NEXT: 1 1 0.33 blsrl %eax, %ecx +# CHECK-NEXT: 2 6 0.50 * blsrl (%rax), %ecx +# CHECK-NEXT: 1 1 0.33 blsrq %rax, %rcx +# CHECK-NEXT: 2 6 0.50 * blsrq (%rax), %rcx +# CHECK-NEXT: 1 3 1.00 tzcntl %eax, %ecx +# CHECK-NEXT: 2 8 1.00 * tzcntl (%rax), %ecx +# CHECK-NEXT: 1 3 1.00 tzcntq %rax, %rcx +# CHECK-NEXT: 2 8 1.00 * tzcntq (%rax), %rcx + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 7.33 13.33 - 7.33 6.00 6.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andnl %eax, %ebx, %ecx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 andnl (%rax), %ebx, %ecx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andnq %rax, %rbx, %rcx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 andnq (%rax), %rbx, %rcx +# CHECK-NEXT: - - 0.50 1.00 - 0.50 - - bextrl %eax, %ebx, %ecx +# CHECK-NEXT: - - 0.50 1.00 - 0.50 0.50 0.50 bextrl %eax, (%rbx), %ecx +# CHECK-NEXT: - - 0.50 1.00 - 0.50 - - bextrq %rax, %rbx, %rcx +# CHECK-NEXT: - - 0.50 1.00 - 0.50 0.50 0.50 bextrq %rax, (%rbx), %rcx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - blsil %eax, %ecx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 blsil (%rax), %ecx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - blsiq %rax, %rcx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 blsiq (%rax), %rcx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - blsmskl %eax, %ecx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 blsmskl (%rax), %ecx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - blsmskq %rax, %rcx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 blsmskq (%rax), %rcx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - blsrl %eax, %ecx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 blsrl (%rax), %ecx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - blsrq %rax, %rcx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 blsrq (%rax), %rcx +# CHECK-NEXT: - - - 1.00 - - - - tzcntl %eax, %ecx +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 tzcntl (%rax), %ecx +# CHECK-NEXT: - - - 1.00 - - - - tzcntq %rax, %rcx +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 tzcntq (%rax), %rcx diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/resources-clflushopt.s b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-clflushopt.s new file mode 100644 index 00000000000..4678467babd --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-clflushopt.s @@ -0,0 +1,33 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +clflushopt (%rax) + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 4 5 1.00 * * U clflushopt (%rax) + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 0.50 0.50 1.00 1.00 0.50 0.50 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 0.50 0.50 1.00 1.00 0.50 0.50 clflushopt (%rax) diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/resources-cmov.s b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-cmov.s new file mode 100644 index 00000000000..e41571428d9 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-cmov.s @@ -0,0 +1,323 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +cmovow %si, %di +cmovnow %si, %di +cmovbw %si, %di +cmovaew %si, %di +cmovew %si, %di +cmovnew %si, %di +cmovbew %si, %di +cmovaw %si, %di +cmovsw %si, %di +cmovnsw %si, %di +cmovpw %si, %di +cmovnpw %si, %di +cmovlw %si, %di +cmovgew %si, %di +cmovlew %si, %di +cmovgw %si, %di + +cmovow (%rax), %di +cmovnow (%rax), %di +cmovbw (%rax), %di +cmovaew (%rax), %di +cmovew (%rax), %di +cmovnew (%rax), %di +cmovbew (%rax), %di +cmovaw (%rax), %di +cmovsw (%rax), %di +cmovnsw (%rax), %di +cmovpw (%rax), %di +cmovnpw (%rax), %di +cmovlw (%rax), %di +cmovgew (%rax), %di +cmovlew (%rax), %di +cmovgw (%rax), %di + +cmovol %esi, %edi +cmovnol %esi, %edi +cmovbl %esi, %edi +cmovael %esi, %edi +cmovel %esi, %edi +cmovnel %esi, %edi +cmovbel %esi, %edi +cmoval %esi, %edi +cmovsl %esi, %edi +cmovnsl %esi, %edi +cmovpl %esi, %edi +cmovnpl %esi, %edi +cmovll %esi, %edi +cmovgel %esi, %edi +cmovlel %esi, %edi +cmovgl %esi, %edi + +cmovol (%rax), %edi +cmovnol (%rax), %edi +cmovbl (%rax), %edi +cmovael (%rax), %edi +cmovel (%rax), %edi +cmovnel (%rax), %edi +cmovbel (%rax), %edi +cmoval (%rax), %edi +cmovsl (%rax), %edi +cmovnsl (%rax), %edi +cmovpl (%rax), %edi +cmovnpl (%rax), %edi +cmovll (%rax), %edi +cmovgel (%rax), %edi +cmovlel (%rax), %edi +cmovgl (%rax), %edi + +cmovoq %rsi, %rdi +cmovnoq %rsi, %rdi +cmovbq %rsi, %rdi +cmovaeq %rsi, %rdi +cmoveq %rsi, %rdi +cmovneq %rsi, %rdi +cmovbeq %rsi, %rdi +cmovaq %rsi, %rdi +cmovsq %rsi, %rdi +cmovnsq %rsi, %rdi +cmovpq %rsi, %rdi +cmovnpq %rsi, %rdi +cmovlq %rsi, %rdi +cmovgeq %rsi, %rdi +cmovleq %rsi, %rdi +cmovgq %rsi, %rdi + +cmovoq (%rax), %rdi +cmovnoq (%rax), %rdi +cmovbq (%rax), %rdi +cmovaeq (%rax), %rdi +cmoveq (%rax), %rdi +cmovneq (%rax), %rdi +cmovbeq (%rax), %rdi +cmovaq (%rax), %rdi +cmovsq (%rax), %rdi +cmovnsq (%rax), %rdi +cmovpq (%rax), %rdi +cmovnpq (%rax), %rdi +cmovlq (%rax), %rdi +cmovgeq (%rax), %rdi +cmovleq (%rax), %rdi +cmovgq (%rax), %rdi + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 2 2 0.67 cmovow %si, %di +# CHECK-NEXT: 2 2 0.67 cmovnow %si, %di +# CHECK-NEXT: 2 2 0.67 cmovbw %si, %di +# CHECK-NEXT: 2 2 0.67 cmovaew %si, %di +# CHECK-NEXT: 2 2 0.67 cmovew %si, %di +# CHECK-NEXT: 2 2 0.67 cmovnew %si, %di +# CHECK-NEXT: 3 3 1.00 cmovbew %si, %di +# CHECK-NEXT: 3 3 1.00 cmovaw %si, %di +# CHECK-NEXT: 2 2 0.67 cmovsw %si, %di +# CHECK-NEXT: 2 2 0.67 cmovnsw %si, %di +# CHECK-NEXT: 2 2 0.67 cmovpw %si, %di +# CHECK-NEXT: 2 2 0.67 cmovnpw %si, %di +# CHECK-NEXT: 2 2 0.67 cmovlw %si, %di +# CHECK-NEXT: 2 2 0.67 cmovgew %si, %di +# CHECK-NEXT: 2 2 0.67 cmovlew %si, %di +# CHECK-NEXT: 2 2 0.67 cmovgw %si, %di +# CHECK-NEXT: 3 7 0.67 * cmovow (%rax), %di +# CHECK-NEXT: 3 7 0.67 * cmovnow (%rax), %di +# CHECK-NEXT: 3 7 0.67 * cmovbw (%rax), %di +# CHECK-NEXT: 3 7 0.67 * cmovaew (%rax), %di +# CHECK-NEXT: 3 7 0.67 * cmovew (%rax), %di +# CHECK-NEXT: 3 7 0.67 * cmovnew (%rax), %di +# CHECK-NEXT: 4 8 1.00 * cmovbew (%rax), %di +# CHECK-NEXT: 4 8 1.00 * cmovaw (%rax), %di +# CHECK-NEXT: 3 7 0.67 * cmovsw (%rax), %di +# CHECK-NEXT: 3 7 0.67 * cmovnsw (%rax), %di +# CHECK-NEXT: 3 7 0.67 * cmovpw (%rax), %di +# CHECK-NEXT: 3 7 0.67 * cmovnpw (%rax), %di +# CHECK-NEXT: 3 7 0.67 * cmovlw (%rax), %di +# CHECK-NEXT: 3 7 0.67 * cmovgew (%rax), %di +# CHECK-NEXT: 3 7 0.67 * cmovlew (%rax), %di +# CHECK-NEXT: 3 7 0.67 * cmovgw (%rax), %di +# CHECK-NEXT: 2 2 0.67 cmovol %esi, %edi +# CHECK-NEXT: 2 2 0.67 cmovnol %esi, %edi +# CHECK-NEXT: 2 2 0.67 cmovbl %esi, %edi +# CHECK-NEXT: 2 2 0.67 cmovael %esi, %edi +# CHECK-NEXT: 2 2 0.67 cmovel %esi, %edi +# CHECK-NEXT: 2 2 0.67 cmovnel %esi, %edi +# CHECK-NEXT: 3 3 1.00 cmovbel %esi, %edi +# CHECK-NEXT: 3 3 1.00 cmoval %esi, %edi +# CHECK-NEXT: 2 2 0.67 cmovsl %esi, %edi +# CHECK-NEXT: 2 2 0.67 cmovnsl %esi, %edi +# CHECK-NEXT: 2 2 0.67 cmovpl %esi, %edi +# CHECK-NEXT: 2 2 0.67 cmovnpl %esi, %edi +# CHECK-NEXT: 2 2 0.67 cmovll %esi, %edi +# CHECK-NEXT: 2 2 0.67 cmovgel %esi, %edi +# CHECK-NEXT: 2 2 0.67 cmovlel %esi, %edi +# CHECK-NEXT: 2 2 0.67 cmovgl %esi, %edi +# CHECK-NEXT: 3 7 0.67 * cmovol (%rax), %edi +# CHECK-NEXT: 3 7 0.67 * cmovnol (%rax), %edi +# CHECK-NEXT: 3 7 0.67 * cmovbl (%rax), %edi +# CHECK-NEXT: 3 7 0.67 * cmovael (%rax), %edi +# CHECK-NEXT: 3 7 0.67 * cmovel (%rax), %edi +# CHECK-NEXT: 3 7 0.67 * cmovnel (%rax), %edi +# CHECK-NEXT: 4 8 1.00 * cmovbel (%rax), %edi +# CHECK-NEXT: 4 8 1.00 * cmoval (%rax), %edi +# CHECK-NEXT: 3 7 0.67 * cmovsl (%rax), %edi +# CHECK-NEXT: 3 7 0.67 * cmovnsl (%rax), %edi +# CHECK-NEXT: 3 7 0.67 * cmovpl (%rax), %edi +# CHECK-NEXT: 3 7 0.67 * cmovnpl (%rax), %edi +# CHECK-NEXT: 3 7 0.67 * cmovll (%rax), %edi +# CHECK-NEXT: 3 7 0.67 * cmovgel (%rax), %edi +# CHECK-NEXT: 3 7 0.67 * cmovlel (%rax), %edi +# CHECK-NEXT: 3 7 0.67 * cmovgl (%rax), %edi +# CHECK-NEXT: 2 2 0.67 cmovoq %rsi, %rdi +# CHECK-NEXT: 2 2 0.67 cmovnoq %rsi, %rdi +# CHECK-NEXT: 2 2 0.67 cmovbq %rsi, %rdi +# CHECK-NEXT: 2 2 0.67 cmovaeq %rsi, %rdi +# CHECK-NEXT: 2 2 0.67 cmoveq %rsi, %rdi +# CHECK-NEXT: 2 2 0.67 cmovneq %rsi, %rdi +# CHECK-NEXT: 3 3 1.00 cmovbeq %rsi, %rdi +# CHECK-NEXT: 3 3 1.00 cmovaq %rsi, %rdi +# CHECK-NEXT: 2 2 0.67 cmovsq %rsi, %rdi +# CHECK-NEXT: 2 2 0.67 cmovnsq %rsi, %rdi +# CHECK-NEXT: 2 2 0.67 cmovpq %rsi, %rdi +# CHECK-NEXT: 2 2 0.67 cmovnpq %rsi, %rdi +# CHECK-NEXT: 2 2 0.67 cmovlq %rsi, %rdi +# CHECK-NEXT: 2 2 0.67 cmovgeq %rsi, %rdi +# CHECK-NEXT: 2 2 0.67 cmovleq %rsi, %rdi +# CHECK-NEXT: 2 2 0.67 cmovgq %rsi, %rdi +# CHECK-NEXT: 3 7 0.67 * cmovoq (%rax), %rdi +# CHECK-NEXT: 3 7 0.67 * cmovnoq (%rax), %rdi +# CHECK-NEXT: 3 7 0.67 * cmovbq (%rax), %rdi +# CHECK-NEXT: 3 7 0.67 * cmovaeq (%rax), %rdi +# CHECK-NEXT: 3 7 0.67 * cmoveq (%rax), %rdi +# CHECK-NEXT: 3 7 0.67 * cmovneq (%rax), %rdi +# CHECK-NEXT: 4 8 1.00 * cmovbeq (%rax), %rdi +# CHECK-NEXT: 4 8 1.00 * cmovaq (%rax), %rdi +# CHECK-NEXT: 3 7 0.67 * cmovsq (%rax), %rdi +# CHECK-NEXT: 3 7 0.67 * cmovnsq (%rax), %rdi +# CHECK-NEXT: 3 7 0.67 * cmovpq (%rax), %rdi +# CHECK-NEXT: 3 7 0.67 * cmovnpq (%rax), %rdi +# CHECK-NEXT: 3 7 0.67 * cmovlq (%rax), %rdi +# CHECK-NEXT: 3 7 0.67 * cmovgeq (%rax), %rdi +# CHECK-NEXT: 3 7 0.67 * cmovleq (%rax), %rdi +# CHECK-NEXT: 3 7 0.67 * cmovgq (%rax), %rdi + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 86.00 32.00 - 86.00 24.00 24.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovow %si, %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovnow %si, %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovbw %si, %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovaew %si, %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovew %si, %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovnew %si, %di +# CHECK-NEXT: - - 1.33 0.33 - 1.33 - - cmovbew %si, %di +# CHECK-NEXT: - - 1.33 0.33 - 1.33 - - cmovaw %si, %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovsw %si, %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovnsw %si, %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovpw %si, %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovnpw %si, %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovlw %si, %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovgew %si, %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovlew %si, %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovgw %si, %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovow (%rax), %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovnow (%rax), %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovbw (%rax), %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovaew (%rax), %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovew (%rax), %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovnew (%rax), %di +# CHECK-NEXT: - - 1.33 0.33 - 1.33 0.50 0.50 cmovbew (%rax), %di +# CHECK-NEXT: - - 1.33 0.33 - 1.33 0.50 0.50 cmovaw (%rax), %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovsw (%rax), %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovnsw (%rax), %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovpw (%rax), %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovnpw (%rax), %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovlw (%rax), %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovgew (%rax), %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovlew (%rax), %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovgw (%rax), %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovol %esi, %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovnol %esi, %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovbl %esi, %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovael %esi, %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovel %esi, %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovnel %esi, %edi +# CHECK-NEXT: - - 1.33 0.33 - 1.33 - - cmovbel %esi, %edi +# CHECK-NEXT: - - 1.33 0.33 - 1.33 - - cmoval %esi, %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovsl %esi, %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovnsl %esi, %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovpl %esi, %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovnpl %esi, %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovll %esi, %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovgel %esi, %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovlel %esi, %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovgl %esi, %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovol (%rax), %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovnol (%rax), %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovbl (%rax), %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovael (%rax), %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovel (%rax), %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovnel (%rax), %edi +# CHECK-NEXT: - - 1.33 0.33 - 1.33 0.50 0.50 cmovbel (%rax), %edi +# CHECK-NEXT: - - 1.33 0.33 - 1.33 0.50 0.50 cmoval (%rax), %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovsl (%rax), %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovnsl (%rax), %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovpl (%rax), %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovnpl (%rax), %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovll (%rax), %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovgel (%rax), %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovlel (%rax), %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovgl (%rax), %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovoq %rsi, %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovnoq %rsi, %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovbq %rsi, %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovaeq %rsi, %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmoveq %rsi, %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovneq %rsi, %rdi +# CHECK-NEXT: - - 1.33 0.33 - 1.33 - - cmovbeq %rsi, %rdi +# CHECK-NEXT: - - 1.33 0.33 - 1.33 - - cmovaq %rsi, %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovsq %rsi, %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovnsq %rsi, %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovpq %rsi, %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovnpq %rsi, %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovlq %rsi, %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovgeq %rsi, %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovleq %rsi, %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovgq %rsi, %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovoq (%rax), %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovnoq (%rax), %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovbq (%rax), %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovaeq (%rax), %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmoveq (%rax), %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovneq (%rax), %rdi +# CHECK-NEXT: - - 1.33 0.33 - 1.33 0.50 0.50 cmovbeq (%rax), %rdi +# CHECK-NEXT: - - 1.33 0.33 - 1.33 0.50 0.50 cmovaq (%rax), %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovsq (%rax), %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovnsq (%rax), %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovpq (%rax), %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovnpq (%rax), %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovlq (%rax), %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovgeq (%rax), %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovleq (%rax), %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovgq (%rax), %rdi diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/resources-cmpxchg.s b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-cmpxchg.s new file mode 100644 index 00000000000..19a220702b1 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-cmpxchg.s @@ -0,0 +1,36 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +cmpxchg8b (%rax) +cmpxchg16b (%rax) + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 3 6 1.00 * * cmpxchg8b (%rax) +# CHECK-NEXT: 3 6 1.00 * * cmpxchg16b (%rax) + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 0.67 0.67 2.00 0.67 2.00 2.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 cmpxchg8b (%rax) +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 cmpxchg16b (%rax) diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/resources-f16c.s b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-f16c.s new file mode 100644 index 00000000000..7dea75f8f8f --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-f16c.s @@ -0,0 +1,57 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +vcvtph2ps %xmm0, %xmm2 +vcvtph2ps (%rax), %xmm2 + +vcvtph2ps %xmm0, %ymm2 +vcvtph2ps (%rax), %ymm2 + +vcvtps2ph $0, %xmm0, %xmm2 +vcvtps2ph $0, %xmm0, (%rax) + +vcvtps2ph $0, %ymm0, %xmm2 +vcvtps2ph $0, %ymm0, (%rax) + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 vcvtph2ps %xmm0, %xmm2 +# CHECK-NEXT: 2 8 1.00 * vcvtph2ps (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 vcvtph2ps %xmm0, %ymm2 +# CHECK-NEXT: 2 8 1.00 * vcvtph2ps (%rax), %ymm2 +# CHECK-NEXT: 1 3 1.00 vcvtps2ph $0, %xmm0, %xmm2 +# CHECK-NEXT: 1 4 1.00 * vcvtps2ph $0, %xmm0, (%rax) +# CHECK-NEXT: 1 3 1.00 vcvtps2ph $0, %ymm0, %xmm2 +# CHECK-NEXT: 1 4 1.00 * vcvtps2ph $0, %ymm0, (%rax) + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - - 8.00 2.00 - 2.00 2.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - - - - vcvtph2ps %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vcvtph2ps (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - vcvtph2ps %xmm0, %ymm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vcvtph2ps (%rax), %ymm2 +# CHECK-NEXT: - - - 1.00 - - - - vcvtps2ph $0, %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 1.00 - 0.50 0.50 vcvtps2ph $0, %xmm0, (%rax) +# CHECK-NEXT: - - - 1.00 - - - - vcvtps2ph $0, %ymm0, %xmm2 +# CHECK-NEXT: - - - 1.00 1.00 - 0.50 0.50 vcvtps2ph $0, %ymm0, (%rax) diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/resources-fma.s b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-fma.s new file mode 100644 index 00000000000..05b63edb7f9 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-fma.s @@ -0,0 +1,701 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +vfmadd132pd %xmm0, %xmm1, %xmm2 +vfmadd132pd (%rax), %xmm1, %xmm2 + +vfmadd132pd %ymm0, %ymm1, %ymm2 +vfmadd132pd (%rax), %ymm1, %ymm2 + +vfmadd213pd %xmm0, %xmm1, %xmm2 +vfmadd213pd (%rax), %xmm1, %xmm2 + +vfmadd213pd %ymm0, %ymm1, %ymm2 +vfmadd213pd (%rax), %ymm1, %ymm2 + +vfmadd231pd %xmm0, %xmm1, %xmm2 +vfmadd231pd (%rax), %xmm1, %xmm2 + +vfmadd231pd %ymm0, %ymm1, %ymm2 +vfmadd231pd (%rax), %ymm1, %ymm2 + +vfmadd132ps %xmm0, %xmm1, %xmm2 +vfmadd132ps (%rax), %xmm1, %xmm2 + +vfmadd132ps %ymm0, %ymm1, %ymm2 +vfmadd132ps (%rax), %ymm1, %ymm2 + +vfmadd213ps %xmm0, %xmm1, %xmm2 +vfmadd213ps (%rax), %xmm1, %xmm2 + +vfmadd213ps %ymm0, %ymm1, %ymm2 +vfmadd213ps (%rax), %ymm1, %ymm2 + +vfmadd231ps %xmm0, %xmm1, %xmm2 +vfmadd231ps (%rax), %xmm1, %xmm2 + +vfmadd231ps %ymm0, %ymm1, %ymm2 +vfmadd231ps (%rax), %ymm1, %ymm2 + +vfmadd132sd %xmm0, %xmm1, %xmm2 +vfmadd132sd (%rax), %xmm1, %xmm2 + +vfmadd213sd %xmm0, %xmm1, %xmm2 +vfmadd213sd (%rax), %xmm1, %xmm2 + +vfmadd231sd %xmm0, %xmm1, %xmm2 +vfmadd231sd (%rax), %xmm1, %xmm2 + +vfmadd132ss %xmm0, %xmm1, %xmm2 +vfmadd132ss (%rax), %xmm1, %xmm2 + +vfmadd213ss %xmm0, %xmm1, %xmm2 +vfmadd213ss (%rax), %xmm1, %xmm2 + +vfmadd231ss %xmm0, %xmm1, %xmm2 +vfmadd231ss (%rax), %xmm1, %xmm2 + +vfmaddsub132pd %xmm0, %xmm1, %xmm2 +vfmaddsub132pd (%rax), %xmm1, %xmm2 + +vfmaddsub132pd %ymm0, %ymm1, %ymm2 +vfmaddsub132pd (%rax), %ymm1, %ymm2 + +vfmaddsub213pd %xmm0, %xmm1, %xmm2 +vfmaddsub213pd (%rax), %xmm1, %xmm2 + +vfmaddsub213pd %ymm0, %ymm1, %ymm2 +vfmaddsub213pd (%rax), %ymm1, %ymm2 + +vfmaddsub231pd %xmm0, %xmm1, %xmm2 +vfmaddsub231pd (%rax), %xmm1, %xmm2 + +vfmaddsub231pd %ymm0, %ymm1, %ymm2 +vfmaddsub231pd (%rax), %ymm1, %ymm2 + +vfmaddsub132ps %xmm0, %xmm1, %xmm2 +vfmaddsub132ps (%rax), %xmm1, %xmm2 + +vfmaddsub132ps %ymm0, %ymm1, %ymm2 +vfmaddsub132ps (%rax), %ymm1, %ymm2 + +vfmaddsub213ps %xmm0, %xmm1, %xmm2 +vfmaddsub213ps (%rax), %xmm1, %xmm2 + +vfmaddsub213ps %ymm0, %ymm1, %ymm2 +vfmaddsub213ps (%rax), %ymm1, %ymm2 + +vfmaddsub231ps %xmm0, %xmm1, %xmm2 +vfmaddsub231ps (%rax), %xmm1, %xmm2 + +vfmaddsub231ps %ymm0, %ymm1, %ymm2 +vfmaddsub231ps (%rax), %ymm1, %ymm2 + +vfmsub132pd %xmm0, %xmm1, %xmm2 +vfmsub132pd (%rax), %xmm1, %xmm2 + +vfmsub132pd %ymm0, %ymm1, %ymm2 +vfmsub132pd (%rax), %ymm1, %ymm2 + +vfmsub213pd %xmm0, %xmm1, %xmm2 +vfmsub213pd (%rax), %xmm1, %xmm2 + +vfmsub213pd %ymm0, %ymm1, %ymm2 +vfmsub213pd (%rax), %ymm1, %ymm2 + +vfmsub231pd %xmm0, %xmm1, %xmm2 +vfmsub231pd (%rax), %xmm1, %xmm2 + +vfmsub231pd %ymm0, %ymm1, %ymm2 +vfmsub231pd (%rax), %ymm1, %ymm2 + +vfmsub132ps %xmm0, %xmm1, %xmm2 +vfmsub132ps (%rax), %xmm1, %xmm2 + +vfmsub132ps %ymm0, %ymm1, %ymm2 +vfmsub132ps (%rax), %ymm1, %ymm2 + +vfmsub213ps %xmm0, %xmm1, %xmm2 +vfmsub213ps (%rax), %xmm1, %xmm2 + +vfmsub213ps %ymm0, %ymm1, %ymm2 +vfmsub213ps (%rax), %ymm1, %ymm2 + +vfmsub231ps %xmm0, %xmm1, %xmm2 +vfmsub231ps (%rax), %xmm1, %xmm2 + +vfmsub231ps %ymm0, %ymm1, %ymm2 +vfmsub231ps (%rax), %ymm1, %ymm2 + +vfmsub132sd %xmm0, %xmm1, %xmm2 +vfmsub132sd (%rax), %xmm1, %xmm2 + +vfmsub213sd %xmm0, %xmm1, %xmm2 +vfmsub213sd (%rax), %xmm1, %xmm2 + +vfmsub231sd %xmm0, %xmm1, %xmm2 +vfmsub231sd (%rax), %xmm1, %xmm2 + +vfmsub132ss %xmm0, %xmm1, %xmm2 +vfmsub132ss (%rax), %xmm1, %xmm2 + +vfmsub213ss %xmm0, %xmm1, %xmm2 +vfmsub213ss (%rax), %xmm1, %xmm2 + +vfmsub231ss %xmm0, %xmm1, %xmm2 +vfmsub231ss (%rax), %xmm1, %xmm2 + +vfmsubadd132pd %xmm0, %xmm1, %xmm2 +vfmsubadd132pd (%rax), %xmm1, %xmm2 + +vfmsubadd132pd %ymm0, %ymm1, %ymm2 +vfmsubadd132pd (%rax), %ymm1, %ymm2 + +vfmsubadd213pd %xmm0, %xmm1, %xmm2 +vfmsubadd213pd (%rax), %xmm1, %xmm2 + +vfmsubadd213pd %ymm0, %ymm1, %ymm2 +vfmsubadd213pd (%rax), %ymm1, %ymm2 + +vfmsubadd231pd %xmm0, %xmm1, %xmm2 +vfmsubadd231pd (%rax), %xmm1, %xmm2 + +vfmsubadd231pd %ymm0, %ymm1, %ymm2 +vfmsubadd231pd (%rax), %ymm1, %ymm2 + +vfmsubadd132ps %xmm0, %xmm1, %xmm2 +vfmsubadd132ps (%rax), %xmm1, %xmm2 + +vfmsubadd132ps %ymm0, %ymm1, %ymm2 +vfmsubadd132ps (%rax), %ymm1, %ymm2 + +vfmsubadd213ps %xmm0, %xmm1, %xmm2 +vfmsubadd213ps (%rax), %xmm1, %xmm2 + +vfmsubadd213ps %ymm0, %ymm1, %ymm2 +vfmsubadd213ps (%rax), %ymm1, %ymm2 + +vfmsubadd231ps %xmm0, %xmm1, %xmm2 +vfmsubadd231ps (%rax), %xmm1, %xmm2 + +vfmsubadd231ps %ymm0, %ymm1, %ymm2 +vfmsubadd231ps (%rax), %ymm1, %ymm2 + +vfnmadd132pd %xmm0, %xmm1, %xmm2 +vfnmadd132pd (%rax), %xmm1, %xmm2 + +vfnmadd132pd %ymm0, %ymm1, %ymm2 +vfnmadd132pd (%rax), %ymm1, %ymm2 + +vfnmadd213pd %xmm0, %xmm1, %xmm2 +vfnmadd213pd (%rax), %xmm1, %xmm2 + +vfnmadd213pd %ymm0, %ymm1, %ymm2 +vfnmadd213pd (%rax), %ymm1, %ymm2 + +vfnmadd231pd %xmm0, %xmm1, %xmm2 +vfnmadd231pd (%rax), %xmm1, %xmm2 + +vfnmadd231pd %ymm0, %ymm1, %ymm2 +vfnmadd231pd (%rax), %ymm1, %ymm2 + +vfnmadd132ps %xmm0, %xmm1, %xmm2 +vfnmadd132ps (%rax), %xmm1, %xmm2 + +vfnmadd132ps %ymm0, %ymm1, %ymm2 +vfnmadd132ps (%rax), %ymm1, %ymm2 + +vfnmadd213ps %xmm0, %xmm1, %xmm2 +vfnmadd213ps (%rax), %xmm1, %xmm2 + +vfnmadd213ps %ymm0, %ymm1, %ymm2 +vfnmadd213ps (%rax), %ymm1, %ymm2 + +vfnmadd231ps %xmm0, %xmm1, %xmm2 +vfnmadd231ps (%rax), %xmm1, %xmm2 + +vfnmadd231ps %ymm0, %ymm1, %ymm2 +vfnmadd231ps (%rax), %ymm1, %ymm2 + +vfnmadd132sd %xmm0, %xmm1, %xmm2 +vfnmadd132sd (%rax), %xmm1, %xmm2 + +vfnmadd213sd %xmm0, %xmm1, %xmm2 +vfnmadd213sd (%rax), %xmm1, %xmm2 + +vfnmadd231sd %xmm0, %xmm1, %xmm2 +vfnmadd231sd (%rax), %xmm1, %xmm2 + +vfnmadd132ss %xmm0, %xmm1, %xmm2 +vfnmadd132ss (%rax), %xmm1, %xmm2 + +vfnmadd213ss %xmm0, %xmm1, %xmm2 +vfnmadd213ss (%rax), %xmm1, %xmm2 + +vfnmadd231ss %xmm0, %xmm1, %xmm2 +vfnmadd231ss (%rax), %xmm1, %xmm2 + +vfnmsub132pd %xmm0, %xmm1, %xmm2 +vfnmsub132pd (%rax), %xmm1, %xmm2 + +vfnmsub132pd %ymm0, %ymm1, %ymm2 +vfnmsub132pd (%rax), %ymm1, %ymm2 + +vfnmsub213pd %xmm0, %xmm1, %xmm2 +vfnmsub213pd (%rax), %xmm1, %xmm2 + +vfnmsub213pd %ymm0, %ymm1, %ymm2 +vfnmsub213pd (%rax), %ymm1, %ymm2 + +vfnmsub231pd %xmm0, %xmm1, %xmm2 +vfnmsub231pd (%rax), %xmm1, %xmm2 + +vfnmsub231pd %ymm0, %ymm1, %ymm2 +vfnmsub231pd (%rax), %ymm1, %ymm2 + +vfnmsub132ps %xmm0, %xmm1, %xmm2 +vfnmsub132ps (%rax), %xmm1, %xmm2 + +vfnmsub132ps %ymm0, %ymm1, %ymm2 +vfnmsub132ps (%rax), %ymm1, %ymm2 + +vfnmsub213ps %xmm0, %xmm1, %xmm2 +vfnmsub213ps (%rax), %xmm1, %xmm2 + +vfnmsub213ps %ymm0, %ymm1, %ymm2 +vfnmsub213ps (%rax), %ymm1, %ymm2 + +vfnmsub231ps %xmm0, %xmm1, %xmm2 +vfnmsub231ps (%rax), %xmm1, %xmm2 + +vfnmsub231ps %ymm0, %ymm1, %ymm2 +vfnmsub231ps (%rax), %ymm1, %ymm2 + +vfnmsub132sd %xmm0, %xmm1, %xmm2 +vfnmsub132sd (%rax), %xmm1, %xmm2 + +vfnmsub213sd %xmm0, %xmm1, %xmm2 +vfnmsub213sd (%rax), %xmm1, %xmm2 + +vfnmsub231sd %xmm0, %xmm1, %xmm2 +vfnmsub231sd (%rax), %xmm1, %xmm2 + +vfnmsub132ss %xmm0, %xmm1, %xmm2 +vfnmsub132ss (%rax), %xmm1, %xmm2 + +vfnmsub213ss %xmm0, %xmm1, %xmm2 +vfnmsub213ss (%rax), %xmm1, %xmm2 + +vfnmsub231ss %xmm0, %xmm1, %xmm2 +vfnmsub231ss (%rax), %xmm1, %xmm2 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 5 0.50 vfmadd132pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmadd132pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmadd132pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfmadd132pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfmadd213pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmadd213pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmadd213pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfmadd213pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfmadd231pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmadd231pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmadd231pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfmadd231pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfmadd132ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmadd132ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmadd132ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfmadd132ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfmadd213ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmadd213ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmadd213ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfmadd213ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfmadd231ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmadd231ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmadd231ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfmadd231ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfmadd132sd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmadd132sd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmadd213sd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmadd213sd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmadd231sd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmadd231sd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmadd132ss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmadd132ss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmadd213ss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmadd213ss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmadd231ss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmadd231ss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmaddsub132pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmaddsub132pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmaddsub132pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfmaddsub132pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfmaddsub213pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmaddsub213pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmaddsub213pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfmaddsub213pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfmaddsub231pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmaddsub231pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmaddsub231pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfmaddsub231pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfmaddsub132ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmaddsub132ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmaddsub132ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfmaddsub132ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfmaddsub213ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmaddsub213ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmaddsub213ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfmaddsub213ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfmaddsub231ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmaddsub231ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmaddsub231ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfmaddsub231ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfmsub132pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmsub132pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmsub132pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfmsub132pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfmsub213pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmsub213pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmsub213pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfmsub213pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfmsub231pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmsub231pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmsub231pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfmsub231pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfmsub132ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmsub132ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmsub132ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfmsub132ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfmsub213ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmsub213ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmsub213ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfmsub213ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfmsub231ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmsub231ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmsub231ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfmsub231ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfmsub132sd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmsub132sd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmsub213sd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmsub213sd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmsub231sd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmsub231sd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmsub132ss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmsub132ss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmsub213ss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmsub213ss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmsub231ss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmsub231ss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmsubadd132pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmsubadd132pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmsubadd132pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfmsubadd132pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfmsubadd213pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmsubadd213pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmsubadd213pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfmsubadd213pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfmsubadd231pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmsubadd231pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmsubadd231pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfmsubadd231pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfmsubadd132ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmsubadd132ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmsubadd132ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfmsubadd132ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfmsubadd213ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmsubadd213ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmsubadd213ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfmsubadd213ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfmsubadd231ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfmsubadd231ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfmsubadd231ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfmsubadd231ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfnmadd132pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfnmadd132pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfnmadd132pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfnmadd132pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfnmadd213pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfnmadd213pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfnmadd213pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfnmadd213pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfnmadd231pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfnmadd231pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfnmadd231pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfnmadd231pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfnmadd132ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfnmadd132ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfnmadd132ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfnmadd132ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfnmadd213ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfnmadd213ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfnmadd213ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfnmadd213ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfnmadd231ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfnmadd231ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfnmadd231ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfnmadd231ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfnmadd132sd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfnmadd132sd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfnmadd213sd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfnmadd213sd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfnmadd231sd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfnmadd231sd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfnmadd132ss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfnmadd132ss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfnmadd213ss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfnmadd213ss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfnmadd231ss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfnmadd231ss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfnmsub132pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfnmsub132pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfnmsub132pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfnmsub132pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfnmsub213pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfnmsub213pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfnmsub213pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfnmsub213pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfnmsub231pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfnmsub231pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfnmsub231pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfnmsub231pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfnmsub132ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfnmsub132ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfnmsub132ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfnmsub132ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfnmsub213ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfnmsub213ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfnmsub213ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfnmsub213ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfnmsub231ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfnmsub231ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfnmsub231ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 10 0.50 * vfnmsub231ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vfnmsub132sd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfnmsub132sd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfnmsub213sd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfnmsub213sd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfnmsub231sd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfnmsub231sd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfnmsub132ss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfnmsub132ss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfnmsub213ss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfnmsub213ss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vfnmsub231ss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 10 0.50 * vfnmsub231ss (%rax), %xmm1, %xmm2 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 96.00 96.00 - - 48.00 48.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmadd132pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmadd132pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmadd132pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmadd132pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmadd213pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmadd213pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmadd213pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmadd213pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmadd231pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmadd231pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmadd231pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmadd231pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmadd132ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmadd132ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmadd132ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmadd132ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmadd213ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmadd213ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmadd213ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmadd213ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmadd231ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmadd231ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmadd231ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmadd231ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmadd132sd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmadd132sd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmadd213sd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmadd213sd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmadd231sd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmadd231sd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmadd132ss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmadd132ss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmadd213ss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmadd213ss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmadd231ss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmadd231ss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmaddsub132pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmaddsub132pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmaddsub132pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmaddsub132pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmaddsub213pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmaddsub213pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmaddsub213pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmaddsub213pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmaddsub231pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmaddsub231pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmaddsub231pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmaddsub231pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmaddsub132ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmaddsub132ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmaddsub132ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmaddsub132ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmaddsub213ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmaddsub213ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmaddsub213ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmaddsub213ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmaddsub231ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmaddsub231ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmaddsub231ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmaddsub231ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsub132pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsub132pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsub132pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsub132pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsub213pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsub213pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsub213pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsub213pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsub231pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsub231pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsub231pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsub231pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsub132ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsub132ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsub132ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsub132ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsub213ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsub213ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsub213ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsub213ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsub231ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsub231ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsub231ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsub231ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsub132sd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsub132sd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsub213sd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsub213sd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsub231sd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsub231sd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsub132ss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsub132ss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsub213ss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsub213ss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsub231ss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsub231ss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsubadd132pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsubadd132pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsubadd132pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsubadd132pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsubadd213pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsubadd213pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsubadd213pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsubadd213pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsubadd231pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsubadd231pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsubadd231pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsubadd231pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsubadd132ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsubadd132ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsubadd132ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsubadd132ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsubadd213ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsubadd213ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsubadd213ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsubadd213ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsubadd231ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsubadd231ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsubadd231ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsubadd231ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmadd132pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmadd132pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmadd132pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmadd132pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmadd213pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmadd213pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmadd213pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmadd213pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmadd231pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmadd231pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmadd231pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmadd231pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmadd132ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmadd132ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmadd132ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmadd132ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmadd213ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmadd213ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmadd213ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmadd213ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmadd231ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmadd231ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmadd231ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmadd231ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmadd132sd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmadd132sd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmadd213sd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmadd213sd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmadd231sd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmadd231sd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmadd132ss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmadd132ss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmadd213ss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmadd213ss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmadd231ss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmadd231ss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmsub132pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmsub132pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmsub132pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmsub132pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmsub213pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmsub213pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmsub213pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmsub213pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmsub231pd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmsub231pd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmsub231pd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmsub231pd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmsub132ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmsub132ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmsub132ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmsub132ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmsub213ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmsub213ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmsub213ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmsub213ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmsub231ps %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmsub231ps (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmsub231ps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmsub231ps (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmsub132sd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmsub132sd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmsub213sd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmsub213sd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmsub231sd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmsub231sd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmsub132ss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmsub132ss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmsub213ss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmsub213ss (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmsub231ss %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmsub231ss (%rax), %xmm1, %xmm2 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/resources-fma4.s b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-fma4.s new file mode 100644 index 00000000000..cc428167b23 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-fma4.s @@ -0,0 +1,349 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +vfmaddpd %xmm0, %xmm1, %xmm2, %xmm3 +vfmaddpd (%rax), %xmm1, %xmm2, %xmm3 +vfmaddpd %xmm0, (%rax), %xmm2, %xmm3 + +vfmaddpd %ymm0, %ymm1, %ymm2, %ymm3 +vfmaddpd (%rax), %ymm1, %ymm2, %ymm3 +vfmaddpd %ymm0, (%rax), %ymm2, %ymm3 + +vfmaddps %xmm0, %xmm1, %xmm2, %xmm3 +vfmaddps (%rax), %xmm1, %xmm2, %xmm3 +vfmaddps %xmm0, (%rax), %xmm2, %xmm3 + +vfmaddps %ymm0, %ymm1, %ymm2, %ymm3 +vfmaddps (%rax), %ymm1, %ymm2, %ymm3 +vfmaddps %ymm0, (%rax), %ymm2, %ymm3 + +vfmaddsd %xmm0, %xmm1, %xmm2, %xmm3 +vfmaddsd (%rax), %xmm1, %xmm2, %xmm3 +vfmaddsd %xmm0, (%rax), %xmm2, %xmm3 + +vfmaddss %xmm0, %xmm1, %xmm2, %xmm3 +vfmaddss (%rax), %xmm1, %xmm2, %xmm3 +vfmaddss %xmm0, (%rax), %xmm2, %xmm3 + +vfmaddsubpd %xmm0, %xmm1, %xmm2, %xmm3 +vfmaddsubpd (%rax), %xmm1, %xmm2, %xmm3 +vfmaddsubpd %xmm0, (%rax), %xmm2, %xmm3 + +vfmaddsubpd %ymm0, %ymm1, %ymm2, %ymm3 +vfmaddsubpd (%rax), %ymm1, %ymm2, %ymm3 +vfmaddsubpd %ymm0, (%rax), %ymm2, %ymm3 + +vfmaddsubps %xmm0, %xmm1, %xmm2, %xmm3 +vfmaddsubps (%rax), %xmm1, %xmm2, %xmm3 +vfmaddsubps %xmm0, (%rax), %xmm2, %xmm3 + +vfmaddsubps %ymm0, %ymm1, %ymm2, %ymm3 +vfmaddsubps (%rax), %ymm1, %ymm2, %ymm3 +vfmaddsubps %ymm0, (%rax), %ymm2, %ymm3 + +vfmsubaddpd %xmm0, %xmm1, %xmm2, %xmm3 +vfmsubaddpd (%rax), %xmm1, %xmm2, %xmm3 +vfmsubaddpd %xmm0, (%rax), %xmm2, %xmm3 + +vfmsubaddpd %ymm0, %ymm1, %ymm2, %ymm3 +vfmsubaddpd (%rax), %ymm1, %ymm2, %ymm3 +vfmsubaddpd %ymm0, (%rax), %ymm2, %ymm3 + +vfmsubaddps %xmm0, %xmm1, %xmm2, %xmm3 +vfmsubaddps (%rax), %xmm1, %xmm2, %xmm3 +vfmsubaddps %xmm0, (%rax), %xmm2, %xmm3 + +vfmsubaddps %ymm0, %ymm1, %ymm2, %ymm3 +vfmsubaddps (%rax), %ymm1, %ymm2, %ymm3 +vfmsubaddps %ymm0, (%rax), %ymm2, %ymm3 + +vfmsubpd %xmm0, %xmm1, %xmm2, %xmm3 +vfmsubpd (%rax), %xmm1, %xmm2, %xmm3 +vfmsubpd %xmm0, (%rax), %xmm2, %xmm3 + +vfmsubpd %ymm0, %ymm1, %ymm2, %ymm3 +vfmsubpd (%rax), %ymm1, %ymm2, %ymm3 +vfmsubpd %ymm0, (%rax), %ymm2, %ymm3 + +vfmsubps %xmm0, %xmm1, %xmm2, %xmm3 +vfmsubps (%rax), %xmm1, %xmm2, %xmm3 +vfmsubps %xmm0, (%rax), %xmm2, %xmm3 + +vfmsubps %ymm0, %ymm1, %ymm2, %ymm3 +vfmsubps (%rax), %ymm1, %ymm2, %ymm3 +vfmsubps %ymm0, (%rax), %ymm2, %ymm3 + +vfmsubsd %xmm0, %xmm1, %xmm2, %xmm3 +vfmsubsd (%rax), %xmm1, %xmm2, %xmm3 +vfmsubsd %xmm0, (%rax), %xmm2, %xmm3 + +vfmsubss %xmm0, %xmm1, %xmm2, %xmm3 +vfmsubss (%rax), %xmm1, %xmm2, %xmm3 +vfmsubss %xmm0, (%rax), %xmm2, %xmm3 + +vfnmaddpd %xmm0, %xmm1, %xmm2, %xmm3 +vfnmaddpd (%rax), %xmm1, %xmm2, %xmm3 +vfnmaddpd %xmm0, (%rax), %xmm2, %xmm3 + +vfnmaddpd %ymm0, %ymm1, %ymm2, %ymm3 +vfnmaddpd (%rax), %ymm1, %ymm2, %ymm3 +vfnmaddpd %ymm0, (%rax), %ymm2, %ymm3 + +vfnmaddps %xmm0, %xmm1, %xmm2, %xmm3 +vfnmaddps (%rax), %xmm1, %xmm2, %xmm3 +vfnmaddps %xmm0, (%rax), %xmm2, %xmm3 + +vfnmaddps %ymm0, %ymm1, %ymm2, %ymm3 +vfnmaddps (%rax), %ymm1, %ymm2, %ymm3 +vfnmaddps %ymm0, (%rax), %ymm2, %ymm3 + +vfnmaddsd %xmm0, %xmm1, %xmm2, %xmm3 +vfnmaddsd (%rax), %xmm1, %xmm2, %xmm3 +vfnmaddsd %xmm0, (%rax), %xmm2, %xmm3 + +vfnmaddss %xmm0, %xmm1, %xmm2, %xmm3 +vfnmaddss (%rax), %xmm1, %xmm2, %xmm3 +vfnmaddss %xmm0, (%rax), %xmm2, %xmm3 + +vfnmsubpd %xmm0, %xmm1, %xmm2, %xmm3 +vfnmsubpd (%rax), %xmm1, %xmm2, %xmm3 +vfnmsubpd %xmm0, (%rax), %xmm2, %xmm3 + +vfnmsubpd %ymm0, %ymm1, %ymm2, %ymm3 +vfnmsubpd (%rax), %ymm1, %ymm2, %ymm3 +vfnmsubpd %ymm0, (%rax), %ymm2, %ymm3 + +vfnmsubps %xmm0, %xmm1, %xmm2, %xmm3 +vfnmsubps (%rax), %xmm1, %xmm2, %xmm3 +vfnmsubps %xmm0, (%rax), %xmm2, %xmm3 + +vfnmsubps %ymm0, %ymm1, %ymm2, %ymm3 +vfnmsubps (%rax), %ymm1, %ymm2, %ymm3 +vfnmsubps %ymm0, (%rax), %ymm2, %ymm3 + +vfnmsubsd %xmm0, %xmm1, %xmm2, %xmm3 +vfnmsubsd (%rax), %xmm1, %xmm2, %xmm3 +vfnmsubsd %xmm0, (%rax), %xmm2, %xmm3 + +vfnmsubss %xmm0, %xmm1, %xmm2, %xmm3 +vfnmsubss (%rax), %xmm1, %xmm2, %xmm3 +vfnmsubss %xmm0, (%rax), %xmm2, %xmm3 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 5 0.50 vfmaddpd %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfmaddpd (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfmaddpd %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: 1 5 0.50 vfmaddpd %ymm0, %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: 2 10 0.50 * vfmaddpd (%rax), %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: 2 10 0.50 * vfmaddpd %ymm0, (%rax), %ymm2, %ymm3 +# CHECK-NEXT: 1 5 0.50 vfmaddps %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfmaddps (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfmaddps %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: 1 5 0.50 vfmaddps %ymm0, %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: 2 10 0.50 * vfmaddps (%rax), %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: 2 10 0.50 * vfmaddps %ymm0, (%rax), %ymm2, %ymm3 +# CHECK-NEXT: 1 5 0.50 vfmaddsd %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfmaddsd (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfmaddsd %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: 1 5 0.50 vfmaddss %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfmaddss (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfmaddss %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: 1 5 0.50 vfmaddsubpd %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfmaddsubpd (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfmaddsubpd %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: 1 5 0.50 vfmaddsubpd %ymm0, %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: 2 10 0.50 * vfmaddsubpd (%rax), %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: 2 10 0.50 * vfmaddsubpd %ymm0, (%rax), %ymm2, %ymm3 +# CHECK-NEXT: 1 5 0.50 vfmaddsubps %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfmaddsubps (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfmaddsubps %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: 1 5 0.50 vfmaddsubps %ymm0, %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: 2 10 0.50 * vfmaddsubps (%rax), %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: 2 10 0.50 * vfmaddsubps %ymm0, (%rax), %ymm2, %ymm3 +# CHECK-NEXT: 1 5 0.50 vfmsubaddpd %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfmsubaddpd (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfmsubaddpd %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: 1 5 0.50 vfmsubaddpd %ymm0, %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: 2 10 0.50 * vfmsubaddpd (%rax), %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: 2 10 0.50 * vfmsubaddpd %ymm0, (%rax), %ymm2, %ymm3 +# CHECK-NEXT: 1 5 0.50 vfmsubaddps %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfmsubaddps (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfmsubaddps %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: 1 5 0.50 vfmsubaddps %ymm0, %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: 2 10 0.50 * vfmsubaddps (%rax), %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: 2 10 0.50 * vfmsubaddps %ymm0, (%rax), %ymm2, %ymm3 +# CHECK-NEXT: 1 5 0.50 vfmsubpd %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfmsubpd (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfmsubpd %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: 1 5 0.50 vfmsubpd %ymm0, %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: 2 10 0.50 * vfmsubpd (%rax), %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: 2 10 0.50 * vfmsubpd %ymm0, (%rax), %ymm2, %ymm3 +# CHECK-NEXT: 1 5 0.50 vfmsubps %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfmsubps (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfmsubps %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: 1 5 0.50 vfmsubps %ymm0, %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: 2 10 0.50 * vfmsubps (%rax), %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: 2 10 0.50 * vfmsubps %ymm0, (%rax), %ymm2, %ymm3 +# CHECK-NEXT: 1 5 0.50 vfmsubsd %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfmsubsd (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfmsubsd %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: 1 5 0.50 vfmsubss %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfmsubss (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfmsubss %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: 1 5 0.50 vfnmaddpd %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfnmaddpd (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfnmaddpd %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: 1 5 0.50 vfnmaddpd %ymm0, %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: 2 10 0.50 * vfnmaddpd (%rax), %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: 2 10 0.50 * vfnmaddpd %ymm0, (%rax), %ymm2, %ymm3 +# CHECK-NEXT: 1 5 0.50 vfnmaddps %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfnmaddps (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfnmaddps %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: 1 5 0.50 vfnmaddps %ymm0, %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: 2 10 0.50 * vfnmaddps (%rax), %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: 2 10 0.50 * vfnmaddps %ymm0, (%rax), %ymm2, %ymm3 +# CHECK-NEXT: 1 5 0.50 vfnmaddsd %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfnmaddsd (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfnmaddsd %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: 1 5 0.50 vfnmaddss %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfnmaddss (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfnmaddss %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: 1 5 0.50 vfnmsubpd %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfnmsubpd (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfnmsubpd %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: 1 5 0.50 vfnmsubpd %ymm0, %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: 2 10 0.50 * vfnmsubpd (%rax), %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: 2 10 0.50 * vfnmsubpd %ymm0, (%rax), %ymm2, %ymm3 +# CHECK-NEXT: 1 5 0.50 vfnmsubps %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfnmsubps (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfnmsubps %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: 1 5 0.50 vfnmsubps %ymm0, %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: 2 10 0.50 * vfnmsubps (%rax), %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: 2 10 0.50 * vfnmsubps %ymm0, (%rax), %ymm2, %ymm3 +# CHECK-NEXT: 1 5 0.50 vfnmsubsd %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfnmsubsd (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfnmsubsd %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: 1 5 0.50 vfnmsubss %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfnmsubss (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 10 0.50 * vfnmsubss %xmm0, (%rax), %xmm2, %xmm3 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 48.00 48.00 - - 32.00 32.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmaddpd %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmaddpd (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmaddpd %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmaddpd %ymm0, %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmaddpd (%rax), %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmaddpd %ymm0, (%rax), %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmaddps %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmaddps (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmaddps %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmaddps %ymm0, %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmaddps (%rax), %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmaddps %ymm0, (%rax), %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmaddsd %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmaddsd (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmaddsd %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmaddss %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmaddss (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmaddss %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmaddsubpd %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmaddsubpd (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmaddsubpd %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmaddsubpd %ymm0, %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmaddsubpd (%rax), %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmaddsubpd %ymm0, (%rax), %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmaddsubps %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmaddsubps (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmaddsubps %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmaddsubps %ymm0, %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmaddsubps (%rax), %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmaddsubps %ymm0, (%rax), %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsubaddpd %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsubaddpd (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsubaddpd %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsubaddpd %ymm0, %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsubaddpd (%rax), %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsubaddpd %ymm0, (%rax), %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsubaddps %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsubaddps (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsubaddps %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsubaddps %ymm0, %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsubaddps (%rax), %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsubaddps %ymm0, (%rax), %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsubpd %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsubpd (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsubpd %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsubpd %ymm0, %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsubpd (%rax), %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsubpd %ymm0, (%rax), %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsubps %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsubps (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsubps %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsubps %ymm0, %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsubps (%rax), %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsubps %ymm0, (%rax), %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsubsd %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsubsd (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsubsd %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfmsubss %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsubss (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfmsubss %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmaddpd %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmaddpd (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmaddpd %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmaddpd %ymm0, %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmaddpd (%rax), %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmaddpd %ymm0, (%rax), %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmaddps %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmaddps (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmaddps %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmaddps %ymm0, %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmaddps (%rax), %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmaddps %ymm0, (%rax), %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmaddsd %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmaddsd (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmaddsd %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmaddss %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmaddss (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmaddss %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmsubpd %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmsubpd (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmsubpd %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmsubpd %ymm0, %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmsubpd (%rax), %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmsubpd %ymm0, (%rax), %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmsubps %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmsubps (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmsubps %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmsubps %ymm0, %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmsubps (%rax), %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmsubps %ymm0, (%rax), %ymm2, %ymm3 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmsubsd %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmsubsd (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmsubsd %xmm0, (%rax), %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - - - vfnmsubss %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmsubss (%rax), %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 vfnmsubss %xmm0, (%rax), %xmm2, %xmm3 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/resources-lea.s b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-lea.s new file mode 100644 index 00000000000..455fbe0411e --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-lea.s @@ -0,0 +1,437 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +lea 0(), %cx +lea 0(), %ecx +lea 0(), %rcx +lea (%eax), %cx +lea (%eax), %ecx +lea (%eax), %rcx +lea (%rax), %cx +lea (%rax), %ecx +lea (%rax), %rcx +lea (, %ebx), %cx +lea (, %ebx), %ecx +lea (, %ebx), %rcx +lea (, %rbx), %cx +lea (, %rbx), %ecx +lea (, %rbx), %rcx +lea (, %ebx, 1), %cx +lea (, %ebx, 1), %ecx +lea (, %ebx, 1), %rcx +lea (, %rbx, 1), %cx +lea (, %rbx, 1), %ecx +lea (, %rbx, 1), %rcx +lea (, %ebx, 2), %cx +lea (, %ebx, 2), %ecx +lea (, %ebx, 2), %rcx +lea (, %rbx, 2), %cx +lea (, %rbx, 2), %ecx +lea (, %rbx, 2), %rcx +lea (%eax, %ebx), %cx +lea (%eax, %ebx), %ecx +lea (%eax, %ebx), %rcx +lea (%rax, %rbx), %cx +lea (%rax, %rbx), %ecx +lea (%rax, %rbx), %rcx +lea (%eax, %ebx, 1), %cx +lea (%eax, %ebx, 1), %ecx +lea (%eax, %ebx, 1), %rcx +lea (%rax, %rbx, 1), %cx +lea (%rax, %rbx, 1), %ecx +lea (%rax, %rbx, 1), %rcx +lea (%eax, %ebx, 2), %cx +lea (%eax, %ebx, 2), %ecx +lea (%eax, %ebx, 2), %rcx +lea (%rax, %rbx, 2), %cx +lea (%rax, %rbx, 2), %ecx +lea (%rax, %rbx, 2), %rcx + +lea -16(), %cx +lea -16(), %ecx +lea -16(), %rcx +lea -16(%eax), %cx +lea -16(%eax), %ecx +lea -16(%eax), %rcx +lea -16(%rax), %cx +lea -16(%rax), %ecx +lea -16(%rax), %rcx +lea -16(, %ebx), %cx +lea -16(, %ebx), %ecx +lea -16(, %ebx), %rcx +lea -16(, %rbx), %cx +lea -16(, %rbx), %ecx +lea -16(, %rbx), %rcx +lea -16(, %ebx, 1), %cx +lea -16(, %ebx, 1), %ecx +lea -16(, %ebx, 1), %rcx +lea -16(, %rbx, 1), %cx +lea -16(, %rbx, 1), %ecx +lea -16(, %rbx, 1), %rcx +lea -16(, %ebx, 2), %cx +lea -16(, %ebx, 2), %ecx +lea -16(, %ebx, 2), %rcx +lea -16(, %rbx, 2), %cx +lea -16(, %rbx, 2), %ecx +lea -16(, %rbx, 2), %rcx +lea -16(%eax, %ebx), %cx +lea -16(%eax, %ebx), %ecx +lea -16(%eax, %ebx), %rcx +lea -16(%rax, %rbx), %cx +lea -16(%rax, %rbx), %ecx +lea -16(%rax, %rbx), %rcx +lea -16(%eax, %ebx, 1), %cx +lea -16(%eax, %ebx, 1), %ecx +lea -16(%eax, %ebx, 1), %rcx +lea -16(%rax, %rbx, 1), %cx +lea -16(%rax, %rbx, 1), %ecx +lea -16(%rax, %rbx, 1), %rcx +lea -16(%eax, %ebx, 2), %cx +lea -16(%eax, %ebx, 2), %ecx +lea -16(%eax, %ebx, 2), %rcx +lea -16(%rax, %rbx, 2), %cx +lea -16(%rax, %rbx, 2), %ecx +lea -16(%rax, %rbx, 2), %rcx + +lea 1024(), %cx +lea 1024(), %ecx +lea 1024(), %rcx +lea 1024(%eax), %cx +lea 1024(%eax), %ecx +lea 1024(%eax), %rcx +lea 1024(%rax), %cx +lea 1024(%rax), %ecx +lea 1024(%rax), %rcx +lea 1024(, %ebx), %cx +lea 1024(, %ebx), %ecx +lea 1024(, %ebx), %rcx +lea 1024(, %rbx), %cx +lea 1024(, %rbx), %ecx +lea 1024(, %rbx), %rcx +lea 1024(, %ebx, 1), %cx +lea 1024(, %ebx, 1), %ecx +lea 1024(, %ebx, 1), %rcx +lea 1024(, %rbx, 1), %cx +lea 1024(, %rbx, 1), %ecx +lea 1024(, %rbx, 1), %rcx +lea 1024(, %ebx, 2), %cx +lea 1024(, %ebx, 2), %ecx +lea 1024(, %ebx, 2), %rcx +lea 1024(, %rbx, 2), %cx +lea 1024(, %rbx, 2), %ecx +lea 1024(, %rbx, 2), %rcx +lea 1024(%eax, %ebx), %cx +lea 1024(%eax, %ebx), %ecx +lea 1024(%eax, %ebx), %rcx +lea 1024(%rax, %rbx), %cx +lea 1024(%rax, %rbx), %ecx +lea 1024(%rax, %rbx), %rcx +lea 1024(%eax, %ebx, 1), %cx +lea 1024(%eax, %ebx, 1), %ecx +lea 1024(%eax, %ebx, 1), %rcx +lea 1024(%rax, %rbx, 1), %cx +lea 1024(%rax, %rbx, 1), %ecx +lea 1024(%rax, %rbx, 1), %rcx +lea 1024(%eax, %ebx, 2), %cx +lea 1024(%eax, %ebx, 2), %ecx +lea 1024(%eax, %ebx, 2), %rcx +lea 1024(%rax, %rbx, 2), %cx +lea 1024(%rax, %rbx, 2), %ecx +lea 1024(%rax, %rbx, 2), %rcx + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 0.50 leaw 0, %cx +# CHECK-NEXT: 1 1 0.50 leal 0, %ecx +# CHECK-NEXT: 1 1 0.50 leaq 0, %rcx +# CHECK-NEXT: 1 1 0.50 leaw (%eax), %cx +# CHECK-NEXT: 1 1 0.50 leal (%eax), %ecx +# CHECK-NEXT: 1 1 0.50 leaq (%eax), %rcx +# CHECK-NEXT: 1 1 0.50 leaw (%rax), %cx +# CHECK-NEXT: 1 1 0.50 leal (%rax), %ecx +# CHECK-NEXT: 1 1 0.50 leaq (%rax), %rcx +# CHECK-NEXT: 1 1 0.50 leaw (,%ebx), %cx +# CHECK-NEXT: 1 1 0.50 leal (,%ebx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq (,%ebx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw (,%rbx), %cx +# CHECK-NEXT: 1 1 0.50 leal (,%rbx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq (,%rbx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw (,%ebx), %cx +# CHECK-NEXT: 1 1 0.50 leal (,%ebx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq (,%ebx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw (,%rbx), %cx +# CHECK-NEXT: 1 1 0.50 leal (,%rbx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq (,%rbx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw (,%ebx,2), %cx +# CHECK-NEXT: 1 1 0.50 leal (,%ebx,2), %ecx +# CHECK-NEXT: 1 1 0.50 leaq (,%ebx,2), %rcx +# CHECK-NEXT: 1 1 0.50 leaw (,%rbx,2), %cx +# CHECK-NEXT: 1 1 0.50 leal (,%rbx,2), %ecx +# CHECK-NEXT: 1 1 0.50 leaq (,%rbx,2), %rcx +# CHECK-NEXT: 1 1 0.50 leaw (%eax,%ebx), %cx +# CHECK-NEXT: 1 1 0.50 leal (%eax,%ebx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq (%eax,%ebx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw (%rax,%rbx), %cx +# CHECK-NEXT: 1 1 0.50 leal (%rax,%rbx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq (%rax,%rbx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw (%eax,%ebx), %cx +# CHECK-NEXT: 1 1 0.50 leal (%eax,%ebx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq (%eax,%ebx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw (%rax,%rbx), %cx +# CHECK-NEXT: 1 1 0.50 leal (%rax,%rbx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq (%rax,%rbx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw (%eax,%ebx,2), %cx +# CHECK-NEXT: 1 1 0.50 leal (%eax,%ebx,2), %ecx +# CHECK-NEXT: 1 1 0.50 leaq (%eax,%ebx,2), %rcx +# CHECK-NEXT: 1 1 0.50 leaw (%rax,%rbx,2), %cx +# CHECK-NEXT: 1 1 0.50 leal (%rax,%rbx,2), %ecx +# CHECK-NEXT: 1 1 0.50 leaq (%rax,%rbx,2), %rcx +# CHECK-NEXT: 1 1 0.50 leaw -16, %cx +# CHECK-NEXT: 1 1 0.50 leal -16, %ecx +# CHECK-NEXT: 1 1 0.50 leaq -16, %rcx +# CHECK-NEXT: 1 1 0.50 leaw -16(%eax), %cx +# CHECK-NEXT: 1 1 0.50 leal -16(%eax), %ecx +# CHECK-NEXT: 1 1 0.50 leaq -16(%eax), %rcx +# CHECK-NEXT: 1 1 0.50 leaw -16(%rax), %cx +# CHECK-NEXT: 1 1 0.50 leal -16(%rax), %ecx +# CHECK-NEXT: 1 1 0.50 leaq -16(%rax), %rcx +# CHECK-NEXT: 1 1 0.50 leaw -16(,%ebx), %cx +# CHECK-NEXT: 1 1 0.50 leal -16(,%ebx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq -16(,%ebx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw -16(,%rbx), %cx +# CHECK-NEXT: 1 1 0.50 leal -16(,%rbx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq -16(,%rbx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw -16(,%ebx), %cx +# CHECK-NEXT: 1 1 0.50 leal -16(,%ebx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq -16(,%ebx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw -16(,%rbx), %cx +# CHECK-NEXT: 1 1 0.50 leal -16(,%rbx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq -16(,%rbx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw -16(,%ebx,2), %cx +# CHECK-NEXT: 1 1 0.50 leal -16(,%ebx,2), %ecx +# CHECK-NEXT: 1 1 0.50 leaq -16(,%ebx,2), %rcx +# CHECK-NEXT: 1 1 0.50 leaw -16(,%rbx,2), %cx +# CHECK-NEXT: 1 1 0.50 leal -16(,%rbx,2), %ecx +# CHECK-NEXT: 1 1 0.50 leaq -16(,%rbx,2), %rcx +# CHECK-NEXT: 1 1 0.50 leaw -16(%eax,%ebx), %cx +# CHECK-NEXT: 1 1 0.50 leal -16(%eax,%ebx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq -16(%eax,%ebx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw -16(%rax,%rbx), %cx +# CHECK-NEXT: 1 1 0.50 leal -16(%rax,%rbx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq -16(%rax,%rbx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw -16(%eax,%ebx), %cx +# CHECK-NEXT: 1 1 0.50 leal -16(%eax,%ebx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq -16(%eax,%ebx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw -16(%rax,%rbx), %cx +# CHECK-NEXT: 1 1 0.50 leal -16(%rax,%rbx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq -16(%rax,%rbx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw -16(%eax,%ebx,2), %cx +# CHECK-NEXT: 1 1 0.50 leal -16(%eax,%ebx,2), %ecx +# CHECK-NEXT: 1 1 0.50 leaq -16(%eax,%ebx,2), %rcx +# CHECK-NEXT: 1 1 0.50 leaw -16(%rax,%rbx,2), %cx +# CHECK-NEXT: 1 1 0.50 leal -16(%rax,%rbx,2), %ecx +# CHECK-NEXT: 1 1 0.50 leaq -16(%rax,%rbx,2), %rcx +# CHECK-NEXT: 1 1 0.50 leaw 1024, %cx +# CHECK-NEXT: 1 1 0.50 leal 1024, %ecx +# CHECK-NEXT: 1 1 0.50 leaq 1024, %rcx +# CHECK-NEXT: 1 1 0.50 leaw 1024(%eax), %cx +# CHECK-NEXT: 1 1 0.50 leal 1024(%eax), %ecx +# CHECK-NEXT: 1 1 0.50 leaq 1024(%eax), %rcx +# CHECK-NEXT: 1 1 0.50 leaw 1024(%rax), %cx +# CHECK-NEXT: 1 1 0.50 leal 1024(%rax), %ecx +# CHECK-NEXT: 1 1 0.50 leaq 1024(%rax), %rcx +# CHECK-NEXT: 1 1 0.50 leaw 1024(,%ebx), %cx +# CHECK-NEXT: 1 1 0.50 leal 1024(,%ebx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq 1024(,%ebx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw 1024(,%rbx), %cx +# CHECK-NEXT: 1 1 0.50 leal 1024(,%rbx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq 1024(,%rbx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw 1024(,%ebx), %cx +# CHECK-NEXT: 1 1 0.50 leal 1024(,%ebx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq 1024(,%ebx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw 1024(,%rbx), %cx +# CHECK-NEXT: 1 1 0.50 leal 1024(,%rbx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq 1024(,%rbx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw 1024(,%ebx,2), %cx +# CHECK-NEXT: 1 1 0.50 leal 1024(,%ebx,2), %ecx +# CHECK-NEXT: 1 1 0.50 leaq 1024(,%ebx,2), %rcx +# CHECK-NEXT: 1 1 0.50 leaw 1024(,%rbx,2), %cx +# CHECK-NEXT: 1 1 0.50 leal 1024(,%rbx,2), %ecx +# CHECK-NEXT: 1 1 0.50 leaq 1024(,%rbx,2), %rcx +# CHECK-NEXT: 1 1 0.50 leaw 1024(%eax,%ebx), %cx +# CHECK-NEXT: 1 1 0.50 leal 1024(%eax,%ebx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq 1024(%eax,%ebx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw 1024(%rax,%rbx), %cx +# CHECK-NEXT: 1 1 0.50 leal 1024(%rax,%rbx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq 1024(%rax,%rbx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw 1024(%eax,%ebx), %cx +# CHECK-NEXT: 1 1 0.50 leal 1024(%eax,%ebx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq 1024(%eax,%ebx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw 1024(%rax,%rbx), %cx +# CHECK-NEXT: 1 1 0.50 leal 1024(%rax,%rbx), %ecx +# CHECK-NEXT: 1 1 0.50 leaq 1024(%rax,%rbx), %rcx +# CHECK-NEXT: 1 1 0.50 leaw 1024(%eax,%ebx,2), %cx +# CHECK-NEXT: 1 1 0.50 leal 1024(%eax,%ebx,2), %ecx +# CHECK-NEXT: 1 1 0.50 leaq 1024(%eax,%ebx,2), %rcx +# CHECK-NEXT: 1 1 0.50 leaw 1024(%rax,%rbx,2), %cx +# CHECK-NEXT: 1 1 0.50 leal 1024(%rax,%rbx,2), %ecx +# CHECK-NEXT: 1 1 0.50 leaq 1024(%rax,%rbx,2), %rcx + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 67.50 67.50 - - - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 0, %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal 0, %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 0, %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (%eax), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal (%eax), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (%eax), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (%rax), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal (%rax), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (%rax), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (,%ebx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal (,%ebx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (,%ebx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (,%rbx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal (,%rbx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (,%rbx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (,%ebx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal (,%ebx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (,%ebx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (,%rbx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal (,%rbx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (,%rbx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (,%ebx,2), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal (,%ebx,2), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (,%ebx,2), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (,%rbx,2), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal (,%rbx,2), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (,%rbx,2), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (%eax,%ebx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal (%eax,%ebx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (%eax,%ebx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (%rax,%rbx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal (%rax,%rbx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (%rax,%rbx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (%eax,%ebx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal (%eax,%ebx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (%eax,%ebx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (%rax,%rbx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal (%rax,%rbx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (%rax,%rbx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (%eax,%ebx,2), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal (%eax,%ebx,2), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (%eax,%ebx,2), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (%rax,%rbx,2), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal (%rax,%rbx,2), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (%rax,%rbx,2), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16, %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16, %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16, %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(%eax), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(%eax), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(%eax), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(%rax), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(%rax), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(%rax), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(,%ebx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(,%ebx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(,%ebx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(,%rbx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(,%rbx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(,%rbx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(,%ebx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(,%ebx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(,%ebx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(,%rbx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(,%rbx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(,%rbx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(,%ebx,2), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(,%ebx,2), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(,%ebx,2), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(,%rbx,2), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(,%rbx,2), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(,%rbx,2), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(%eax,%ebx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(%eax,%ebx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(%eax,%ebx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(%rax,%rbx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(%rax,%rbx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(%rax,%rbx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(%eax,%ebx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(%eax,%ebx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(%eax,%ebx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(%rax,%rbx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(%rax,%rbx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(%rax,%rbx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(%eax,%ebx,2), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(%eax,%ebx,2), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(%eax,%ebx,2), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(%rax,%rbx,2), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(%rax,%rbx,2), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(%rax,%rbx,2), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024, %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024, %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024, %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(%eax), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(%eax), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(%eax), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(%rax), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(%rax), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(%rax), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(,%ebx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(,%ebx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(,%ebx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(,%rbx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(,%rbx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(,%rbx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(,%ebx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(,%ebx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(,%ebx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(,%rbx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(,%rbx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(,%rbx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(,%ebx,2), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(,%ebx,2), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(,%ebx,2), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(,%rbx,2), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(,%rbx,2), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(,%rbx,2), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(%eax,%ebx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(%eax,%ebx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(%eax,%ebx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(%rax,%rbx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(%rax,%rbx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(%rax,%rbx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(%eax,%ebx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(%eax,%ebx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(%eax,%ebx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(%rax,%rbx), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(%rax,%rbx), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(%rax,%rbx), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(%eax,%ebx,2), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(%eax,%ebx,2), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(%eax,%ebx,2), %rcx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(%rax,%rbx,2), %cx +# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(%rax,%rbx,2), %ecx +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(%rax,%rbx,2), %rcx diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/resources-lzcnt.s b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-lzcnt.s new file mode 100644 index 00000000000..6ac0945d4d8 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-lzcnt.s @@ -0,0 +1,50 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +lzcntw %cx, %cx +lzcntw (%rax), %cx + +lzcntl %eax, %ecx +lzcntl (%rax), %ecx + +lzcntq %rax, %rcx +lzcntq (%rax), %rcx + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 lzcntw %cx, %cx +# CHECK-NEXT: 2 8 1.00 * lzcntw (%rax), %cx +# CHECK-NEXT: 1 3 1.00 lzcntl %eax, %ecx +# CHECK-NEXT: 2 8 1.00 * lzcntl (%rax), %ecx +# CHECK-NEXT: 1 3 1.00 lzcntq %rax, %rcx +# CHECK-NEXT: 2 8 1.00 * lzcntq (%rax), %rcx + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - - 6.00 - - 1.50 1.50 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - - - - lzcntw %cx, %cx +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 lzcntw (%rax), %cx +# CHECK-NEXT: - - - 1.00 - - - - lzcntl %eax, %ecx +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 lzcntl (%rax), %ecx +# CHECK-NEXT: - - - 1.00 - - - - lzcntq %rax, %rcx +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 lzcntq (%rax), %rcx diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/resources-mmx.s b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-mmx.s new file mode 100644 index 00000000000..8c9644b6494 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-mmx.s @@ -0,0 +1,393 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +emms + +movd %eax, %mm2 +movd (%rax), %mm2 + +movd %mm0, %ecx +movd %mm0, (%rax) + +movq %rax, %mm2 +movq (%rax), %mm2 + +movq %mm0, %rcx +movq %mm0, (%rax) + +packsswb %mm0, %mm2 +packsswb (%rax), %mm2 + +packssdw %mm0, %mm2 +packssdw (%rax), %mm2 + +packuswb %mm0, %mm2 +packuswb (%rax), %mm2 + +paddb %mm0, %mm2 +paddb (%rax), %mm2 + +paddd %mm0, %mm2 +paddd (%rax), %mm2 + +paddsb %mm0, %mm2 +paddsb (%rax), %mm2 + +paddsw %mm0, %mm2 +paddsw (%rax), %mm2 + +paddusb %mm0, %mm2 +paddusb (%rax), %mm2 + +paddusw %mm0, %mm2 +paddusw (%rax), %mm2 + +paddw %mm0, %mm2 +paddw (%rax), %mm2 + +pand %mm0, %mm2 +pand (%rax), %mm2 + +pandn %mm0, %mm2 +pandn (%rax), %mm2 + +pcmpeqb %mm0, %mm2 +pcmpeqb (%rax), %mm2 + +pcmpeqd %mm0, %mm2 +pcmpeqd (%rax), %mm2 + +pcmpeqw %mm0, %mm2 +pcmpeqw (%rax), %mm2 + +pcmpgtb %mm0, %mm2 +pcmpgtb (%rax), %mm2 + +pcmpgtd %mm0, %mm2 +pcmpgtd (%rax), %mm2 + +pcmpgtw %mm0, %mm2 +pcmpgtw (%rax), %mm2 + +pmaddwd %mm0, %mm2 +pmaddwd (%rax), %mm2 + +pmulhw %mm0, %mm2 +pmulhw (%rax), %mm2 + +pmullw %mm0, %mm2 +pmullw (%rax), %mm2 + +por %mm0, %mm2 +por (%rax), %mm2 + +pslld $1, %mm2 +pslld %mm0, %mm2 +pslld (%rax), %mm2 + +psllq $1, %mm2 +psllq %mm0, %mm2 +psllq (%rax), %mm2 + +psllw $1, %mm2 +psllw %mm0, %mm2 +psllw (%rax), %mm2 + +psrad $1, %mm2 +psrad %mm0, %mm2 +psrad (%rax), %mm2 + +psraw $1, %mm2 +psraw %mm0, %mm2 +psraw (%rax), %mm2 + +psrld $1, %mm2 +psrld %mm0, %mm2 +psrld (%rax), %mm2 + +psrlq $1, %mm2 +psrlq %mm0, %mm2 +psrlq (%rax), %mm2 + +psrlw $1, %mm2 +psrlw %mm0, %mm2 +psrlw (%rax), %mm2 + +psubb %mm0, %mm2 +psubb (%rax), %mm2 + +psubd %mm0, %mm2 +psubd (%rax), %mm2 + +psubsb %mm0, %mm2 +psubsb (%rax), %mm2 + +psubsw %mm0, %mm2 +psubsw (%rax), %mm2 + +psubusb %mm0, %mm2 +psubusb (%rax), %mm2 + +psubusw %mm0, %mm2 +psubusw (%rax), %mm2 + +psubw %mm0, %mm2 +psubw (%rax), %mm2 + +punpckhbw %mm0, %mm2 +punpckhbw (%rax), %mm2 + +punpckhdq %mm0, %mm2 +punpckhdq (%rax), %mm2 + +punpckhwd %mm0, %mm2 +punpckhwd (%rax), %mm2 + +punpcklbw %mm0, %mm2 +punpcklbw (%rax), %mm2 + +punpckldq %mm0, %mm2 +punpckldq (%rax), %mm2 + +punpcklwd %mm0, %mm2 +punpcklwd (%rax), %mm2 + +pxor %mm0, %mm2 +pxor (%rax), %mm2 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 31 31 10.33 * * U emms +# CHECK-NEXT: 1 1 1.00 movd %eax, %mm2 +# CHECK-NEXT: 1 5 0.50 * movd (%rax), %mm2 +# CHECK-NEXT: 1 2 1.00 movd %mm0, %ecx +# CHECK-NEXT: 1 1 1.00 * U movd %mm0, (%rax) +# CHECK-NEXT: 1 1 1.00 movq %rax, %mm2 +# CHECK-NEXT: 1 5 0.50 * movq (%rax), %mm2 +# CHECK-NEXT: 1 2 1.00 movq %mm0, %rcx +# CHECK-NEXT: 1 1 1.00 * movq %mm0, (%rax) +# CHECK-NEXT: 1 1 1.00 packsswb %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * packsswb (%rax), %mm2 +# CHECK-NEXT: 1 1 1.00 packssdw %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * packssdw (%rax), %mm2 +# CHECK-NEXT: 1 1 1.00 packuswb %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * packuswb (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 paddb %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * paddb (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 paddd %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * paddd (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 paddsb %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * paddsb (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 paddsw %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * paddsw (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 paddusb %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * paddusb (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 paddusw %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * paddusw (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 paddw %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * paddw (%rax), %mm2 +# CHECK-NEXT: 1 1 0.33 pand %mm0, %mm2 +# CHECK-NEXT: 2 6 0.50 * pand (%rax), %mm2 +# CHECK-NEXT: 1 1 0.33 pandn %mm0, %mm2 +# CHECK-NEXT: 2 6 0.50 * pandn (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pcmpeqb %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * pcmpeqb (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pcmpeqd %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * pcmpeqd (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pcmpeqw %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * pcmpeqw (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pcmpgtb %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * pcmpgtb (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pcmpgtd %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * pcmpgtd (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pcmpgtw %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * pcmpgtw (%rax), %mm2 +# CHECK-NEXT: 1 5 1.00 pmaddwd %mm0, %mm2 +# CHECK-NEXT: 2 10 1.00 * pmaddwd (%rax), %mm2 +# CHECK-NEXT: 1 5 1.00 pmulhw %mm0, %mm2 +# CHECK-NEXT: 2 10 1.00 * pmulhw (%rax), %mm2 +# CHECK-NEXT: 1 5 1.00 pmullw %mm0, %mm2 +# CHECK-NEXT: 2 10 1.00 * pmullw (%rax), %mm2 +# CHECK-NEXT: 1 1 0.33 por %mm0, %mm2 +# CHECK-NEXT: 2 6 0.50 * por (%rax), %mm2 +# CHECK-NEXT: 1 1 1.00 pslld $1, %mm2 +# CHECK-NEXT: 1 1 1.00 pslld %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * pslld (%rax), %mm2 +# CHECK-NEXT: 1 1 1.00 psllq $1, %mm2 +# CHECK-NEXT: 1 1 1.00 psllq %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * psllq (%rax), %mm2 +# CHECK-NEXT: 1 1 1.00 psllw $1, %mm2 +# CHECK-NEXT: 1 1 1.00 psllw %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * psllw (%rax), %mm2 +# CHECK-NEXT: 1 1 1.00 psrad $1, %mm2 +# CHECK-NEXT: 1 1 1.00 psrad %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * psrad (%rax), %mm2 +# CHECK-NEXT: 1 1 1.00 psraw $1, %mm2 +# CHECK-NEXT: 1 1 1.00 psraw %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * psraw (%rax), %mm2 +# CHECK-NEXT: 1 1 1.00 psrld $1, %mm2 +# CHECK-NEXT: 1 1 1.00 psrld %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * psrld (%rax), %mm2 +# CHECK-NEXT: 1 1 1.00 psrlq $1, %mm2 +# CHECK-NEXT: 1 1 1.00 psrlq %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * psrlq (%rax), %mm2 +# CHECK-NEXT: 1 1 1.00 psrlw $1, %mm2 +# CHECK-NEXT: 1 1 1.00 psrlw %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * psrlw (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 psubb %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * psubb (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 psubd %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * psubd (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 psubsb %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * psubsb (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 psubsw %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * psubsw (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 psubusb %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * psubusb (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 psubusw %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * psubusw (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 psubw %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * psubw (%rax), %mm2 +# CHECK-NEXT: 1 1 1.00 punpckhbw %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * punpckhbw (%rax), %mm2 +# CHECK-NEXT: 1 1 1.00 punpckhdq %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * punpckhdq (%rax), %mm2 +# CHECK-NEXT: 1 1 1.00 punpckhwd %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * punpckhwd (%rax), %mm2 +# CHECK-NEXT: 1 1 1.00 punpcklbw %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * punpcklbw (%rax), %mm2 +# CHECK-NEXT: 1 1 1.00 punpckldq %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * punpckldq (%rax), %mm2 +# CHECK-NEXT: 1 1 1.00 punpcklwd %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * punpcklwd (%rax), %mm2 +# CHECK-NEXT: 1 1 0.33 pxor %mm0, %mm2 +# CHECK-NEXT: 2 6 0.50 * pxor (%rax), %mm2 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 21.00 53.00 2.00 57.00 24.00 24.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 10.33 10.33 - 10.33 - - emms +# CHECK-NEXT: - - - - - 1.00 - - movd %eax, %mm2 +# CHECK-NEXT: - - - - - - 0.50 0.50 movd (%rax), %mm2 +# CHECK-NEXT: - - 1.00 - - - - - movd %mm0, %ecx +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movd %mm0, (%rax) +# CHECK-NEXT: - - - - - 1.00 - - movq %rax, %mm2 +# CHECK-NEXT: - - - - - - 0.50 0.50 movq (%rax), %mm2 +# CHECK-NEXT: - - 1.00 - - - - - movq %mm0, %rcx +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movq %mm0, (%rax) +# CHECK-NEXT: - - - - - 1.00 - - packsswb %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 packsswb (%rax), %mm2 +# CHECK-NEXT: - - - - - 1.00 - - packssdw %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 packssdw (%rax), %mm2 +# CHECK-NEXT: - - - - - 1.00 - - packuswb %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 packuswb (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - paddb %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 paddb (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - paddd %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 paddd (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - paddsb %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 paddsb (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - paddsw %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 paddsw (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - paddusb %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 paddusb (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - paddusw %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 paddusw (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - paddw %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 paddw (%rax), %mm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - pand %mm0, %mm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 pand (%rax), %mm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - pandn %mm0, %mm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 pandn (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pcmpeqb %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pcmpeqb (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pcmpeqd %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pcmpeqd (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pcmpeqw %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pcmpeqw (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pcmpgtb %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pcmpgtb (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pcmpgtd %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pcmpgtd (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pcmpgtw %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pcmpgtw (%rax), %mm2 +# CHECK-NEXT: - - 1.00 - - - - - pmaddwd %mm0, %mm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmaddwd (%rax), %mm2 +# CHECK-NEXT: - - 1.00 - - - - - pmulhw %mm0, %mm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmulhw (%rax), %mm2 +# CHECK-NEXT: - - 1.00 - - - - - pmullw %mm0, %mm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmullw (%rax), %mm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - por %mm0, %mm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 por (%rax), %mm2 +# CHECK-NEXT: - - - - - 1.00 - - pslld $1, %mm2 +# CHECK-NEXT: - - - - - 1.00 - - pslld %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 pslld (%rax), %mm2 +# CHECK-NEXT: - - - - - 1.00 - - psllq $1, %mm2 +# CHECK-NEXT: - - - - - 1.00 - - psllq %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 psllq (%rax), %mm2 +# CHECK-NEXT: - - - - - 1.00 - - psllw $1, %mm2 +# CHECK-NEXT: - - - - - 1.00 - - psllw %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 psllw (%rax), %mm2 +# CHECK-NEXT: - - - - - 1.00 - - psrad $1, %mm2 +# CHECK-NEXT: - - - - - 1.00 - - psrad %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 psrad (%rax), %mm2 +# CHECK-NEXT: - - - - - 1.00 - - psraw $1, %mm2 +# CHECK-NEXT: - - - - - 1.00 - - psraw %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 psraw (%rax), %mm2 +# CHECK-NEXT: - - - - - 1.00 - - psrld $1, %mm2 +# CHECK-NEXT: - - - - - 1.00 - - psrld %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 psrld (%rax), %mm2 +# CHECK-NEXT: - - - - - 1.00 - - psrlq $1, %mm2 +# CHECK-NEXT: - - - - - 1.00 - - psrlq %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 psrlq (%rax), %mm2 +# CHECK-NEXT: - - - - - 1.00 - - psrlw $1, %mm2 +# CHECK-NEXT: - - - - - 1.00 - - psrlw %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 psrlw (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - psubb %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 psubb (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - psubd %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 psubd (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - psubsb %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 psubsb (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - psubsw %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 psubsw (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - psubusb %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 psubusb (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - psubusw %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 psubusw (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - psubw %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 psubw (%rax), %mm2 +# CHECK-NEXT: - - - - - 1.00 - - punpckhbw %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 punpckhbw (%rax), %mm2 +# CHECK-NEXT: - - - - - 1.00 - - punpckhdq %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 punpckhdq (%rax), %mm2 +# CHECK-NEXT: - - - - - 1.00 - - punpckhwd %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 punpckhwd (%rax), %mm2 +# CHECK-NEXT: - - - - - 1.00 - - punpcklbw %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 punpcklbw (%rax), %mm2 +# CHECK-NEXT: - - - - - 1.00 - - punpckldq %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 punpckldq (%rax), %mm2 +# CHECK-NEXT: - - - - - 1.00 - - punpcklwd %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 punpcklwd (%rax), %mm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - pxor %mm0, %mm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 pxor (%rax), %mm2 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/resources-movbe.s b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-movbe.s new file mode 100644 index 00000000000..aa8641484e1 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-movbe.s @@ -0,0 +1,50 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +movbe %cx, (%rax) +movbe (%rax), %cx + +movbe %ecx, (%rax) +movbe (%rax), %ecx + +movbe %rcx, (%rax) +movbe (%rax), %rcx + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 1.00 * movbew %cx, (%rax) +# CHECK-NEXT: 2 6 0.50 * movbew (%rax), %cx +# CHECK-NEXT: 1 1 1.00 * movbel %ecx, (%rax) +# CHECK-NEXT: 2 6 0.50 * movbel (%rax), %ecx +# CHECK-NEXT: 1 1 1.00 * movbeq %rcx, (%rax) +# CHECK-NEXT: 2 6 0.50 * movbeq (%rax), %rcx + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 1.00 1.00 3.00 1.00 3.00 3.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movbew %cx, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 movbew (%rax), %cx +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movbel %ecx, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 movbel (%rax), %ecx +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movbeq %rcx, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 movbeq (%rax), %rcx diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/resources-pclmul.s b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-pclmul.s new file mode 100644 index 00000000000..12f879b5fb0 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-pclmul.s @@ -0,0 +1,36 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +pclmulqdq $11, %xmm0, %xmm2 +pclmulqdq $11, (%rax), %xmm2 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 14 6.00 pclmulqdq $11, %xmm0, %xmm2 +# CHECK-NEXT: 1 14 5.67 * pclmulqdq $11, (%rax), %xmm2 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 11.67 11.67 - 11.67 0.50 0.50 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 6.00 6.00 - 6.00 - - pclmulqdq $11, %xmm0, %xmm2 +# CHECK-NEXT: - - 5.67 5.67 - 5.67 0.50 0.50 pclmulqdq $11, (%rax), %xmm2 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/resources-popcnt.s b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-popcnt.s new file mode 100644 index 00000000000..c24ce8869f9 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-popcnt.s @@ -0,0 +1,50 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +popcntw %cx, %cx +popcntw (%rax), %cx + +popcntl %eax, %ecx +popcntl (%rax), %ecx + +popcntq %rax, %rcx +popcntq (%rax), %rcx + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 popcntw %cx, %cx +# CHECK-NEXT: 2 9 1.00 * popcntw (%rax), %cx +# CHECK-NEXT: 1 3 1.00 popcntl %eax, %ecx +# CHECK-NEXT: 2 9 1.00 * popcntl (%rax), %ecx +# CHECK-NEXT: 1 3 1.00 popcntq %rax, %rcx +# CHECK-NEXT: 2 9 1.00 * popcntq (%rax), %rcx + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - - 6.00 - - 1.50 1.50 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - - - - popcntw %cx, %cx +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 popcntw (%rax), %cx +# CHECK-NEXT: - - - 1.00 - - - - popcntl %eax, %ecx +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 popcntl (%rax), %ecx +# CHECK-NEXT: - - - 1.00 - - - - popcntq %rax, %rcx +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 popcntq (%rax), %rcx diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/resources-prefetchw.s b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-prefetchw.s new file mode 100644 index 00000000000..b44b28c3725 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-prefetchw.s @@ -0,0 +1,36 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +prefetch (%rax) +prefetchw (%rax) + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 5 0.50 * * prefetch (%rax) +# CHECK-NEXT: 1 5 0.50 * * prefetchw (%rax) + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - - - - - 1.00 1.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - - - - 0.50 0.50 prefetch (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 prefetchw (%rax) diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/resources-sse1.s b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-sse1.s new file mode 100644 index 00000000000..cc4d6ed0b43 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-sse1.s @@ -0,0 +1,461 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +addps %xmm0, %xmm2 +addps (%rax), %xmm2 + +addss %xmm0, %xmm2 +addss (%rax), %xmm2 + +andnps %xmm0, %xmm2 +andnps (%rax), %xmm2 + +andps %xmm0, %xmm2 +andps (%rax), %xmm2 + +cmpps $0, %xmm0, %xmm2 +cmpps $0, (%rax), %xmm2 + +cmpss $0, %xmm0, %xmm2 +cmpss $0, (%rax), %xmm2 + +comiss %xmm0, %xmm1 +comiss (%rax), %xmm1 + +cvtpi2ps %mm0, %xmm2 +cvtpi2ps (%rax), %xmm2 + +cvtps2pi %xmm0, %mm2 +cvtps2pi (%rax), %mm2 + +cvtsi2ss %ecx, %xmm2 +cvtsi2ss %rcx, %xmm2 +cvtsi2ss (%rax), %xmm2 +cvtsi2ss (%rax), %xmm2 + +cvtss2si %xmm0, %ecx +cvtss2si %xmm0, %rcx +cvtss2si (%rax), %ecx +cvtss2si (%rax), %rcx + +cvttps2pi %xmm0, %mm2 +cvttps2pi (%rax), %mm2 + +cvttss2si %xmm0, %ecx +cvttss2si %xmm0, %rcx +cvttss2si (%rax), %ecx +cvttss2si (%rax), %rcx + +divps %xmm0, %xmm2 +divps (%rax), %xmm2 + +divss %xmm0, %xmm2 +divss (%rax), %xmm2 + +ldmxcsr (%rax) + +maskmovq %mm0, %mm1 + +maxps %xmm0, %xmm2 +maxps (%rax), %xmm2 + +maxss %xmm0, %xmm2 +maxss (%rax), %xmm2 + +minps %xmm0, %xmm2 +minps (%rax), %xmm2 + +minss %xmm0, %xmm2 +minss (%rax), %xmm2 + +movaps %xmm0, %xmm2 +movaps %xmm0, (%rax) +movaps (%rax), %xmm2 + +movhlps %xmm0, %xmm2 +movlhps %xmm0, %xmm2 + +movhps %xmm0, (%rax) +movhps (%rax), %xmm2 + +movlps %xmm0, (%rax) +movlps (%rax), %xmm2 + +movmskps %xmm0, %rcx + +movntps %xmm0, (%rax) +movntq %mm0, (%rax) + +movss %xmm0, %xmm2 +movss %xmm0, (%rax) +movss (%rax), %xmm2 + +movups %xmm0, %xmm2 +movups %xmm0, (%rax) +movups (%rax), %xmm2 + +mulps %xmm0, %xmm2 +mulps (%rax), %xmm2 + +mulss %xmm0, %xmm2 +mulss (%rax), %xmm2 + +orps %xmm0, %xmm2 +orps (%rax), %xmm2 + +pavgb %mm0, %mm2 +pavgb (%rax), %mm2 + +pavgw %mm0, %mm2 +pavgw (%rax), %mm2 + +pextrw $1, %mm0, %rcx + +pinsrw $1, %rax, %mm2 +pinsrw $1, (%rax), %mm2 + +pmaxsw %mm0, %mm2 +pmaxsw (%rax), %mm2 + +pmaxub %mm0, %mm2 +pmaxub (%rax), %mm2 + +pminsw %mm0, %mm2 +pminsw (%rax), %mm2 + +pminub %mm0, %mm2 +pminub (%rax), %mm2 + +pmovmskb %xmm0, %rcx + +pmulhuw %mm0, %mm2 +pmulhuw (%rax), %mm2 + +prefetcht0 (%rax) +prefetcht1 (%rax) +prefetcht2 (%rax) +prefetchnta (%rax) + +psadbw %mm0, %mm2 +psadbw (%rax), %mm2 + +pshufw $1, %mm0, %mm2 +pshufw $1, (%rax), %mm2 + +rcpps %xmm0, %xmm2 +rcpps (%rax), %xmm2 + +rcpss %xmm0, %xmm2 +rcpss (%rax), %xmm2 + +rsqrtps %xmm0, %xmm2 +rsqrtps (%rax), %xmm2 + +rsqrtss %xmm0, %xmm2 +rsqrtss (%rax), %xmm2 + +sfence + +shufps $1, %xmm0, %xmm2 +shufps $1, (%rax), %xmm2 + +sqrtps %xmm0, %xmm2 +sqrtps (%rax), %xmm2 + +sqrtss %xmm0, %xmm2 +sqrtss (%rax), %xmm2 + +stmxcsr (%rax) + +subps %xmm0, %xmm2 +subps (%rax), %xmm2 + +subss %xmm0, %xmm2 +subss (%rax), %xmm2 + +ucomiss %xmm0, %xmm1 +ucomiss (%rax), %xmm1 + +unpckhps %xmm0, %xmm2 +unpckhps (%rax), %xmm2 + +unpcklps %xmm0, %xmm2 +unpcklps (%rax), %xmm2 + +xorps %xmm0, %xmm2 +xorps (%rax), %xmm2 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * addps (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 addss %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * addss (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 andnps %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * andnps (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 andps %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * andps (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 cmpps $0, %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * cmpps $0, (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 cmpss $0, %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * cmpss $0, (%rax), %xmm2 +# CHECK-NEXT: 2 2 1.00 comiss %xmm0, %xmm1 +# CHECK-NEXT: 3 8 1.00 * comiss (%rax), %xmm1 +# CHECK-NEXT: 1 3 1.00 cvtpi2ps %mm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * cvtpi2ps (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 cvtps2pi %xmm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * cvtps2pi (%rax), %mm2 +# CHECK-NEXT: 3 5 2.00 cvtsi2ssl %ecx, %xmm2 +# CHECK-NEXT: 3 5 2.00 cvtsi2ssq %rcx, %xmm2 +# CHECK-NEXT: 3 10 1.00 * cvtsi2ssl (%rax), %xmm2 +# CHECK-NEXT: 3 10 1.00 * cvtsi2ssl (%rax), %xmm2 +# CHECK-NEXT: 2 5 1.00 cvtss2si %xmm0, %ecx +# CHECK-NEXT: 2 5 1.00 cvtss2si %xmm0, %rcx +# CHECK-NEXT: 3 9 1.00 * cvtss2si (%rax), %ecx +# CHECK-NEXT: 3 9 1.00 * cvtss2si (%rax), %rcx +# CHECK-NEXT: 1 3 1.00 cvttps2pi %xmm0, %mm2 +# CHECK-NEXT: 2 9 1.00 * cvttps2pi (%rax), %mm2 +# CHECK-NEXT: 2 5 1.00 cvttss2si %xmm0, %ecx +# CHECK-NEXT: 2 5 1.00 cvttss2si %xmm0, %rcx +# CHECK-NEXT: 3 9 1.00 * cvttss2si (%rax), %ecx +# CHECK-NEXT: 3 9 1.00 * cvttss2si (%rax), %rcx +# CHECK-NEXT: 1 14 14.00 divps %xmm0, %xmm2 +# CHECK-NEXT: 2 20 14.00 * divps (%rax), %xmm2 +# CHECK-NEXT: 1 14 14.00 divss %xmm0, %xmm2 +# CHECK-NEXT: 2 20 14.00 * divss (%rax), %xmm2 +# CHECK-NEXT: 4 5 1.00 * * U ldmxcsr (%rax) +# CHECK-NEXT: 1 1 1.00 * * U maskmovq %mm0, %mm1 +# CHECK-NEXT: 1 3 1.00 maxps %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * maxps (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 maxss %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * maxss (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 minps %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * minps (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 minss %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * minss (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 movaps %xmm0, %xmm2 +# CHECK-NEXT: 1 1 1.00 * movaps %xmm0, (%rax) +# CHECK-NEXT: 1 6 0.50 * movaps (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 movhlps %xmm0, %xmm2 +# CHECK-NEXT: 1 1 1.00 movlhps %xmm0, %xmm2 +# CHECK-NEXT: 1 1 1.00 * movhps %xmm0, (%rax) +# CHECK-NEXT: 2 7 1.00 * movhps (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 * movlps %xmm0, (%rax) +# CHECK-NEXT: 2 7 1.00 * movlps (%rax), %xmm2 +# CHECK-NEXT: 1 2 1.00 movmskps %xmm0, %ecx +# CHECK-NEXT: 1 1 1.00 * movntps %xmm0, (%rax) +# CHECK-NEXT: 1 1 1.00 * * U movntq %mm0, (%rax) +# CHECK-NEXT: 1 1 1.00 movss %xmm0, %xmm2 +# CHECK-NEXT: 1 1 1.00 * movss %xmm0, (%rax) +# CHECK-NEXT: 1 6 0.50 * movss (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 movups %xmm0, %xmm2 +# CHECK-NEXT: 1 1 1.00 * movups %xmm0, (%rax) +# CHECK-NEXT: 1 6 0.50 * movups (%rax), %xmm2 +# CHECK-NEXT: 1 5 1.00 mulps %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * mulps (%rax), %xmm2 +# CHECK-NEXT: 1 5 1.00 mulss %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * mulss (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 orps %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * orps (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 pavgb %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * pavgb (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pavgw %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * pavgw (%rax), %mm2 +# CHECK-NEXT: 2 3 1.00 pextrw $1, %mm0, %ecx +# CHECK-NEXT: 2 2 1.00 pinsrw $1, %eax, %mm2 +# CHECK-NEXT: 2 7 0.50 * pinsrw $1, (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pmaxsw %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * pmaxsw (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pmaxub %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * pmaxub (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pminsw %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * pminsw (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 pminub %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * pminub (%rax), %mm2 +# CHECK-NEXT: 1 2 1.00 pmovmskb %xmm0, %ecx +# CHECK-NEXT: 1 5 1.00 pmulhuw %mm0, %mm2 +# CHECK-NEXT: 2 10 1.00 * pmulhuw (%rax), %mm2 +# CHECK-NEXT: 1 5 0.50 * * prefetcht0 (%rax) +# CHECK-NEXT: 1 5 0.50 * * prefetcht1 (%rax) +# CHECK-NEXT: 1 5 0.50 * * prefetcht2 (%rax) +# CHECK-NEXT: 1 5 0.50 * * prefetchnta (%rax) +# CHECK-NEXT: 1 5 1.00 psadbw %mm0, %mm2 +# CHECK-NEXT: 2 10 1.00 * psadbw (%rax), %mm2 +# CHECK-NEXT: 1 1 1.00 pshufw $1, %mm0, %mm2 +# CHECK-NEXT: 2 6 1.00 * pshufw $1, (%rax), %mm2 +# CHECK-NEXT: 1 5 1.00 rcpps %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * rcpps (%rax), %xmm2 +# CHECK-NEXT: 1 5 1.00 rcpss %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * rcpss (%rax), %xmm2 +# CHECK-NEXT: 1 5 1.00 rsqrtps %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * rsqrtps (%rax), %xmm2 +# CHECK-NEXT: 1 5 1.00 rsqrtss %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * rsqrtss (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 * * U sfence +# CHECK-NEXT: 1 1 1.00 shufps $1, %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * shufps $1, (%rax), %xmm2 +# CHECK-NEXT: 1 14 14.00 sqrtps %xmm0, %xmm2 +# CHECK-NEXT: 2 20 14.00 * sqrtps (%rax), %xmm2 +# CHECK-NEXT: 1 14 14.00 sqrtss %xmm0, %xmm2 +# CHECK-NEXT: 2 20 14.00 * sqrtss (%rax), %xmm2 +# CHECK-NEXT: 4 5 1.00 * * U stmxcsr (%rax) +# CHECK-NEXT: 1 3 1.00 subps %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * subps (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 subss %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * subss (%rax), %xmm2 +# CHECK-NEXT: 2 2 1.00 ucomiss %xmm0, %xmm1 +# CHECK-NEXT: 3 8 1.00 * ucomiss (%rax), %xmm1 +# CHECK-NEXT: 1 1 1.00 unpckhps %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * unpckhps (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 unpcklps %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * unpcklps (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 xorps %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * xorps (%rax), %xmm2 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - 112.00 41.00 55.50 10.00 34.50 33.50 33.50 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - - - - addps %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 addps (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - addss %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 addss (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - andnps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 andnps (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - andps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 andps (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - cmpps $0, %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cmpps $0, (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - cmpss $0, %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cmpss $0, (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 1.00 - - - - comiss %xmm0, %xmm1 +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 comiss (%rax), %xmm1 +# CHECK-NEXT: - - - 1.00 - - - - cvtpi2ps %mm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cvtpi2ps (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - cvtps2pi %xmm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cvtps2pi (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - 2.00 - - cvtsi2ssl %ecx, %xmm2 +# CHECK-NEXT: - - - 1.00 - 2.00 - - cvtsi2ssq %rcx, %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 cvtsi2ssl (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 cvtsi2ssl (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 1.00 - - - - cvtss2si %xmm0, %ecx +# CHECK-NEXT: - - 1.00 1.00 - - - - cvtss2si %xmm0, %rcx +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 cvtss2si (%rax), %ecx +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 cvtss2si (%rax), %rcx +# CHECK-NEXT: - - - 1.00 - - - - cvttps2pi %xmm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cvttps2pi (%rax), %mm2 +# CHECK-NEXT: - - 1.00 1.00 - - - - cvttss2si %xmm0, %ecx +# CHECK-NEXT: - - 1.00 1.00 - - - - cvttss2si %xmm0, %rcx +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 cvttss2si (%rax), %ecx +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 cvttss2si (%rax), %rcx +# CHECK-NEXT: - 14.00 1.00 - - - - - divps %xmm0, %xmm2 +# CHECK-NEXT: - 14.00 1.00 - - - 0.50 0.50 divps (%rax), %xmm2 +# CHECK-NEXT: - 14.00 1.00 - - - - - divss %xmm0, %xmm2 +# CHECK-NEXT: - 14.00 1.00 - - - 0.50 0.50 divss (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - 1.00 1.00 0.50 0.50 ldmxcsr (%rax) +# CHECK-NEXT: - - - - - 1.00 - - maskmovq %mm0, %mm1 +# CHECK-NEXT: - - - 1.00 - - - - maxps %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 maxps (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - maxss %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 maxss (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - minps %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 minps (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - minss %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 minss (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - movaps %xmm0, %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movaps %xmm0, (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 movaps (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - movhlps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - movlhps %xmm0, %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movhps %xmm0, (%rax) +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 movhps (%rax), %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movlps %xmm0, (%rax) +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 movlps (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - movmskps %xmm0, %ecx +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movntps %xmm0, (%rax) +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movntq %mm0, (%rax) +# CHECK-NEXT: - - - - - 1.00 - - movss %xmm0, %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movss %xmm0, (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 movss (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - movups %xmm0, %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movups %xmm0, (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 movups (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - mulps %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 mulps (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - mulss %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 mulss (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - orps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 orps (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - pavgb %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pavgb (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pavgw %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pavgw (%rax), %mm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - pextrw $1, %mm0, %ecx +# CHECK-NEXT: - - - 0.50 - 1.50 - - pinsrw $1, %eax, %mm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pinsrw $1, (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pmaxsw %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pmaxsw (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pmaxub %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pmaxub (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pminsw %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pminsw (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pminub %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pminub (%rax), %mm2 +# CHECK-NEXT: - - 1.00 - - - - - pmovmskb %xmm0, %ecx +# CHECK-NEXT: - - 1.00 - - - - - pmulhuw %mm0, %mm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmulhuw (%rax), %mm2 +# CHECK-NEXT: - - - - - - 0.50 0.50 prefetcht0 (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 prefetcht1 (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 prefetcht2 (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 prefetchnta (%rax) +# CHECK-NEXT: - - 1.00 - - - - - psadbw %mm0, %mm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 psadbw (%rax), %mm2 +# CHECK-NEXT: - - - - - 1.00 - - pshufw $1, %mm0, %mm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 pshufw $1, (%rax), %mm2 +# CHECK-NEXT: - - 1.00 - - - - - rcpps %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 rcpps (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - rcpss %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 rcpss (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - rsqrtps %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 rsqrtps (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - rsqrtss %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 rsqrtss (%rax), %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 sfence +# CHECK-NEXT: - - - - - 1.00 - - shufps $1, %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 shufps $1, (%rax), %xmm2 +# CHECK-NEXT: - 14.00 1.00 - - - - - sqrtps %xmm0, %xmm2 +# CHECK-NEXT: - 14.00 1.00 - - - 0.50 0.50 sqrtps (%rax), %xmm2 +# CHECK-NEXT: - 14.00 1.00 - - - - - sqrtss %xmm0, %xmm2 +# CHECK-NEXT: - 14.00 1.00 - - - 0.50 0.50 sqrtss (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - 1.00 1.00 0.50 0.50 stmxcsr (%rax) +# CHECK-NEXT: - - - 1.00 - - - - subps %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 subps (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - subss %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 subss (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 1.00 - - - - ucomiss %xmm0, %xmm1 +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 ucomiss (%rax), %xmm1 +# CHECK-NEXT: - - - - - 1.00 - - unpckhps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 unpckhps (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - unpcklps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 unpcklps (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - xorps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 xorps (%rax), %xmm2 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/resources-sse2.s b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-sse2.s new file mode 100644 index 00000000000..30534807cb3 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-sse2.s @@ -0,0 +1,949 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +addpd %xmm0, %xmm2 +addpd (%rax), %xmm2 + +addsd %xmm0, %xmm2 +addsd (%rax), %xmm2 + +andnpd %xmm0, %xmm2 +andnpd (%rax), %xmm2 + +andpd %xmm0, %xmm2 +andpd (%rax), %xmm2 + +clflush (%rax) + +cmppd $0, %xmm0, %xmm2 +cmppd $0, (%rax), %xmm2 + +cmpsd $0, %xmm0, %xmm2 +cmpsd $0, (%rax), %xmm2 + +comisd %xmm0, %xmm1 +comisd (%rax), %xmm1 + +cvtdq2pd %xmm0, %xmm2 +cvtdq2pd (%rax), %xmm2 + +cvtdq2ps %xmm0, %xmm2 +cvtdq2ps (%rax), %xmm2 + +cvtpd2dq %xmm0, %xmm2 +cvtpd2dq (%rax), %xmm2 + +cvtpd2pi %xmm0, %mm2 +cvtpd2pi (%rax), %mm2 + +cvtpd2ps %xmm0, %xmm2 +cvtpd2ps (%rax), %xmm2 + +cvtpi2pd %mm0, %xmm2 +cvtpi2pd (%rax), %xmm2 + +cvtps2dq %xmm0, %xmm2 +cvtps2dq (%rax), %xmm2 + +cvtps2pd %xmm0, %xmm2 +cvtps2pd (%rax), %xmm2 + +cvtsd2si %xmm0, %ecx +cvtsd2si %xmm0, %rcx +cvtsd2si (%rax), %ecx +cvtsd2si (%rax), %rcx + +cvtsd2ss %xmm0, %xmm2 +cvtsd2ss (%rax), %xmm2 + +cvtsi2sd %ecx, %xmm2 +cvtsi2sd %rcx, %xmm2 +cvtsi2sd (%rax), %xmm2 +cvtsi2sd (%rax), %xmm2 + +cvtss2sd %xmm0, %xmm2 +cvtss2sd (%rax), %xmm2 + +cvttpd2dq %xmm0, %xmm2 +cvttpd2dq (%rax), %xmm2 + +cvttpd2pi %xmm0, %mm2 +cvttpd2pi (%rax), %mm2 + +cvttps2dq %xmm0, %xmm2 +cvttps2dq (%rax), %xmm2 + +cvttsd2si %xmm0, %ecx +cvttsd2si %xmm0, %rcx +cvttsd2si (%rax), %ecx +cvttsd2si (%rax), %rcx + +divpd %xmm0, %xmm2 +divpd (%rax), %xmm2 + +divsd %xmm0, %xmm2 +divsd (%rax), %xmm2 + +lfence + +maskmovdqu %xmm0, %xmm1 + +maxpd %xmm0, %xmm2 +maxpd (%rax), %xmm2 + +maxsd %xmm0, %xmm2 +maxsd (%rax), %xmm2 + +minpd %xmm0, %xmm2 +minpd (%rax), %xmm2 + +minsd %xmm0, %xmm2 +minsd (%rax), %xmm2 + +movapd %xmm0, %xmm2 +movapd %xmm0, (%rax) +movapd (%rax), %xmm2 + +movd %eax, %xmm2 +movd (%rax), %xmm2 + +movd %xmm0, %ecx +movd %xmm0, (%rax) + +movdqa %xmm0, %xmm2 +movdqa %xmm0, (%rax) +movdqa (%rax), %xmm2 + +movdqu %xmm0, %xmm2 +movdqu %xmm0, (%rax) +movdqu (%rax), %xmm2 + +movdq2q %xmm0, %mm2 + +movhpd %xmm0, (%rax) +movhpd (%rax), %xmm2 + +movlpd %xmm0, (%rax) +movlpd (%rax), %xmm2 + +movmskpd %xmm0, %rcx + +movntil %eax, (%rax) +movntiq %rax, (%rax) + +movntdq %xmm0, (%rax) +movntpd %xmm0, (%rax) + +movq %xmm0, %xmm2 + +movq %rax, %xmm2 +movq (%rax), %xmm2 + +movq %xmm0, %rcx +movq %xmm0, (%rax) + +movq2dq %mm0, %xmm2 + +movsd %xmm0, %xmm2 +movsd %xmm0, (%rax) +movsd (%rax), %xmm2 + +movupd %xmm0, %xmm2 +movupd %xmm0, (%rax) +movupd (%rax), %xmm2 + +mulpd %xmm0, %xmm2 +mulpd (%rax), %xmm2 + +mulsd %xmm0, %xmm2 +mulsd (%rax), %xmm2 + +orpd %xmm0, %xmm2 +orpd (%rax), %xmm2 + +packssdw %xmm0, %xmm2 +packssdw (%rax), %xmm2 + +packsswb %xmm0, %xmm2 +packsswb (%rax), %xmm2 + +packuswb %xmm0, %xmm2 +packuswb (%rax), %xmm2 + +paddb %xmm0, %xmm2 +paddb (%rax), %xmm2 + +paddd %xmm0, %xmm2 +paddd (%rax), %xmm2 + +paddq %mm0, %mm2 +paddq (%rax), %mm2 + +paddq %xmm0, %xmm2 +paddq (%rax), %xmm2 + +paddsb %xmm0, %xmm2 +paddsb (%rax), %xmm2 + +paddsw %xmm0, %xmm2 +paddsw (%rax), %xmm2 + +paddusb %xmm0, %xmm2 +paddusb (%rax), %xmm2 + +paddusw %xmm0, %xmm2 +paddusw (%rax), %xmm2 + +paddw %xmm0, %xmm2 +paddw (%rax), %xmm2 + +pand %xmm0, %xmm2 +pand (%rax), %xmm2 + +pandn %xmm0, %xmm2 +pandn (%rax), %xmm2 + +pavgb %xmm0, %xmm2 +pavgb (%rax), %xmm2 + +pavgw %xmm0, %xmm2 +pavgw (%rax), %xmm2 + +pcmpeqb %xmm0, %xmm2 +pcmpeqb (%rax), %xmm2 + +pcmpeqd %xmm0, %xmm2 +pcmpeqd (%rax), %xmm2 + +pcmpeqw %xmm0, %xmm2 +pcmpeqw (%rax), %xmm2 + +pcmpgtb %xmm0, %xmm2 +pcmpgtb (%rax), %xmm2 + +pcmpgtd %xmm0, %xmm2 +pcmpgtd (%rax), %xmm2 + +pcmpgtw %xmm0, %xmm2 +pcmpgtw (%rax), %xmm2 + +pextrw $1, %xmm0, %rcx + +pmaddwd %xmm0, %xmm2 +pmaddwd (%rax), %xmm2 + +pmaxsw %xmm0, %xmm2 +pmaxsw (%rax), %xmm2 + +pmaxub %xmm0, %xmm2 +pmaxub (%rax), %xmm2 + +pminsw %xmm0, %xmm2 +pminsw (%rax), %xmm2 + +pminub %xmm0, %xmm2 +pminub (%rax), %xmm2 + +pmovmskb %xmm0, %rcx + +pmulhuw %xmm0, %xmm2 +pmulhuw (%rax), %xmm2 + +pmulhw %xmm0, %xmm2 +pmulhw (%rax), %xmm2 + +pmullw %xmm0, %xmm2 +pmullw (%rax), %xmm2 + +pmuludq %mm0, %mm2 +pmuludq (%rax), %mm2 + +pmuludq %xmm0, %xmm2 +pmuludq (%rax), %xmm2 + +por %xmm0, %xmm2 +por (%rax), %xmm2 + +psadbw %xmm0, %xmm2 +psadbw (%rax), %xmm2 + +pshufd $1, %xmm0, %xmm2 +pshufd $1, (%rax), %xmm2 + +pshufhw $1, %xmm0, %xmm2 +pshufhw $1, (%rax), %xmm2 + +pshuflw $1, %xmm0, %xmm2 +pshuflw $1, (%rax), %xmm2 + +pslld $1, %xmm2 +pslld %xmm0, %xmm2 +pslld (%rax), %xmm2 + +pslldq $1, %xmm2 + +psllq $1, %xmm2 +psllq %xmm0, %xmm2 +psllq (%rax), %xmm2 + +psllw $1, %xmm2 +psllw %xmm0, %xmm2 +psllw (%rax), %xmm2 + +psrad $1, %xmm2 +psrad %xmm0, %xmm2 +psrad (%rax), %xmm2 + +psraw $1, %xmm2 +psraw %xmm0, %xmm2 +psraw (%rax), %xmm2 + +psrld $1, %xmm2 +psrld %xmm0, %xmm2 +psrld (%rax), %xmm2 + +psrldq $1, %xmm2 + +psrlq $1, %xmm2 +psrlq %xmm0, %xmm2 +psrlq (%rax), %xmm2 + +psrlw $1, %xmm2 +psrlw %xmm0, %xmm2 +psrlw (%rax), %xmm2 + +psubb %xmm0, %xmm2 +psubb (%rax), %xmm2 + +psubd %xmm0, %xmm2 +psubd (%rax), %xmm2 + +psubq %mm0, %mm2 +psubq (%rax), %mm2 + +psubq %xmm0, %xmm2 +psubq (%rax), %xmm2 + +psubsb %xmm0, %xmm2 +psubsb (%rax), %xmm2 + +psubsw %xmm0, %xmm2 +psubsw (%rax), %xmm2 + +psubusb %xmm0, %xmm2 +psubusb (%rax), %xmm2 + +psubusw %xmm0, %xmm2 +psubusw (%rax), %xmm2 + +psubw %xmm0, %xmm2 +psubw (%rax), %xmm2 + +punpckhbw %xmm0, %xmm2 +punpckhbw (%rax), %xmm2 + +punpckhdq %xmm0, %xmm2 +punpckhdq (%rax), %xmm2 + +punpckhqdq %xmm0, %xmm2 +punpckhqdq (%rax), %xmm2 + +punpckhwd %xmm0, %xmm2 +punpckhwd (%rax), %xmm2 + +punpcklbw %xmm0, %xmm2 +punpcklbw (%rax), %xmm2 + +punpckldq %xmm0, %xmm2 +punpckldq (%rax), %xmm2 + +punpcklqdq %xmm0, %xmm2 +punpcklqdq (%rax), %xmm2 + +punpcklwd %xmm0, %xmm2 +punpcklwd (%rax), %xmm2 + +pxor %xmm0, %xmm2 +pxor (%rax), %xmm2 + +shufpd $1, %xmm0, %xmm2 +shufpd $1, (%rax), %xmm2 + +sqrtpd %xmm0, %xmm2 +sqrtpd (%rax), %xmm2 + +sqrtsd %xmm0, %xmm2 +sqrtsd (%rax), %xmm2 + +subpd %xmm0, %xmm2 +subpd (%rax), %xmm2 + +subsd %xmm0, %xmm2 +subsd (%rax), %xmm2 + +ucomisd %xmm0, %xmm1 +ucomisd (%rax), %xmm1 + +unpckhpd %xmm0, %xmm2 +unpckhpd (%rax), %xmm2 + +unpcklpd %xmm0, %xmm2 +unpcklpd (%rax), %xmm2 + +xorpd %xmm0, %xmm2 +xorpd (%rax), %xmm2 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 addpd %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * addpd (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 addsd %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * addsd (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 andnpd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * andnpd (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 andpd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * andpd (%rax), %xmm2 +# CHECK-NEXT: 4 5 1.00 * * U clflush (%rax) +# CHECK-NEXT: 1 3 1.00 cmppd $0, %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * cmppd $0, (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 cmpsd $0, %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * cmpsd $0, (%rax), %xmm2 +# CHECK-NEXT: 2 2 1.00 comisd %xmm0, %xmm1 +# CHECK-NEXT: 3 8 1.00 * comisd (%rax), %xmm1 +# CHECK-NEXT: 2 4 1.00 cvtdq2pd %xmm0, %xmm2 +# CHECK-NEXT: 3 10 1.00 * cvtdq2pd (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 cvtdq2ps %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * cvtdq2ps (%rax), %xmm2 +# CHECK-NEXT: 2 4 1.00 cvtpd2dq %xmm0, %xmm2 +# CHECK-NEXT: 3 10 1.00 * cvtpd2dq (%rax), %xmm2 +# CHECK-NEXT: 2 4 1.00 cvtpd2pi %xmm0, %mm2 +# CHECK-NEXT: 3 10 1.00 * cvtpd2pi (%rax), %mm2 +# CHECK-NEXT: 2 4 1.00 cvtpd2ps %xmm0, %xmm2 +# CHECK-NEXT: 3 10 1.00 * cvtpd2ps (%rax), %xmm2 +# CHECK-NEXT: 2 4 1.00 cvtpi2pd %mm0, %xmm2 +# CHECK-NEXT: 3 10 1.00 * cvtpi2pd (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 cvtps2dq %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * cvtps2dq (%rax), %xmm2 +# CHECK-NEXT: 2 2 1.00 cvtps2pd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * cvtps2pd (%rax), %xmm2 +# CHECK-NEXT: 2 5 1.00 cvtsd2si %xmm0, %ecx +# CHECK-NEXT: 2 5 1.00 cvtsd2si %xmm0, %rcx +# CHECK-NEXT: 3 9 1.00 * cvtsd2si (%rax), %ecx +# CHECK-NEXT: 3 9 1.00 * cvtsd2si (%rax), %rcx +# CHECK-NEXT: 2 4 1.00 cvtsd2ss %xmm0, %xmm2 +# CHECK-NEXT: 3 10 1.00 * cvtsd2ss (%rax), %xmm2 +# CHECK-NEXT: 2 4 1.00 cvtsi2sdl %ecx, %xmm2 +# CHECK-NEXT: 2 4 1.00 cvtsi2sdq %rcx, %xmm2 +# CHECK-NEXT: 2 9 1.00 * cvtsi2sdl (%rax), %xmm2 +# CHECK-NEXT: 2 9 1.00 * cvtsi2sdl (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 cvtss2sd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * cvtss2sd (%rax), %xmm2 +# CHECK-NEXT: 2 4 1.00 cvttpd2dq %xmm0, %xmm2 +# CHECK-NEXT: 3 10 1.00 * cvttpd2dq (%rax), %xmm2 +# CHECK-NEXT: 2 4 1.00 cvttpd2pi %xmm0, %mm2 +# CHECK-NEXT: 3 10 1.00 * cvttpd2pi (%rax), %mm2 +# CHECK-NEXT: 1 3 1.00 cvttps2dq %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * cvttps2dq (%rax), %xmm2 +# CHECK-NEXT: 2 5 1.00 cvttsd2si %xmm0, %ecx +# CHECK-NEXT: 2 5 1.00 cvttsd2si %xmm0, %rcx +# CHECK-NEXT: 3 9 1.00 * cvttsd2si (%rax), %ecx +# CHECK-NEXT: 3 9 1.00 * cvttsd2si (%rax), %rcx +# CHECK-NEXT: 1 22 22.00 divpd %xmm0, %xmm2 +# CHECK-NEXT: 2 28 22.00 * divpd (%rax), %xmm2 +# CHECK-NEXT: 1 22 22.00 divsd %xmm0, %xmm2 +# CHECK-NEXT: 2 28 22.00 * divsd (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 * * U lfence +# CHECK-NEXT: 1 1 1.00 * * U maskmovdqu %xmm0, %xmm1 +# CHECK-NEXT: 1 3 1.00 maxpd %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * maxpd (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 maxsd %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * maxsd (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 minpd %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * minpd (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 minsd %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * minsd (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 movapd %xmm0, %xmm2 +# CHECK-NEXT: 1 1 1.00 * movapd %xmm0, (%rax) +# CHECK-NEXT: 1 6 0.50 * movapd (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 movd %eax, %xmm2 +# CHECK-NEXT: 1 6 0.50 * movd (%rax), %xmm2 +# CHECK-NEXT: 1 2 1.00 movd %xmm0, %ecx +# CHECK-NEXT: 1 1 1.00 * movd %xmm0, (%rax) +# CHECK-NEXT: 1 1 0.33 movdqa %xmm0, %xmm2 +# CHECK-NEXT: 1 1 1.00 * movdqa %xmm0, (%rax) +# CHECK-NEXT: 1 6 0.50 * movdqa (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.33 movdqu %xmm0, %xmm2 +# CHECK-NEXT: 1 1 1.00 * movdqu %xmm0, (%rax) +# CHECK-NEXT: 1 6 0.50 * movdqu (%rax), %xmm2 +# CHECK-NEXT: 2 2 1.00 movdq2q %xmm0, %mm2 +# CHECK-NEXT: 1 1 1.00 * movhpd %xmm0, (%rax) +# CHECK-NEXT: 2 7 1.00 * movhpd (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 * movlpd %xmm0, (%rax) +# CHECK-NEXT: 2 7 1.00 * movlpd (%rax), %xmm2 +# CHECK-NEXT: 1 2 1.00 movmskpd %xmm0, %ecx +# CHECK-NEXT: 1 1 1.00 * movntil %eax, (%rax) +# CHECK-NEXT: 1 1 1.00 * movntiq %rax, (%rax) +# CHECK-NEXT: 1 1 1.00 * movntdq %xmm0, (%rax) +# CHECK-NEXT: 1 1 1.00 * movntpd %xmm0, (%rax) +# CHECK-NEXT: 1 1 0.33 movq %xmm0, %xmm2 +# CHECK-NEXT: 1 1 1.00 movq %rax, %xmm2 +# CHECK-NEXT: 1 6 0.50 * movq (%rax), %xmm2 +# CHECK-NEXT: 1 2 1.00 movq %xmm0, %rcx +# CHECK-NEXT: 1 1 1.00 * movq %xmm0, (%rax) +# CHECK-NEXT: 1 1 0.33 movq2dq %mm0, %xmm2 +# CHECK-NEXT: 1 1 1.00 movsd %xmm0, %xmm2 +# CHECK-NEXT: 1 1 1.00 * movsd %xmm0, (%rax) +# CHECK-NEXT: 1 6 0.50 * movsd (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 movupd %xmm0, %xmm2 +# CHECK-NEXT: 1 1 1.00 * movupd %xmm0, (%rax) +# CHECK-NEXT: 1 6 0.50 * movupd (%rax), %xmm2 +# CHECK-NEXT: 1 5 1.00 mulpd %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * mulpd (%rax), %xmm2 +# CHECK-NEXT: 1 5 1.00 mulsd %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * mulsd (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 orpd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * orpd (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 packssdw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * packssdw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 packsswb %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * packsswb (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 packuswb %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * packuswb (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 paddb %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * paddb (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 paddd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * paddd (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 paddq %mm0, %mm2 +# CHECK-NEXT: 2 7 0.50 * paddq (%rax), %mm2 +# CHECK-NEXT: 1 1 0.50 paddq %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * paddq (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 paddsb %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * paddsb (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 paddsw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * paddsw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 paddusb %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * paddusb (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 paddusw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * paddusw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 paddw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * paddw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.33 pand %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pand (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.33 pandn %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pandn (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pavgb %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pavgb (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pavgw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pavgw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pcmpeqb %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pcmpeqb (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pcmpeqd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pcmpeqd (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pcmpeqw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pcmpeqw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pcmpgtb %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pcmpgtb (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pcmpgtd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pcmpgtd (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pcmpgtw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pcmpgtw (%rax), %xmm2 +# CHECK-NEXT: 2 3 1.00 pextrw $1, %xmm0, %ecx +# CHECK-NEXT: 1 5 1.00 pmaddwd %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * pmaddwd (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pmaxsw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pmaxsw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pmaxub %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pmaxub (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pminsw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pminsw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pminub %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pminub (%rax), %xmm2 +# CHECK-NEXT: 1 2 1.00 pmovmskb %xmm0, %ecx +# CHECK-NEXT: 1 5 1.00 pmulhuw %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * pmulhuw (%rax), %xmm2 +# CHECK-NEXT: 1 5 1.00 pmulhw %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * pmulhw (%rax), %xmm2 +# CHECK-NEXT: 1 5 1.00 pmullw %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * pmullw (%rax), %xmm2 +# CHECK-NEXT: 1 5 1.00 pmuludq %mm0, %mm2 +# CHECK-NEXT: 2 10 1.00 * pmuludq (%rax), %mm2 +# CHECK-NEXT: 1 5 1.00 pmuludq %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * pmuludq (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.33 por %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * por (%rax), %xmm2 +# CHECK-NEXT: 1 5 1.00 psadbw %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * psadbw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pshufd $1, %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pshufd $1, (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pshufhw $1, %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pshufhw $1, (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pshuflw $1, %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pshuflw $1, (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 pslld $1, %xmm2 +# CHECK-NEXT: 2 2 1.00 pslld %xmm0, %xmm2 +# CHECK-NEXT: 3 8 1.00 * pslld (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pslldq $1, %xmm2 +# CHECK-NEXT: 1 1 1.00 psllq $1, %xmm2 +# CHECK-NEXT: 2 2 1.00 psllq %xmm0, %xmm2 +# CHECK-NEXT: 3 8 1.00 * psllq (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 psllw $1, %xmm2 +# CHECK-NEXT: 2 2 1.00 psllw %xmm0, %xmm2 +# CHECK-NEXT: 3 8 1.00 * psllw (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 psrad $1, %xmm2 +# CHECK-NEXT: 2 2 1.00 psrad %xmm0, %xmm2 +# CHECK-NEXT: 3 8 1.00 * psrad (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 psraw $1, %xmm2 +# CHECK-NEXT: 2 2 1.00 psraw %xmm0, %xmm2 +# CHECK-NEXT: 3 8 1.00 * psraw (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 psrld $1, %xmm2 +# CHECK-NEXT: 2 2 1.00 psrld %xmm0, %xmm2 +# CHECK-NEXT: 3 8 1.00 * psrld (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 psrldq $1, %xmm2 +# CHECK-NEXT: 1 1 1.00 psrlq $1, %xmm2 +# CHECK-NEXT: 2 2 1.00 psrlq %xmm0, %xmm2 +# CHECK-NEXT: 3 8 1.00 * psrlq (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 psrlw $1, %xmm2 +# CHECK-NEXT: 2 2 1.00 psrlw %xmm0, %xmm2 +# CHECK-NEXT: 3 8 1.00 * psrlw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 psubb %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * psubb (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 psubd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * psubd (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 psubq %mm0, %mm2 +# CHECK-NEXT: 2 8 1.00 * psubq (%rax), %mm2 +# CHECK-NEXT: 1 1 0.50 psubq %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * psubq (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 psubsb %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * psubsb (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 psubsw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * psubsw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 psubusb %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * psubusb (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 psubusw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * psubusw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 psubw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * psubw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 punpckhbw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * punpckhbw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 punpckhdq %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * punpckhdq (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 punpckhqdq %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * punpckhqdq (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 punpckhwd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * punpckhwd (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 punpcklbw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * punpcklbw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 punpckldq %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * punpckldq (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 punpcklqdq %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * punpcklqdq (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 punpcklwd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * punpcklwd (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.33 pxor %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pxor (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 shufpd $1, %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * shufpd $1, (%rax), %xmm2 +# CHECK-NEXT: 1 21 21.00 sqrtpd %xmm0, %xmm2 +# CHECK-NEXT: 2 27 21.00 * sqrtpd (%rax), %xmm2 +# CHECK-NEXT: 1 21 21.00 sqrtsd %xmm0, %xmm2 +# CHECK-NEXT: 2 27 21.00 * sqrtsd (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 subpd %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * subpd (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 subsd %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * subsd (%rax), %xmm2 +# CHECK-NEXT: 2 2 1.00 ucomisd %xmm0, %xmm1 +# CHECK-NEXT: 3 8 1.00 * ucomisd (%rax), %xmm1 +# CHECK-NEXT: 1 1 1.00 unpckhpd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * unpckhpd (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 unpcklpd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * unpcklpd (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 xorpd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * xorpd (%rax), %xmm2 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - 172.00 75.83 117.33 16.00 98.83 66.00 66.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - - - - addpd %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 addpd (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - addsd %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 addsd (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - andnpd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 andnpd (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - andpd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 andpd (%rax), %xmm2 +# CHECK-NEXT: - - 0.50 0.50 1.00 1.00 0.50 0.50 clflush (%rax) +# CHECK-NEXT: - - - 1.00 - - - - cmppd $0, %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cmppd $0, (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - cmpsd $0, %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cmpsd $0, (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 1.00 - - - - comisd %xmm0, %xmm1 +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 comisd (%rax), %xmm1 +# CHECK-NEXT: - - - 1.00 - 1.00 - - cvtdq2pd %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 cvtdq2pd (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - cvtdq2ps %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cvtdq2ps (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 - - cvtpd2dq %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 cvtpd2dq (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 - - cvtpd2pi %xmm0, %mm2 +# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 cvtpd2pi (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - 1.00 - - cvtpd2ps %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 cvtpd2ps (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 - - cvtpi2pd %mm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 cvtpi2pd (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - cvtps2dq %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cvtps2dq (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - 1.00 - - cvtps2pd %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 cvtps2pd (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 1.00 - - - - cvtsd2si %xmm0, %ecx +# CHECK-NEXT: - - 1.00 1.00 - - - - cvtsd2si %xmm0, %rcx +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 cvtsd2si (%rax), %ecx +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 cvtsd2si (%rax), %rcx +# CHECK-NEXT: - - - 1.00 - 1.00 - - cvtsd2ss %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 cvtsd2ss (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 - - cvtsi2sdl %ecx, %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 - - cvtsi2sdq %rcx, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cvtsi2sdl (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cvtsi2sdl (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - cvtss2sd %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 cvtss2sd (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 - - cvttpd2dq %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 cvttpd2dq (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 - - cvttpd2pi %xmm0, %mm2 +# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 cvttpd2pi (%rax), %mm2 +# CHECK-NEXT: - - - 1.00 - - - - cvttps2dq %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cvttps2dq (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 1.00 - - - - cvttsd2si %xmm0, %ecx +# CHECK-NEXT: - - 1.00 1.00 - - - - cvttsd2si %xmm0, %rcx +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 cvttsd2si (%rax), %ecx +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 cvttsd2si (%rax), %rcx +# CHECK-NEXT: - 22.00 1.00 - - - - - divpd %xmm0, %xmm2 +# CHECK-NEXT: - 22.00 1.00 - - - 0.50 0.50 divpd (%rax), %xmm2 +# CHECK-NEXT: - 22.00 1.00 - - - - - divsd %xmm0, %xmm2 +# CHECK-NEXT: - 22.00 1.00 - - - 0.50 0.50 divsd (%rax), %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 lfence +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 maskmovdqu %xmm0, %xmm1 +# CHECK-NEXT: - - - 1.00 - - - - maxpd %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 maxpd (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - maxsd %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 maxsd (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - minpd %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 minpd (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - minsd %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 minsd (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - movapd %xmm0, %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movapd %xmm0, (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 movapd (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - movd %eax, %xmm2 +# CHECK-NEXT: - - - - - - 0.50 0.50 movd (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - movd %xmm0, %ecx +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movd %xmm0, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movdqa %xmm0, %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movdqa %xmm0, (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 movdqa (%rax), %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movdqu %xmm0, %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movdqu %xmm0, (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 movdqu (%rax), %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 1.33 - - movdq2q %xmm0, %mm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movhpd %xmm0, (%rax) +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 movhpd (%rax), %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movlpd %xmm0, (%rax) +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 movlpd (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - movmskpd %xmm0, %ecx +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movntil %eax, (%rax) +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movntiq %rax, (%rax) +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movntdq %xmm0, (%rax) +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movntpd %xmm0, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movq %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - movq %rax, %xmm2 +# CHECK-NEXT: - - - - - - 0.50 0.50 movq (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - movq %xmm0, %rcx +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movq %xmm0, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movq2dq %mm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - movsd %xmm0, %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movsd %xmm0, (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 movsd (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - movupd %xmm0, %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movupd %xmm0, (%rax) +# CHECK-NEXT: - - - - - - 0.50 0.50 movupd (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - mulpd %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 mulpd (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - mulsd %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 mulsd (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - orpd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 orpd (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - packssdw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 packssdw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - packsswb %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 packsswb (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - packuswb %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 packuswb (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - paddb %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 paddb (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - paddd %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 paddd (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - paddq %mm0, %mm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 paddq (%rax), %mm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - paddq %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 paddq (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - paddsb %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 paddsb (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - paddsw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 paddsw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - paddusb %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 paddusb (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - paddusw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 paddusw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - paddw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 paddw (%rax), %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - pand %xmm0, %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 pand (%rax), %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - pandn %xmm0, %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 pandn (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pavgb %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pavgb (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pavgw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pavgw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pcmpeqb %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pcmpeqb (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pcmpeqd %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pcmpeqd (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pcmpeqw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pcmpeqw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pcmpgtb %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pcmpgtb (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pcmpgtd %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pcmpgtd (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pcmpgtw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pcmpgtw (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - pextrw $1, %xmm0, %ecx +# CHECK-NEXT: - - 1.00 - - - - - pmaddwd %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmaddwd (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pmaxsw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmaxsw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pmaxub %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmaxub (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pminsw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pminsw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pminub %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pminub (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - pmovmskb %xmm0, %ecx +# CHECK-NEXT: - - 1.00 - - - - - pmulhuw %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmulhuw (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - pmulhw %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmulhw (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - pmullw %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmullw (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - pmuludq %mm0, %mm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmuludq (%rax), %mm2 +# CHECK-NEXT: - - 1.00 - - - - - pmuludq %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmuludq (%rax), %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - por %xmm0, %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 por (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - psadbw %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 psadbw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pshufd $1, %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pshufd $1, (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pshufhw $1, %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pshufhw $1, (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pshuflw $1, %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pshuflw $1, (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - pslld $1, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - pslld %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 0.50 0.50 pslld (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pslldq $1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - psllq $1, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - psllq %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 0.50 0.50 psllq (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - psllw $1, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - psllw %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 0.50 0.50 psllw (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - psrad $1, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - psrad %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 0.50 0.50 psrad (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - psraw $1, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - psraw %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 0.50 0.50 psraw (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - psrld $1, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - psrld %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 0.50 0.50 psrld (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - psrldq $1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - psrlq $1, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - psrlq %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 0.50 0.50 psrlq (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - psrlw $1, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - psrlw %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 0.50 0.50 psrlw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - psubb %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 psubb (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - psubd %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 psubd (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - psubq %mm0, %mm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 psubq (%rax), %mm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - psubq %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 psubq (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - psubsb %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 psubsb (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - psubsw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 psubsw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - psubusb %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 psubusb (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - psubusw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 psubusw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - psubw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 psubw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - punpckhbw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 punpckhbw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - punpckhdq %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 punpckhdq (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - punpckhqdq %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 punpckhqdq (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - punpckhwd %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 punpckhwd (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - punpcklbw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 punpcklbw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - punpckldq %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 punpckldq (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - punpcklqdq %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 punpcklqdq (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - punpcklwd %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 punpcklwd (%rax), %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - pxor %xmm0, %xmm2 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 pxor (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - shufpd $1, %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 shufpd $1, (%rax), %xmm2 +# CHECK-NEXT: - 21.00 1.00 - - - - - sqrtpd %xmm0, %xmm2 +# CHECK-NEXT: - 21.00 1.00 - - - 0.50 0.50 sqrtpd (%rax), %xmm2 +# CHECK-NEXT: - 21.00 1.00 - - - - - sqrtsd %xmm0, %xmm2 +# CHECK-NEXT: - 21.00 1.00 - - - 0.50 0.50 sqrtsd (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - subpd %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 subpd (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - subsd %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 subsd (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 1.00 - - - - ucomisd %xmm0, %xmm1 +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 ucomisd (%rax), %xmm1 +# CHECK-NEXT: - - - - - 1.00 - - unpckhpd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 unpckhpd (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - unpcklpd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 unpcklpd (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - xorpd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 xorpd (%rax), %xmm2 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/resources-sse3.s b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-sse3.s new file mode 100644 index 00000000000..8438e1a7a84 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-sse3.s @@ -0,0 +1,96 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +addsubpd %xmm0, %xmm2 +addsubpd (%rax), %xmm2 + +addsubps %xmm0, %xmm2 +addsubps (%rax), %xmm2 + +haddpd %xmm0, %xmm2 +haddpd (%rax), %xmm2 + +haddps %xmm0, %xmm2 +haddps (%rax), %xmm2 + +hsubpd %xmm0, %xmm2 +hsubpd (%rax), %xmm2 + +hsubps %xmm0, %xmm2 +hsubps (%rax), %xmm2 + +lddqu (%rax), %xmm2 + +movddup %xmm0, %xmm2 +movddup (%rax), %xmm2 + +movshdup %xmm0, %xmm2 +movshdup (%rax), %xmm2 + +movsldup %xmm0, %xmm2 +movsldup (%rax), %xmm2 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 addsubpd %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * addsubpd (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 addsubps %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * addsubps (%rax), %xmm2 +# CHECK-NEXT: 3 5 2.00 haddpd %xmm0, %xmm2 +# CHECK-NEXT: 4 11 2.00 * haddpd (%rax), %xmm2 +# CHECK-NEXT: 3 5 2.00 haddps %xmm0, %xmm2 +# CHECK-NEXT: 4 11 2.00 * haddps (%rax), %xmm2 +# CHECK-NEXT: 3 5 2.00 hsubpd %xmm0, %xmm2 +# CHECK-NEXT: 4 11 2.00 * hsubpd (%rax), %xmm2 +# CHECK-NEXT: 3 5 2.00 hsubps %xmm0, %xmm2 +# CHECK-NEXT: 4 11 2.00 * hsubps (%rax), %xmm2 +# CHECK-NEXT: 1 6 0.50 * lddqu (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 movddup %xmm0, %xmm2 +# CHECK-NEXT: 1 6 0.50 * movddup (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 movshdup %xmm0, %xmm2 +# CHECK-NEXT: 1 6 0.50 * movshdup (%rax), %xmm2 +# CHECK-NEXT: 1 1 1.00 movsldup %xmm0, %xmm2 +# CHECK-NEXT: 1 6 0.50 * movsldup (%rax), %xmm2 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - - 12.00 - 19.00 5.00 5.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - - - - addsubpd %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 addsubpd (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - addsubps %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 addsubps (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - 2.00 - - haddpd %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - 2.00 0.50 0.50 haddpd (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - 2.00 - - haddps %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - 2.00 0.50 0.50 haddps (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - 2.00 - - hsubpd %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - 2.00 0.50 0.50 hsubpd (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - 2.00 - - hsubps %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - 2.00 0.50 0.50 hsubps (%rax), %xmm2 +# CHECK-NEXT: - - - - - - 0.50 0.50 lddqu (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - movddup %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - 0.50 0.50 movddup (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - movshdup %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - 0.50 0.50 movshdup (%rax), %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - movsldup %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - 0.50 0.50 movsldup (%rax), %xmm2 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/resources-sse41.s b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-sse41.s new file mode 100644 index 00000000000..08c6ccfde8f --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-sse41.s @@ -0,0 +1,366 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +blendpd $11, %xmm0, %xmm2 +blendpd $11, (%rax), %xmm2 + +blendps $11, %xmm0, %xmm2 +blendps $11, (%rax), %xmm2 + +blendvpd %xmm0, %xmm2 +blendvpd (%rax), %xmm2 + +blendvps %xmm0, %xmm2 +blendvps (%rax), %xmm2 + +dppd $22, %xmm0, %xmm2 +dppd $22, (%rax), %xmm2 + +dpps $22, %xmm0, %xmm2 +dpps $22, (%rax), %xmm2 + +extractps $1, %xmm0, %rcx +extractps $1, %xmm0, (%rax) + +insertps $1, %xmm0, %xmm2 +insertps $1, (%rax), %xmm2 + +movntdqa (%rax), %xmm2 + +mpsadbw $1, %xmm0, %xmm2 +mpsadbw $1, (%rax), %xmm2 + +packusdw %xmm0, %xmm2 +packusdw (%rax), %xmm2 + +pblendvb %xmm0, %xmm2 +pblendvb (%rax), %xmm2 + +pblendw $11, %xmm0, %xmm2 +pblendw $11, (%rax), %xmm2 + +pcmpeqq %xmm0, %xmm2 +pcmpeqq (%rax), %xmm2 + +pextrb $1, %xmm0, %ecx +pextrb $1, %xmm0, (%rax) + +pextrd $1, %xmm0, %ecx +pextrd $1, %xmm0, (%rax) + +pextrq $1, %xmm0, %rcx +pextrq $1, %xmm0, (%rax) + +pextrw $1, %xmm0, (%rax) + +phminposuw %xmm0, %xmm2 +phminposuw (%rax), %xmm2 + +pinsrb $1, %eax, %xmm1 +pinsrb $1, (%rax), %xmm1 + +pinsrd $1, %eax, %xmm1 +pinsrd $1, (%rax), %xmm1 + +pinsrq $1, %rax, %xmm1 +pinsrq $1, (%rax), %xmm1 + +pmaxsb %xmm0, %xmm2 +pmaxsb (%rax), %xmm2 + +pmaxsd %xmm0, %xmm2 +pmaxsd (%rax), %xmm2 + +pmaxud %xmm0, %xmm2 +pmaxud (%rax), %xmm2 + +pmaxuw %xmm0, %xmm2 +pmaxuw (%rax), %xmm2 + +pminsb %xmm0, %xmm2 +pminsb (%rax), %xmm2 + +pminsd %xmm0, %xmm2 +pminsd (%rax), %xmm2 + +pminud %xmm0, %xmm2 +pminud (%rax), %xmm2 + +pminuw %xmm0, %xmm2 +pminuw (%rax), %xmm2 + +pmovsxbd %xmm0, %xmm2 +pmovsxbd (%rax), %xmm2 + +pmovsxbq %xmm0, %xmm2 +pmovsxbq (%rax), %xmm2 + +pmovsxbw %xmm0, %xmm2 +pmovsxbw (%rax), %xmm2 + +pmovsxdq %xmm0, %xmm2 +pmovsxdq (%rax), %xmm2 + +pmovsxwd %xmm0, %xmm2 +pmovsxwd (%rax), %xmm2 + +pmovsxwq %xmm0, %xmm2 +pmovsxwq (%rax), %xmm2 + +pmovzxbd %xmm0, %xmm2 +pmovzxbd (%rax), %xmm2 + +pmovzxbq %xmm0, %xmm2 +pmovzxbq (%rax), %xmm2 + +pmovzxbw %xmm0, %xmm2 +pmovzxbw (%rax), %xmm2 + +pmovzxdq %xmm0, %xmm2 +pmovzxdq (%rax), %xmm2 + +pmovzxwd %xmm0, %xmm2 +pmovzxwd (%rax), %xmm2 + +pmovzxwq %xmm0, %xmm2 +pmovzxwq (%rax), %xmm2 + +pmuldq %xmm0, %xmm2 +pmuldq (%rax), %xmm2 + +pmulld %xmm0, %xmm2 +pmulld (%rax), %xmm2 + +ptest %xmm0, %xmm1 +ptest (%rax), %xmm1 + +roundpd $1, %xmm0, %xmm2 +roundpd $1, (%rax), %xmm2 + +roundps $1, %xmm0, %xmm2 +roundps $1, (%rax), %xmm2 + +roundsd $1, %xmm0, %xmm2 +roundsd $1, (%rax), %xmm2 + +roundss $1, %xmm0, %xmm2 +roundss $1, (%rax), %xmm2 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 0.50 blendpd $11, %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * blendpd $11, (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 blendps $11, %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * blendps $11, (%rax), %xmm2 +# CHECK-NEXT: 2 2 1.00 blendvpd %xmm0, %xmm0, %xmm2 +# CHECK-NEXT: 3 8 1.00 * blendvpd %xmm0, (%rax), %xmm2 +# CHECK-NEXT: 2 2 1.00 blendvps %xmm0, %xmm0, %xmm2 +# CHECK-NEXT: 3 8 1.00 * blendvps %xmm0, (%rax), %xmm2 +# CHECK-NEXT: 3 9 1.00 dppd $22, %xmm0, %xmm2 +# CHECK-NEXT: 4 15 1.00 * dppd $22, (%rax), %xmm2 +# CHECK-NEXT: 4 12 2.00 dpps $22, %xmm0, %xmm2 +# CHECK-NEXT: 5 18 2.00 * dpps $22, (%rax), %xmm2 +# CHECK-NEXT: 2 3 1.00 extractps $1, %xmm0, %ecx +# CHECK-NEXT: 3 5 1.00 * extractps $1, %xmm0, (%rax) +# CHECK-NEXT: 1 1 1.00 insertps $1, %xmm0, %xmm2 +# CHECK-NEXT: 2 7 1.00 * insertps $1, (%rax), %xmm2 +# CHECK-NEXT: 1 6 0.50 * movntdqa (%rax), %xmm2 +# CHECK-NEXT: 3 7 1.00 mpsadbw $1, %xmm0, %xmm2 +# CHECK-NEXT: 4 13 1.00 * mpsadbw $1, (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 packusdw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * packusdw (%rax), %xmm2 +# CHECK-NEXT: 2 2 1.00 pblendvb %xmm0, %xmm0, %xmm2 +# CHECK-NEXT: 3 8 1.00 * pblendvb %xmm0, (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pblendw $11, %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pblendw $11, (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pcmpeqq %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pcmpeqq (%rax), %xmm2 +# CHECK-NEXT: 2 3 1.00 pextrb $1, %xmm0, %ecx +# CHECK-NEXT: 3 5 1.00 * pextrb $1, %xmm0, (%rax) +# CHECK-NEXT: 2 3 1.00 pextrd $1, %xmm0, %ecx +# CHECK-NEXT: 4 5 1.00 * pextrd $1, %xmm0, (%rax) +# CHECK-NEXT: 2 3 1.00 pextrq $1, %xmm0, %rcx +# CHECK-NEXT: 4 5 1.00 * pextrq $1, %xmm0, (%rax) +# CHECK-NEXT: 3 5 1.00 * pextrw $1, %xmm0, (%rax) +# CHECK-NEXT: 1 5 1.00 phminposuw %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * phminposuw (%rax), %xmm2 +# CHECK-NEXT: 2 2 1.00 pinsrb $1, %eax, %xmm1 +# CHECK-NEXT: 2 7 0.50 * pinsrb $1, (%rax), %xmm1 +# CHECK-NEXT: 2 2 1.00 pinsrd $1, %eax, %xmm1 +# CHECK-NEXT: 2 7 0.50 * pinsrd $1, (%rax), %xmm1 +# CHECK-NEXT: 2 2 1.00 pinsrq $1, %rax, %xmm1 +# CHECK-NEXT: 2 7 0.50 * pinsrq $1, (%rax), %xmm1 +# CHECK-NEXT: 1 1 0.50 pmaxsb %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pmaxsb (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pmaxsd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pmaxsd (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pmaxud %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pmaxud (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pmaxuw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pmaxuw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pminsb %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pminsb (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pminsd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pminsd (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pminud %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pminud (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pminuw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pminuw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pmovsxbd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pmovsxbd (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pmovsxbq %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pmovsxbq (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pmovsxbw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pmovsxbw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pmovsxdq %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pmovsxdq (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pmovsxwd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pmovsxwd (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pmovsxwq %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pmovsxwq (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pmovzxbd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pmovzxbd (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pmovzxbq %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pmovzxbq (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pmovzxbw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pmovzxbw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pmovzxdq %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pmovzxdq (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pmovzxwd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pmovzxwd (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pmovzxwq %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pmovzxwq (%rax), %xmm2 +# CHECK-NEXT: 1 5 1.00 pmuldq %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * pmuldq (%rax), %xmm2 +# CHECK-NEXT: 1 5 1.00 pmulld %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * pmulld (%rax), %xmm2 +# CHECK-NEXT: 2 2 1.00 ptest %xmm0, %xmm1 +# CHECK-NEXT: 3 8 1.00 * ptest (%rax), %xmm1 +# CHECK-NEXT: 1 3 1.00 roundpd $1, %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * roundpd $1, (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 roundps $1, %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * roundps $1, (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 roundsd $1, %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * roundsd $1, (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.00 roundss $1, %xmm0, %xmm2 +# CHECK-NEXT: 2 9 1.00 * roundss $1, (%rax), %xmm2 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 26.00 47.50 5.00 52.50 24.50 24.50 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 0.50 - - 0.50 - - blendpd $11, %xmm0, %xmm2 +# CHECK-NEXT: - - 0.50 - - 0.50 0.50 0.50 blendpd $11, (%rax), %xmm2 +# CHECK-NEXT: - - 0.50 - - 0.50 - - blendps $11, %xmm0, %xmm2 +# CHECK-NEXT: - - 0.50 - - 0.50 0.50 0.50 blendps $11, (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - 1.00 - - blendvpd %xmm0, %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - 1.00 0.50 0.50 blendvpd %xmm0, (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - 1.00 - - blendvps %xmm0, %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - 1.00 0.50 0.50 blendvps %xmm0, (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - dppd $22, %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 1.00 - 1.00 0.50 0.50 dppd $22, (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 2.00 - 1.00 - - dpps $22, %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 2.00 - 1.00 0.50 0.50 dpps $22, (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - 1.00 - - extractps $1, %xmm0, %ecx +# CHECK-NEXT: - - - - 1.00 1.00 0.50 0.50 extractps $1, %xmm0, (%rax) +# CHECK-NEXT: - - - - - 1.00 - - insertps $1, %xmm0, %xmm2 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 insertps $1, (%rax), %xmm2 +# CHECK-NEXT: - - - - - - 0.50 0.50 movntdqa (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - mpsadbw $1, %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 1.00 - 1.00 0.50 0.50 mpsadbw $1, (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - packusdw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 packusdw (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 - - pblendvb %xmm0, %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 pblendvb %xmm0, (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pblendw $11, %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pblendw $11, (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pcmpeqq %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pcmpeqq (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - pextrb $1, %xmm0, %ecx +# CHECK-NEXT: - - - 0.50 1.00 0.50 0.50 0.50 pextrb $1, %xmm0, (%rax) +# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - pextrd $1, %xmm0, %ecx +# CHECK-NEXT: - - 1.00 0.50 1.00 0.50 0.50 0.50 pextrd $1, %xmm0, (%rax) +# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - pextrq $1, %xmm0, %rcx +# CHECK-NEXT: - - 1.00 0.50 1.00 0.50 0.50 0.50 pextrq $1, %xmm0, (%rax) +# CHECK-NEXT: - - - 0.50 1.00 0.50 0.50 0.50 pextrw $1, %xmm0, (%rax) +# CHECK-NEXT: - - 1.00 - - - - - phminposuw %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 phminposuw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 1.50 - - pinsrb $1, %eax, %xmm1 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pinsrb $1, (%rax), %xmm1 +# CHECK-NEXT: - - - 0.50 - 1.50 - - pinsrd $1, %eax, %xmm1 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pinsrd $1, (%rax), %xmm1 +# CHECK-NEXT: - - - 0.50 - 1.50 - - pinsrq $1, %rax, %xmm1 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pinsrq $1, (%rax), %xmm1 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pmaxsb %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmaxsb (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pmaxsd %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmaxsd (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pmaxud %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmaxud (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pmaxuw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmaxuw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pminsb %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pminsb (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pminsd %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pminsd (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pminud %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pminud (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pminuw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pminuw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pmovsxbd %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovsxbd (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pmovsxbq %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovsxbq (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pmovsxbw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovsxbw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pmovsxdq %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovsxdq (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pmovsxwd %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovsxwd (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pmovsxwq %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovsxwq (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pmovzxbd %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovzxbd (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pmovzxbq %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovzxbq (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pmovzxbw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovzxbw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pmovzxdq %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovzxdq (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pmovzxwd %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovzxwd (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pmovzxwq %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmovzxwq (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - pmuldq %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmuldq (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - pmulld %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmulld (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - 1.00 - - ptest %xmm0, %xmm1 +# CHECK-NEXT: - - 1.00 - - 1.00 0.50 0.50 ptest (%rax), %xmm1 +# CHECK-NEXT: - - - 1.00 - - - - roundpd $1, %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 roundpd $1, (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - roundps $1, %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 roundps $1, (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - roundsd $1, %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 roundsd $1, (%rax), %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - roundss $1, %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 roundss $1, (%rax), %xmm2 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/resources-sse42.s b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-sse42.s new file mode 100644 index 00000000000..935c5e3d7f3 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-sse42.s @@ -0,0 +1,99 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +crc32b %al, %ecx +crc32b (%rax), %ecx + +crc32l %eax, %ecx +crc32l (%rax), %ecx + +crc32w %ax, %ecx +crc32w (%rax), %ecx + +crc32b %al, %rcx +crc32b (%rax), %rcx + +crc32q %rax, %rcx +crc32q (%rax), %rcx + +pcmpestri $1, %xmm0, %xmm2 +pcmpestri $1, (%rax), %xmm2 + +pcmpestrm $1, %xmm0, %xmm2 +pcmpestrm $1, (%rax), %xmm2 + +pcmpistri $1, %xmm0, %xmm2 +pcmpistri $1, (%rax), %xmm2 + +pcmpistrm $1, %xmm0, %xmm2 +pcmpistrm $1, (%rax), %xmm2 + +pcmpgtq %xmm0, %xmm2 +pcmpgtq (%rax), %xmm2 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 crc32b %al, %ecx +# CHECK-NEXT: 2 8 1.00 * crc32b (%rax), %ecx +# CHECK-NEXT: 1 3 1.00 crc32l %eax, %ecx +# CHECK-NEXT: 2 8 1.00 * crc32l (%rax), %ecx +# CHECK-NEXT: 1 3 1.00 crc32w %ax, %ecx +# CHECK-NEXT: 2 8 1.00 * crc32w (%rax), %ecx +# CHECK-NEXT: 1 3 1.00 crc32b %al, %rcx +# CHECK-NEXT: 2 8 1.00 * crc32b (%rax), %rcx +# CHECK-NEXT: 1 3 1.00 crc32q %rax, %rcx +# CHECK-NEXT: 2 8 1.00 * crc32q (%rax), %rcx +# CHECK-NEXT: 1 4 2.67 pcmpestri $1, %xmm0, %xmm2 +# CHECK-NEXT: 1 4 2.33 * pcmpestri $1, (%rax), %xmm2 +# CHECK-NEXT: 1 11 2.67 pcmpestrm $1, %xmm0, %xmm2 +# CHECK-NEXT: 1 11 2.33 * pcmpestrm $1, (%rax), %xmm2 +# CHECK-NEXT: 3 11 3.00 pcmpistri $1, %xmm0, %xmm2 +# CHECK-NEXT: 4 17 3.00 * pcmpistri $1, (%rax), %xmm2 +# CHECK-NEXT: 3 11 3.00 pcmpistrm $1, %xmm0, %xmm2 +# CHECK-NEXT: 4 17 3.00 * pcmpistrm $1, (%rax), %xmm2 +# CHECK-NEXT: 1 5 1.00 pcmpgtq %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * pcmpgtq (%rax), %xmm2 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 24.00 20.00 - 10.00 5.00 5.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - - - - crc32b %al, %ecx +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 crc32b (%rax), %ecx +# CHECK-NEXT: - - - 1.00 - - - - crc32l %eax, %ecx +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 crc32l (%rax), %ecx +# CHECK-NEXT: - - - 1.00 - - - - crc32w %ax, %ecx +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 crc32w (%rax), %ecx +# CHECK-NEXT: - - - 1.00 - - - - crc32b %al, %rcx +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 crc32b (%rax), %rcx +# CHECK-NEXT: - - - 1.00 - - - - crc32q %rax, %rcx +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 crc32q (%rax), %rcx +# CHECK-NEXT: - - 2.67 2.67 - 2.67 - - pcmpestri $1, %xmm0, %xmm2 +# CHECK-NEXT: - - 2.33 2.33 - 2.33 0.50 0.50 pcmpestri $1, (%rax), %xmm2 +# CHECK-NEXT: - - 2.67 2.67 - 2.67 - - pcmpestrm $1, %xmm0, %xmm2 +# CHECK-NEXT: - - 2.33 2.33 - 2.33 0.50 0.50 pcmpestrm $1, (%rax), %xmm2 +# CHECK-NEXT: - - 3.00 - - - - - pcmpistri $1, %xmm0, %xmm2 +# CHECK-NEXT: - - 3.00 - - - 0.50 0.50 pcmpistri $1, (%rax), %xmm2 +# CHECK-NEXT: - - 3.00 - - - - - pcmpistrm $1, %xmm0, %xmm2 +# CHECK-NEXT: - - 3.00 - - - 0.50 0.50 pcmpistrm $1, (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - pcmpgtq %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pcmpgtq (%rax), %xmm2 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/resources-sse4a.s b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-sse4a.s new file mode 100644 index 00000000000..f4b9c94d48a --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-sse4a.s @@ -0,0 +1,50 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +extrq %xmm0, %xmm2 +extrq $22, $2, %xmm2 + +insertq %xmm0, %xmm2 +insertq $22, $22, %xmm0, %xmm2 + +movntsd %xmm0, (%rax) +movntss %xmm0, (%rax) + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 0.50 extrq %xmm0, %xmm2 +# CHECK-NEXT: 1 1 0.50 extrq $22, $2, %xmm2 +# CHECK-NEXT: 1 1 0.50 insertq %xmm0, %xmm2 +# CHECK-NEXT: 1 1 0.50 insertq $22, $22, %xmm0, %xmm2 +# CHECK-NEXT: 1 1 1.00 * movntsd %xmm0, (%rax) +# CHECK-NEXT: 1 1 1.00 * movntss %xmm0, (%rax) + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - - 2.00 2.00 2.00 1.00 1.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 0.50 - 0.50 - - extrq %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - extrq $22, $2, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - insertq %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - insertq $22, $22, %xmm0, %xmm2 +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movntsd %xmm0, (%rax) +# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movntss %xmm0, (%rax) diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/resources-ssse3.s b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-ssse3.s new file mode 100644 index 00000000000..c341022a288 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-ssse3.s @@ -0,0 +1,253 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +pabsb %mm0, %mm2 +pabsb (%rax), %mm2 + +pabsb %xmm0, %xmm2 +pabsb (%rax), %xmm2 + +pabsd %mm0, %mm2 +pabsd (%rax), %mm2 + +pabsd %xmm0, %xmm2 +pabsd (%rax), %xmm2 + +pabsw %mm0, %mm2 +pabsw (%rax), %mm2 + +pabsw %xmm0, %xmm2 +pabsw (%rax), %xmm2 + +palignr $1, %mm0, %mm2 +palignr $1, (%rax), %mm2 + +palignr $1, %xmm0, %xmm2 +palignr $1, (%rax), %xmm2 + +phaddd %mm0, %mm2 +phaddd (%rax), %mm2 + +phaddd %xmm0, %xmm2 +phaddd (%rax), %xmm2 + +phaddsw %mm0, %mm2 +phaddsw (%rax), %mm2 + +phaddsw %xmm0, %xmm2 +phaddsw (%rax), %xmm2 + +phaddw %mm0, %mm2 +phaddw (%rax), %mm2 + +phaddw %xmm0, %xmm2 +phaddw (%rax), %xmm2 + +phsubd %mm0, %mm2 +phsubd (%rax), %mm2 + +phsubd %xmm0, %xmm2 +phsubd (%rax), %xmm2 + +phsubsw %mm0, %mm2 +phsubsw (%rax), %mm2 + +phsubsw %xmm0, %xmm2 +phsubsw (%rax), %xmm2 + +phsubw %mm0, %mm2 +phsubw (%rax), %mm2 + +phsubw %xmm0, %xmm2 +phsubw (%rax), %xmm2 + +pmaddubsw %mm0, %mm2 +pmaddubsw (%rax), %mm2 + +pmaddubsw %xmm0, %xmm2 +pmaddubsw (%rax), %xmm2 + +pmulhrsw %mm0, %mm2 +pmulhrsw (%rax), %mm2 + +pmulhrsw %xmm0, %xmm2 +pmulhrsw (%rax), %xmm2 + +pshufb %mm0, %mm2 +pshufb (%rax), %mm2 + +pshufb %xmm0, %xmm2 +pshufb (%rax), %xmm2 + +psignb %mm0, %mm2 +psignb (%rax), %mm2 + +psignb %xmm0, %xmm2 +psignb (%rax), %xmm2 + +psignd %mm0, %mm2 +psignd (%rax), %mm2 + +psignd %xmm0, %xmm2 +psignd (%rax), %xmm2 + +psignw %mm0, %mm2 +psignw (%rax), %mm2 + +psignw %xmm0, %xmm2 +psignw (%rax), %xmm2 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 0.50 pabsb %mm0, %mm2 +# CHECK-NEXT: 2 6 0.50 * pabsb (%rax), %mm2 +# CHECK-NEXT: 1 1 0.50 pabsb %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pabsb (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pabsd %mm0, %mm2 +# CHECK-NEXT: 2 6 0.50 * pabsd (%rax), %mm2 +# CHECK-NEXT: 1 1 0.50 pabsd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pabsd (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pabsw %mm0, %mm2 +# CHECK-NEXT: 2 6 0.50 * pabsw (%rax), %mm2 +# CHECK-NEXT: 1 1 0.50 pabsw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pabsw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 palignr $1, %mm0, %mm2 +# CHECK-NEXT: 2 6 0.50 * palignr $1, (%rax), %mm2 +# CHECK-NEXT: 1 1 0.50 palignr $1, %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * palignr $1, (%rax), %xmm2 +# CHECK-NEXT: 3 3 1.50 phaddd %mm0, %mm2 +# CHECK-NEXT: 4 8 1.50 * phaddd (%rax), %mm2 +# CHECK-NEXT: 3 3 1.50 phaddd %xmm0, %xmm2 +# CHECK-NEXT: 4 9 1.50 * phaddd (%rax), %xmm2 +# CHECK-NEXT: 3 3 1.50 phaddsw %mm0, %mm2 +# CHECK-NEXT: 4 8 1.50 * phaddsw (%rax), %mm2 +# CHECK-NEXT: 3 3 1.50 phaddsw %xmm0, %xmm2 +# CHECK-NEXT: 4 9 1.50 * phaddsw (%rax), %xmm2 +# CHECK-NEXT: 3 3 1.50 phaddw %mm0, %mm2 +# CHECK-NEXT: 4 8 1.50 * phaddw (%rax), %mm2 +# CHECK-NEXT: 3 3 1.50 phaddw %xmm0, %xmm2 +# CHECK-NEXT: 4 9 1.50 * phaddw (%rax), %xmm2 +# CHECK-NEXT: 3 3 1.50 phsubd %mm0, %mm2 +# CHECK-NEXT: 4 8 1.50 * phsubd (%rax), %mm2 +# CHECK-NEXT: 3 3 1.50 phsubd %xmm0, %xmm2 +# CHECK-NEXT: 4 9 1.50 * phsubd (%rax), %xmm2 +# CHECK-NEXT: 3 3 1.50 phsubsw %mm0, %mm2 +# CHECK-NEXT: 4 8 1.50 * phsubsw (%rax), %mm2 +# CHECK-NEXT: 3 3 1.50 phsubsw %xmm0, %xmm2 +# CHECK-NEXT: 4 9 1.50 * phsubsw (%rax), %xmm2 +# CHECK-NEXT: 3 3 1.50 phsubw %mm0, %mm2 +# CHECK-NEXT: 4 8 1.50 * phsubw (%rax), %mm2 +# CHECK-NEXT: 3 3 1.50 phsubw %xmm0, %xmm2 +# CHECK-NEXT: 4 9 1.50 * phsubw (%rax), %xmm2 +# CHECK-NEXT: 1 5 1.00 pmaddubsw %mm0, %mm2 +# CHECK-NEXT: 2 10 1.00 * pmaddubsw (%rax), %mm2 +# CHECK-NEXT: 1 5 1.00 pmaddubsw %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * pmaddubsw (%rax), %xmm2 +# CHECK-NEXT: 1 5 1.00 pmulhrsw %mm0, %mm2 +# CHECK-NEXT: 2 10 1.00 * pmulhrsw (%rax), %mm2 +# CHECK-NEXT: 1 5 1.00 pmulhrsw %xmm0, %xmm2 +# CHECK-NEXT: 2 11 1.00 * pmulhrsw (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 pshufb %mm0, %mm2 +# CHECK-NEXT: 2 6 0.50 * pshufb (%rax), %mm2 +# CHECK-NEXT: 1 1 0.50 pshufb %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * pshufb (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 psignb %mm0, %mm2 +# CHECK-NEXT: 2 6 0.50 * psignb (%rax), %mm2 +# CHECK-NEXT: 1 1 0.50 psignb %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * psignb (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 psignd %mm0, %mm2 +# CHECK-NEXT: 2 6 0.50 * psignd (%rax), %mm2 +# CHECK-NEXT: 1 1 0.50 psignd %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * psignd (%rax), %xmm2 +# CHECK-NEXT: 1 1 0.50 psignw %mm0, %mm2 +# CHECK-NEXT: 2 6 0.50 * psignw (%rax), %mm2 +# CHECK-NEXT: 1 1 0.50 psignw %xmm0, %xmm2 +# CHECK-NEXT: 2 7 0.50 * psignw (%rax), %xmm2 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 8.00 52.00 - 52.00 16.00 16.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 0.50 - 0.50 - - pabsb %mm0, %mm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pabsb (%rax), %mm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pabsb %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pabsb (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pabsd %mm0, %mm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pabsd (%rax), %mm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pabsd %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pabsd (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pabsw %mm0, %mm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pabsw (%rax), %mm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pabsw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pabsw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - palignr $1, %mm0, %mm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 palignr $1, (%rax), %mm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - palignr $1, %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 palignr $1, (%rax), %xmm2 +# CHECK-NEXT: - - - 1.50 - 1.50 - - phaddd %mm0, %mm2 +# CHECK-NEXT: - - - 1.50 - 1.50 0.50 0.50 phaddd (%rax), %mm2 +# CHECK-NEXT: - - - 1.50 - 1.50 - - phaddd %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.50 - 1.50 0.50 0.50 phaddd (%rax), %xmm2 +# CHECK-NEXT: - - - 1.50 - 1.50 - - phaddsw %mm0, %mm2 +# CHECK-NEXT: - - - 1.50 - 1.50 0.50 0.50 phaddsw (%rax), %mm2 +# CHECK-NEXT: - - - 1.50 - 1.50 - - phaddsw %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.50 - 1.50 0.50 0.50 phaddsw (%rax), %xmm2 +# CHECK-NEXT: - - - 1.50 - 1.50 - - phaddw %mm0, %mm2 +# CHECK-NEXT: - - - 1.50 - 1.50 0.50 0.50 phaddw (%rax), %mm2 +# CHECK-NEXT: - - - 1.50 - 1.50 - - phaddw %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.50 - 1.50 0.50 0.50 phaddw (%rax), %xmm2 +# CHECK-NEXT: - - - 1.50 - 1.50 - - phsubd %mm0, %mm2 +# CHECK-NEXT: - - - 1.50 - 1.50 0.50 0.50 phsubd (%rax), %mm2 +# CHECK-NEXT: - - - 1.50 - 1.50 - - phsubd %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.50 - 1.50 0.50 0.50 phsubd (%rax), %xmm2 +# CHECK-NEXT: - - - 1.50 - 1.50 - - phsubsw %mm0, %mm2 +# CHECK-NEXT: - - - 1.50 - 1.50 0.50 0.50 phsubsw (%rax), %mm2 +# CHECK-NEXT: - - - 1.50 - 1.50 - - phsubsw %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.50 - 1.50 0.50 0.50 phsubsw (%rax), %xmm2 +# CHECK-NEXT: - - - 1.50 - 1.50 - - phsubw %mm0, %mm2 +# CHECK-NEXT: - - - 1.50 - 1.50 0.50 0.50 phsubw (%rax), %mm2 +# CHECK-NEXT: - - - 1.50 - 1.50 - - phsubw %xmm0, %xmm2 +# CHECK-NEXT: - - - 1.50 - 1.50 0.50 0.50 phsubw (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - pmaddubsw %mm0, %mm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmaddubsw (%rax), %mm2 +# CHECK-NEXT: - - 1.00 - - - - - pmaddubsw %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmaddubsw (%rax), %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - pmulhrsw %mm0, %mm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmulhrsw (%rax), %mm2 +# CHECK-NEXT: - - 1.00 - - - - - pmulhrsw %xmm0, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmulhrsw (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pshufb %mm0, %mm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pshufb (%rax), %mm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - pshufb %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pshufb (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - psignb %mm0, %mm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 psignb (%rax), %mm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - psignb %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 psignb (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - psignd %mm0, %mm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 psignd (%rax), %mm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - psignd %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 psignd (%rax), %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - psignw %mm0, %mm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 psignw (%rax), %mm2 +# CHECK-NEXT: - - - 0.50 - 0.50 - - psignw %xmm0, %xmm2 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 psignw (%rax), %xmm2 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/resources-tbm.s b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-tbm.s new file mode 100644 index 00000000000..ebe9975654c --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-tbm.s @@ -0,0 +1,169 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +bextr $8192, %ebx, %ecx +bextr $8192, (%rbx), %ecx + +bextr $16384, %rbx, %rcx +bextr $16384, (%rbx), %rcx + +blcfill %eax, %ecx +blcfill (%rax), %ecx + +blcfill %rax, %rcx +blcfill (%rax), %rcx + +blci %eax, %ecx +blci (%rax), %ecx + +blci %rax, %rcx +blci (%rax), %rcx + +blcic %eax, %ecx +blcic (%rax), %ecx + +blcic %rax, %rcx +blcic (%rax), %rcx + +blcmsk %eax, %ecx +blcmsk (%rax), %ecx + +blcmsk %rax, %rcx +blcmsk (%rax), %rcx + +blcs %eax, %ecx +blcs (%rax), %ecx + +blcs %rax, %rcx +blcs (%rax), %rcx + +blsfill %eax, %ecx +blsfill (%rax), %ecx + +blsfill %rax, %rcx +blsfill (%rax), %rcx + +blsic %eax, %ecx +blsic (%rax), %ecx + +blsic %rax, %rcx +blsic (%rax), %rcx + +t1mskc %eax, %ecx +t1mskc (%rax), %ecx + +t1mskc %rax, %rcx +t1mskc (%rax), %rcx + +tzmsk %eax, %ecx +tzmsk (%rax), %ecx + +tzmsk %rax, %rcx +tzmsk (%rax), %rcx + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 2 2 1.00 bextrl $8192, %ebx, %ecx +# CHECK-NEXT: 3 7 1.00 * bextrl $8192, (%rbx), %ecx +# CHECK-NEXT: 2 2 1.00 bextrq $16384, %rbx, %rcx +# CHECK-NEXT: 3 7 1.00 * bextrq $16384, (%rbx), %rcx +# CHECK-NEXT: 1 1 0.33 blcfilll %eax, %ecx +# CHECK-NEXT: 2 6 0.50 * blcfilll (%rax), %ecx +# CHECK-NEXT: 1 1 0.33 blcfillq %rax, %rcx +# CHECK-NEXT: 2 6 0.50 * blcfillq (%rax), %rcx +# CHECK-NEXT: 1 1 0.33 blcil %eax, %ecx +# CHECK-NEXT: 2 6 0.50 * blcil (%rax), %ecx +# CHECK-NEXT: 1 1 0.33 blciq %rax, %rcx +# CHECK-NEXT: 2 6 0.50 * blciq (%rax), %rcx +# CHECK-NEXT: 1 1 0.33 blcicl %eax, %ecx +# CHECK-NEXT: 2 6 0.50 * blcicl (%rax), %ecx +# CHECK-NEXT: 1 1 0.33 blcicq %rax, %rcx +# CHECK-NEXT: 2 6 0.50 * blcicq (%rax), %rcx +# CHECK-NEXT: 1 1 0.33 blcmskl %eax, %ecx +# CHECK-NEXT: 2 6 0.50 * blcmskl (%rax), %ecx +# CHECK-NEXT: 1 1 0.33 blcmskq %rax, %rcx +# CHECK-NEXT: 2 6 0.50 * blcmskq (%rax), %rcx +# CHECK-NEXT: 1 1 0.33 blcsl %eax, %ecx +# CHECK-NEXT: 2 6 0.50 * blcsl (%rax), %ecx +# CHECK-NEXT: 1 1 0.33 blcsq %rax, %rcx +# CHECK-NEXT: 2 6 0.50 * blcsq (%rax), %rcx +# CHECK-NEXT: 1 1 0.33 blsfilll %eax, %ecx +# CHECK-NEXT: 2 6 0.50 * blsfilll (%rax), %ecx +# CHECK-NEXT: 1 1 0.33 blsfillq %rax, %rcx +# CHECK-NEXT: 2 6 0.50 * blsfillq (%rax), %rcx +# CHECK-NEXT: 1 1 0.33 blsicl %eax, %ecx +# CHECK-NEXT: 2 6 0.50 * blsicl (%rax), %ecx +# CHECK-NEXT: 1 1 0.33 blsicq %rax, %rcx +# CHECK-NEXT: 2 6 0.50 * blsicq (%rax), %rcx +# CHECK-NEXT: 1 1 0.33 t1mskcl %eax, %ecx +# CHECK-NEXT: 2 6 0.50 * t1mskcl (%rax), %ecx +# CHECK-NEXT: 1 1 0.33 t1mskcq %rax, %rcx +# CHECK-NEXT: 2 6 0.50 * t1mskcq (%rax), %rcx +# CHECK-NEXT: 1 1 0.33 tzmskl %eax, %ecx +# CHECK-NEXT: 2 6 0.50 * tzmskl (%rax), %ecx +# CHECK-NEXT: 1 1 0.33 tzmskq %rax, %rcx +# CHECK-NEXT: 2 6 0.50 * tzmskq (%rax), %rcx + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 14.00 16.00 - 14.00 10.00 10.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 0.50 1.00 - 0.50 - - bextrl $8192, %ebx, %ecx +# CHECK-NEXT: - - 0.50 1.00 - 0.50 0.50 0.50 bextrl $8192, (%rbx), %ecx +# CHECK-NEXT: - - 0.50 1.00 - 0.50 - - bextrq $16384, %rbx, %rcx +# CHECK-NEXT: - - 0.50 1.00 - 0.50 0.50 0.50 bextrq $16384, (%rbx), %rcx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - blcfilll %eax, %ecx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 blcfilll (%rax), %ecx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - blcfillq %rax, %rcx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 blcfillq (%rax), %rcx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - blcil %eax, %ecx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 blcil (%rax), %ecx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - blciq %rax, %rcx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 blciq (%rax), %rcx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - blcicl %eax, %ecx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 blcicl (%rax), %ecx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - blcicq %rax, %rcx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 blcicq (%rax), %rcx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - blcmskl %eax, %ecx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 blcmskl (%rax), %ecx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - blcmskq %rax, %rcx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 blcmskq (%rax), %rcx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - blcsl %eax, %ecx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 blcsl (%rax), %ecx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - blcsq %rax, %rcx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 blcsq (%rax), %rcx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - blsfilll %eax, %ecx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 blsfilll (%rax), %ecx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - blsfillq %rax, %rcx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 blsfillq (%rax), %rcx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - blsicl %eax, %ecx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 blsicl (%rax), %ecx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - blsicq %rax, %rcx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 blsicq (%rax), %rcx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - t1mskcl %eax, %ecx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 t1mskcl (%rax), %ecx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - t1mskcq %rax, %rcx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 t1mskcq (%rax), %rcx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - tzmskl %eax, %ecx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 tzmskl (%rax), %ecx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - tzmskq %rax, %rcx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 tzmskq (%rax), %rcx diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/resources-x86_32.s b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-x86_32.s new file mode 100644 index 00000000000..b4672620cf4 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-x86_32.s @@ -0,0 +1,78 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=i686-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +aaa + +aad +aad $7 + +aam +aam $7 + +aas + +bound %bx, (%eax) +bound %ebx, (%eax) + +daa + +das + +into + +leave + +salc + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 100 0.33 aaa +# CHECK-NEXT: 1 100 0.33 aad +# CHECK-NEXT: 1 100 0.33 aad $7 +# CHECK-NEXT: 1 100 0.33 aam +# CHECK-NEXT: 1 100 0.33 aam $7 +# CHECK-NEXT: 1 100 0.33 aas +# CHECK-NEXT: 1 100 0.33 U bound %bx, (%eax) +# CHECK-NEXT: 1 100 0.33 U bound %ebx, (%eax) +# CHECK-NEXT: 1 100 0.33 daa +# CHECK-NEXT: 1 100 0.33 das +# CHECK-NEXT: 1 100 0.33 U into +# CHECK-NEXT: 3 7 0.67 * leave +# CHECK-NEXT: 1 1 0.33 U salc + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 4.67 4.67 - 4.67 0.50 0.50 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - aaa +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - aad +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - aad $7 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - aam +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - aam $7 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - aas +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - bound %bx, (%eax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - bound %ebx, (%eax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - daa +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - das +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - into +# CHECK-NEXT: - - 0.67 0.67 - 0.67 0.50 0.50 leave +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - salc diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/resources-x86_64.s b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-x86_64.s new file mode 100644 index 00000000000..2ab041c3de6 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-x86_64.s @@ -0,0 +1,2372 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +adcb $7, %al +adcb $7, %dil +adcb $7, (%rax) +adcb %sil, %dil +adcb %sil, (%rax) +adcb (%rax), %dil + +adcw $511, %ax +adcw $511, %di +adcw $511, (%rax) +adcw $7, %di +adcw $7, (%rax) +adcw %si, %di +adcw %si, (%rax) +adcw (%rax), %di + +adcl $665536, %eax +adcl $665536, %edi +adcl $665536, (%rax) +adcl $7, %edi +adcl $7, (%rax) +adcl %esi, %edi +adcl %esi, (%rax) +adcl (%rax), %edi + +adcq $665536, %rax +adcq $665536, %rdi +adcq $665536, (%rax) +adcq $7, %rdi +adcq $7, (%rax) +adcq %rsi, %rdi +adcq %rsi, (%rax) +adcq (%rax), %rdi + +addb $7, %al +addb $7, %dil +addb $7, (%rax) +addb %sil, %dil +addb %sil, (%rax) +addb (%rax), %dil + +addw $511, %ax +addw $511, %di +addw $511, (%rax) +addw $7, %di +addw $7, (%rax) +addw %si, %di +addw %si, (%rax) +addw (%rax), %di + +addl $665536, %eax +addl $665536, %edi +addl $665536, (%rax) +addl $7, %edi +addl $7, (%rax) +addl %esi, %edi +addl %esi, (%rax) +addl (%rax), %edi + +addq $665536, %rax +addq $665536, %rdi +addq $665536, (%rax) +addq $7, %rdi +addq $7, (%rax) +addq %rsi, %rdi +addq %rsi, (%rax) +addq (%rax), %rdi + +andb $7, %al +andb $7, %dil +andb $7, (%rax) +andb %sil, %dil +andb %sil, (%rax) +andb (%rax), %dil + +andw $511, %ax +andw $511, %di +andw $511, (%rax) +andw $7, %di +andw $7, (%rax) +andw %si, %di +andw %si, (%rax) +andw (%rax), %di + +andl $665536, %eax +andl $665536, %edi +andl $665536, (%rax) +andl $7, %edi +andl $7, (%rax) +andl %esi, %edi +andl %esi, (%rax) +andl (%rax), %edi + +andq $665536, %rax +andq $665536, %rdi +andq $665536, (%rax) +andq $7, %rdi +andq $7, (%rax) +andq %rsi, %rdi +andq %rsi, (%rax) +andq (%rax), %rdi + +bsfw %si, %di +bsrw %si, %di +bsfw (%rax), %di +bsrw (%rax), %di + +bsfl %esi, %edi +bsrl %esi, %edi +bsfl (%rax), %edi +bsrl (%rax), %edi + +bsfq %rsi, %rdi +bsrq %rsi, %rdi +bsfq (%rax), %rdi +bsrq (%rax), %rdi + +bswap %eax +bswap %rax + +btw %si, %di +btcw %si, %di +btrw %si, %di +btsw %si, %di +btw %si, (%rax) +btcw %si, (%rax) +btrw %si, (%rax) +btsw %si, (%rax) +btw $7, %di +btcw $7, %di +btrw $7, %di +btsw $7, %di +btw $7, (%rax) +btcw $7, (%rax) +btrw $7, (%rax) +btsw $7, (%rax) + +btl %esi, %edi +btcl %esi, %edi +btrl %esi, %edi +btsl %esi, %edi +btl %esi, (%rax) +btcl %esi, (%rax) +btrl %esi, (%rax) +btsl %esi, (%rax) +btl $7, %edi +btcl $7, %edi +btrl $7, %edi +btsl $7, %edi +btl $7, (%rax) +btcl $7, (%rax) +btrl $7, (%rax) +btsl $7, (%rax) + +btq %rsi, %rdi +btcq %rsi, %rdi +btrq %rsi, %rdi +btsq %rsi, %rdi +btq %rsi, (%rax) +btcq %rsi, (%rax) +btrq %rsi, (%rax) +btsq %rsi, (%rax) +btq $7, %rdi +btcq $7, %rdi +btrq $7, %rdi +btsq $7, %rdi +btq $7, (%rax) +btcq $7, (%rax) +btrq $7, (%rax) +btsq $7, (%rax) + +cbw +cwde +cdqe +cwd +cdq +cqo + +clc +cld +cmc + +cmpb $7, %al +cmpb $7, %dil +cmpb $7, (%rax) +cmpb %sil, %dil +cmpb %sil, (%rax) +cmpb (%rax), %dil + +cmpw $511, %ax +cmpw $511, %di +cmpw $511, (%rax) +cmpw $7, %di +cmpw $7, (%rax) +cmpw %si, %di +cmpw %si, (%rax) +cmpw (%rax), %di + +cmpl $665536, %eax +cmpl $665536, %edi +cmpl $665536, (%rax) +cmpl $7, %edi +cmpl $7, (%rax) +cmpl %esi, %edi +cmpl %esi, (%rax) +cmpl (%rax), %edi + +cmpq $665536, %rax +cmpq $665536, %rdi +cmpq $665536, (%rax) +cmpq $7, %rdi +cmpq $7, (%rax) +cmpq %rsi, %rdi +cmpq %rsi, (%rax) +cmpq (%rax), %rdi + +cmpsb +cmpsw +cmpsl +cmpsq + +cmpxchgb %cl, %bl +cmpxchgb %cl, (%rbx) + +cmpxchgw %cx, %bx +cmpxchgw %cx, (%rbx) + +cmpxchgl %ecx, %ebx +cmpxchgl %ecx, (%rbx) + +cmpxchgq %rcx, %rbx +cmpxchgq %rcx, (%rbx) + +cpuid + +decb %dil +decb (%rax) +decw %di +decw (%rax) +decl %edi +decl (%rax) +decq %rdi +decq (%rax) + +divb %dil +divb (%rax) +divw %si +divw (%rax) +divl %edx +divl (%rax) +divq %rcx +divq (%rax) + +idivb %dil +idivb (%rax) +idivw %si +idivw (%rax) +idivl %edx +idivl (%rax) +idivq %rcx +idivq (%rax) + +imulb %dil +imulb (%rax) + +imulw %di +imulw (%rax) +imulw %si, %di +imulw (%rax), %di +imulw $511, %si, %di +imulw $511, (%rax), %di +imulw $7, %si, %di +imulw $7, (%rax), %di + +imull %edi +imull (%rax) +imull %esi, %edi +imull (%rax), %edi +imull $665536, %esi, %edi +imull $665536, (%rax), %edi +imull $7, %esi, %edi +imull $7, (%rax), %edi + +imulq %rdi +imulq (%rax) +imulq %rsi, %rdi +imulq (%rax), %rdi +imulq $665536, %rsi, %rdi +imulq $665536, (%rax), %rdi +imulq $7, %rsi, %rdi +imulq $7, (%rax), %rdi + +inb $7, %al +inb %dx, %al +inw $7, %ax +inw %dx, %ax +inl $7, %eax +inl %dx, %eax + +incb %dil +incb (%rax) +incw %di +incw (%rax) +incl %edi +incl (%rax) +incq %rdi +incq (%rax) + +insb +insw +insl + +int $7 + +lahf + +lodsb +lodsw +lodsl +lodsq + +movsb +movsw +movsl +movsq + +movsbw %al, %di +movzbw %al, %di +movsbw (%rax), %di +movzbw (%rax), %di +movsbl %al, %edi +movzbl %al, %edi +movsbl (%rax), %edi +movzbl (%rax), %edi +movsbq %al, %rdi +movzbq %al, %rdi +movsbq (%rax), %rdi +movzbq (%rax), %rdi + +movswl %ax, %edi +movzwl %ax, %edi +movswl (%rax), %edi +movzwl (%rax), %edi +movswq %ax, %rdi +movzwq %ax, %rdi +movswq (%rax), %rdi +movzwq (%rax), %rdi + +movslq %eax, %rdi +movslq (%rax), %rdi + +mulb %dil +mulb (%rax) +mulw %si +mulw (%rax) +mull %edx +mull (%rax) +mulq %rcx +mulq (%rax) + +negb %dil +negb (%r8) +negw %si +negw (%r9) +negl %edx +negl (%rax) +negq %rcx +negq (%r10) + +nop +nopw %di +nopw (%rcx) +nopl %esi +nopl (%r8) +nopq %rdx +nopq (%r9) + +notb %dil +notb (%r8) +notw %si +notw (%r9) +notl %edx +notl (%rax) +notq %rcx +notq (%r10) + +orb $7, %al +orb $7, %dil +orb $7, (%rax) +orb %sil, %dil +orb %sil, (%rax) +orb (%rax), %dil + +orw $511, %ax +orw $511, %di +orw $511, (%rax) +orw $7, %di +orw $7, (%rax) +orw %si, %di +orw %si, (%rax) +orw (%rax), %di + +orl $665536, %eax +orl $665536, %edi +orl $665536, (%rax) +orl $7, %edi +orl $7, (%rax) +orl %esi, %edi +orl %esi, (%rax) +orl (%rax), %edi + +orq $665536, %rax +orq $665536, %rdi +orq $665536, (%rax) +orq $7, %rdi +orq $7, (%rax) +orq %rsi, %rdi +orq %rsi, (%rax) +orq (%rax), %rdi + +outb %al, $7 +outb %al, %dx +outw %ax, $7 +outw %ax, %dx +outl %eax, $7 +outl %eax, %dx + +outsb +outsw +outsl + +pause + +rclb %dil +rcrb %dil +rclb (%rax) +rcrb (%rax) +rclb $7, %dil +rcrb $7, %dil +rclb $7, (%rax) +rcrb $7, (%rax) +rclb %cl, %dil +rcrb %cl, %dil +rclb %cl, (%rax) +rcrb %cl, (%rax) + +rclw %di +rcrw %di +rclw (%rax) +rcrw (%rax) +rclw $7, %di +rcrw $7, %di +rclw $7, (%rax) +rcrw $7, (%rax) +rclw %cl, %di +rcrw %cl, %di +rclw %cl, (%rax) +rcrw %cl, (%rax) + +rcll %edi +rcrl %edi +rcll (%rax) +rcrl (%rax) +rcll $7, %edi +rcrl $7, %edi +rcll $7, (%rax) +rcrl $7, (%rax) +rcll %cl, %edi +rcrl %cl, %edi +rcll %cl, (%rax) +rcrl %cl, (%rax) + +rclq %rdi +rcrq %rdi +rclq (%rax) +rcrq (%rax) +rclq $7, %rdi +rcrq $7, %rdi +rclq $7, (%rax) +rcrq $7, (%rax) +rclq %cl, %rdi +rcrq %cl, %rdi +rclq %cl, (%rax) +rcrq %cl, (%rax) + +rolb %dil +rorb %dil +rolb (%rax) +rorb (%rax) +rolb $7, %dil +rorb $7, %dil +rolb $7, (%rax) +rorb $7, (%rax) +rolb %cl, %dil +rorb %cl, %dil +rolb %cl, (%rax) +rorb %cl, (%rax) + +rolw %di +rorw %di +rolw (%rax) +rorw (%rax) +rolw $7, %di +rorw $7, %di +rolw $7, (%rax) +rorw $7, (%rax) +rolw %cl, %di +rorw %cl, %di +rolw %cl, (%rax) +rorw %cl, (%rax) + +roll %edi +rorl %edi +roll (%rax) +rorl (%rax) +roll $7, %edi +rorl $7, %edi +roll $7, (%rax) +rorl $7, (%rax) +roll %cl, %edi +rorl %cl, %edi +roll %cl, (%rax) +rorl %cl, (%rax) + +rolq %rdi +rorq %rdi +rolq (%rax) +rorq (%rax) +rolq $7, %rdi +rorq $7, %rdi +rolq $7, (%rax) +rorq $7, (%rax) +rolq %cl, %rdi +rorq %cl, %rdi +rolq %cl, (%rax) +rorq %cl, (%rax) + +sahf + +sarb %dil +shlb %dil +shrb %dil +sarb (%rax) +shlb (%rax) +shrb (%rax) +sarb $7, %dil +shlb $7, %dil +shrb $7, %dil +sarb $7, (%rax) +shlb $7, (%rax) +shrb $7, (%rax) +sarb %cl, %dil +shlb %cl, %dil +shrb %cl, %dil +sarb %cl, (%rax) +shlb %cl, (%rax) +shrb %cl, (%rax) + +sarw %di +shlw %di +shrw %di +sarw (%rax) +shlw (%rax) +shrw (%rax) +sarw $7, %di +shlw $7, %di +shrw $7, %di +sarw $7, (%rax) +shlw $7, (%rax) +shrw $7, (%rax) +sarw %cl, %di +shlw %cl, %di +shrw %cl, %di +sarw %cl, (%rax) +shlw %cl, (%rax) +shrw %cl, (%rax) + +sarl %edi +shll %edi +shrl %edi +sarl (%rax) +shll (%rax) +shrl (%rax) +sarl $7, %edi +shll $7, %edi +shrl $7, %edi +sarl $7, (%rax) +shll $7, (%rax) +shrl $7, (%rax) +sarl %cl, %edi +shll %cl, %edi +shrl %cl, %edi +sarl %cl, (%rax) +shll %cl, (%rax) +shrl %cl, (%rax) + +sarq %rdi +shlq %rdi +shrq %rdi +sarq (%rax) +shlq (%rax) +shrq (%rax) +sarq $7, %rdi +shlq $7, %rdi +shrq $7, %rdi +sarq $7, (%rax) +shlq $7, (%rax) +shrq $7, (%rax) +sarq %cl, %rdi +shlq %cl, %rdi +shrq %cl, %rdi +sarq %cl, (%rax) +shlq %cl, (%rax) +shrq %cl, (%rax) + +sbbb $7, %al +sbbb $7, %dil +sbbb $7, (%rax) +sbbb %sil, %dil +sbbb %sil, (%rax) +sbbb (%rax), %dil + +sbbw $511, %ax +sbbw $511, %di +sbbw $511, (%rax) +sbbw $7, %di +sbbw $7, (%rax) +sbbw %si, %di +sbbw %si, (%rax) +sbbw (%rax), %di + +sbbl $665536, %eax +sbbl $665536, %edi +sbbl $665536, (%rax) +sbbl $7, %edi +sbbl $7, (%rax) +sbbl %esi, %edi +sbbl %esi, (%rax) +sbbl (%rax), %edi + +sbbq $665536, %rax +sbbq $665536, %rdi +sbbq $665536, (%rax) +sbbq $7, %rdi +sbbq $7, (%rax) +sbbq %rsi, %rdi +sbbq %rsi, (%rax) +sbbq (%rax), %rdi + +scasb +scasw +scasl +scasq + +seto %al +seto (%rax) +setno %al +setno (%rax) +setb %al +setb (%rax) +setnb %al +setnb (%rax) +setz %al +setz (%rax) +setnz %al +setnz (%rax) +seta %al +seta (%rax) +setna %al +setna (%rax) +sets %al +sets (%rax) +setns %al +setns (%rax) +setp %al +setp (%rax) +setnp %al +setnp (%rax) +setl %al +setl (%rax) +setnl %al +setnl (%rax) +setg %al +setg (%rax) +setng %al +setng (%rax) + +shldw %cl, %si, %di +shrdw %cl, %si, %di +shldw %cl, %si, (%rax) +shrdw %cl, %si, (%rax) +shldw $7, %si, %di +shrdw $7, %si, %di +shldw $7, %si, (%rax) +shrdw $7, %si, (%rax) + +shldl %cl, %esi, %edi +shrdl %cl, %esi, %edi +shldl %cl, %esi, (%rax) +shrdl %cl, %esi, (%rax) +shldl $7, %esi, %edi +shrdl $7, %esi, %edi +shldl $7, %esi, (%rax) +shrdl $7, %esi, (%rax) + +shldq %cl, %rsi, %rdi +shrdq %cl, %rsi, %rdi +shldq %cl, %rsi, (%rax) +shrdq %cl, %rsi, (%rax) +shldq $7, %rsi, %rdi +shrdq $7, %rsi, %rdi +shldq $7, %rsi, (%rax) +shrdq $7, %rsi, (%rax) + +stc +std + +stosb +stosw +stosl +stosq + +subb $7, %al +subb $7, %dil +subb $7, (%rax) +subb %sil, %dil +subb %sil, (%rax) +subb (%rax), %dil + +subw $511, %ax +subw $511, %di +subw $511, (%rax) +subw $7, %di +subw $7, (%rax) +subw %si, %di +subw %si, (%rax) +subw (%rax), %di + +subl $665536, %eax +subl $665536, %edi +subl $665536, (%rax) +subl $7, %edi +subl $7, (%rax) +subl %esi, %edi +subl %esi, (%rax) +subl (%rax), %edi + +subq $665536, %rax +subq $665536, %rdi +subq $665536, (%rax) +subq $7, %rdi +subq $7, (%rax) +subq %rsi, %rdi +subq %rsi, (%rax) +subq (%rax), %rdi + +testb $7, %al +testb $7, %dil +testb $7, (%rax) +testb %sil, %dil +testb %sil, (%rax) + +testw $511, %ax +testw $511, %di +testw $511, (%rax) +testw $7, %di +testw $7, (%rax) +testw %si, %di +testw %si, (%rax) + +testl $665536, %eax +testl $665536, %edi +testl $665536, (%rax) +testl $7, %edi +testl $7, (%rax) +testl %esi, %edi +testl %esi, (%rax) + +testq $665536, %rax +testq $665536, %rdi +testq $665536, (%rax) +testq $7, %rdi +testq $7, (%rax) +testq %rsi, %rdi +testq %rsi, (%rax) + +ud2 + +xaddb %bl, %cl +xaddb %bl, (%rcx) + +xaddw %bx, %cx +xaddw %ax, (%rbx) + +xaddl %ebx, %ecx +xaddl %eax, (%rbx) + +xaddq %rbx, %rcx +xaddq %rax, (%rbx) + +xchgb %bl, %cl +xchgb %bl, (%rbx) + +xchgw %ax, %bx +xchgw %bx, %cx +xchgw %ax, (%rbx) + +xchgl %eax, %ebx +xchgl %ebx, %ecx +xchgl %eax, (%rbx) + +xchgq %rax, %rbx +xchgq %rbx, %rcx +xchgq %rax, (%rbx) + +xlatb + +xorb $7, %al +xorb $7, %dil +xorb $7, (%rax) +xorb %sil, %dil +xorb %sil, (%rax) +xorb (%rax), %dil + +xorw $511, %ax +xorw $511, %di +xorw $511, (%rax) +xorw $7, %di +xorw $7, (%rax) +xorw %si, %di +xorw %si, (%rax) +xorw (%rax), %di + +xorl $665536, %eax +xorl $665536, %edi +xorl $665536, (%rax) +xorl $7, %edi +xorl $7, (%rax) +xorl %esi, %edi +xorl %esi, (%rax) +xorl (%rax), %edi + +xorq $665536, %rax +xorq $665536, %rdi +xorq $665536, (%rax) +xorq $7, %rdi +xorq $7, (%rax) +xorq %rsi, %rdi +xorq %rsi, (%rax) +xorq (%rax), %rdi + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 2 2 0.67 adcb $7, %al +# CHECK-NEXT: 2 2 0.67 adcb $7, %dil +# CHECK-NEXT: 6 9 1.00 * * adcb $7, (%rax) +# CHECK-NEXT: 2 2 0.67 adcb %sil, %dil +# CHECK-NEXT: 6 9 1.00 * * adcb %sil, (%rax) +# CHECK-NEXT: 3 7 0.67 * adcb (%rax), %dil +# CHECK-NEXT: 2 2 0.67 adcw $511, %ax +# CHECK-NEXT: 2 2 0.67 adcw $511, %di +# CHECK-NEXT: 6 9 1.00 * * adcw $511, (%rax) +# CHECK-NEXT: 2 2 0.67 adcw $7, %di +# CHECK-NEXT: 6 9 1.00 * * adcw $7, (%rax) +# CHECK-NEXT: 2 2 0.67 adcw %si, %di +# CHECK-NEXT: 6 9 1.00 * * adcw %si, (%rax) +# CHECK-NEXT: 3 7 0.67 * adcw (%rax), %di +# CHECK-NEXT: 2 2 0.67 adcl $665536, %eax +# CHECK-NEXT: 2 2 0.67 adcl $665536, %edi +# CHECK-NEXT: 6 9 1.00 * * adcl $665536, (%rax) +# CHECK-NEXT: 2 2 0.67 adcl $7, %edi +# CHECK-NEXT: 6 9 1.00 * * adcl $7, (%rax) +# CHECK-NEXT: 2 2 0.67 adcl %esi, %edi +# CHECK-NEXT: 6 9 1.00 * * adcl %esi, (%rax) +# CHECK-NEXT: 3 7 0.67 * adcl (%rax), %edi +# CHECK-NEXT: 2 2 0.67 adcq $665536, %rax +# CHECK-NEXT: 2 2 0.67 adcq $665536, %rdi +# CHECK-NEXT: 6 9 1.00 * * adcq $665536, (%rax) +# CHECK-NEXT: 2 2 0.67 adcq $7, %rdi +# CHECK-NEXT: 6 9 1.00 * * adcq $7, (%rax) +# CHECK-NEXT: 2 2 0.67 adcq %rsi, %rdi +# CHECK-NEXT: 6 9 1.00 * * adcq %rsi, (%rax) +# CHECK-NEXT: 3 7 0.67 * adcq (%rax), %rdi +# CHECK-NEXT: 1 1 0.33 addb $7, %al +# CHECK-NEXT: 1 1 0.33 addb $7, %dil +# CHECK-NEXT: 3 7 1.00 * * addb $7, (%rax) +# CHECK-NEXT: 1 1 0.33 addb %sil, %dil +# CHECK-NEXT: 3 7 1.00 * * addb %sil, (%rax) +# CHECK-NEXT: 2 6 0.50 * addb (%rax), %dil +# CHECK-NEXT: 1 1 0.33 addw $511, %ax +# CHECK-NEXT: 1 1 0.33 addw $511, %di +# CHECK-NEXT: 3 7 1.00 * * addw $511, (%rax) +# CHECK-NEXT: 1 1 0.33 addw $7, %di +# CHECK-NEXT: 3 7 1.00 * * addw $7, (%rax) +# CHECK-NEXT: 1 1 0.33 addw %si, %di +# CHECK-NEXT: 3 7 1.00 * * addw %si, (%rax) +# CHECK-NEXT: 2 6 0.50 * addw (%rax), %di +# CHECK-NEXT: 1 1 0.33 addl $665536, %eax +# CHECK-NEXT: 1 1 0.33 addl $665536, %edi +# CHECK-NEXT: 3 7 1.00 * * addl $665536, (%rax) +# CHECK-NEXT: 1 1 0.33 addl $7, %edi +# CHECK-NEXT: 3 7 1.00 * * addl $7, (%rax) +# CHECK-NEXT: 1 1 0.33 addl %esi, %edi +# CHECK-NEXT: 3 7 1.00 * * addl %esi, (%rax) +# CHECK-NEXT: 2 6 0.50 * addl (%rax), %edi +# CHECK-NEXT: 1 1 0.33 addq $665536, %rax +# CHECK-NEXT: 1 1 0.33 addq $665536, %rdi +# CHECK-NEXT: 3 7 1.00 * * addq $665536, (%rax) +# CHECK-NEXT: 1 1 0.33 addq $7, %rdi +# CHECK-NEXT: 3 7 1.00 * * addq $7, (%rax) +# CHECK-NEXT: 1 1 0.33 addq %rsi, %rdi +# CHECK-NEXT: 3 7 1.00 * * addq %rsi, (%rax) +# CHECK-NEXT: 2 6 0.50 * addq (%rax), %rdi +# CHECK-NEXT: 1 1 0.33 andb $7, %al +# CHECK-NEXT: 1 1 0.33 andb $7, %dil +# CHECK-NEXT: 3 7 1.00 * * andb $7, (%rax) +# CHECK-NEXT: 1 1 0.33 andb %sil, %dil +# CHECK-NEXT: 3 7 1.00 * * andb %sil, (%rax) +# CHECK-NEXT: 2 6 0.50 * andb (%rax), %dil +# CHECK-NEXT: 1 1 0.33 andw $511, %ax +# CHECK-NEXT: 1 1 0.33 andw $511, %di +# CHECK-NEXT: 3 7 1.00 * * andw $511, (%rax) +# CHECK-NEXT: 1 1 0.33 andw $7, %di +# CHECK-NEXT: 3 7 1.00 * * andw $7, (%rax) +# CHECK-NEXT: 1 1 0.33 andw %si, %di +# CHECK-NEXT: 3 7 1.00 * * andw %si, (%rax) +# CHECK-NEXT: 2 6 0.50 * andw (%rax), %di +# CHECK-NEXT: 1 1 0.33 andl $665536, %eax +# CHECK-NEXT: 1 1 0.33 andl $665536, %edi +# CHECK-NEXT: 3 7 1.00 * * andl $665536, (%rax) +# CHECK-NEXT: 1 1 0.33 andl $7, %edi +# CHECK-NEXT: 3 7 1.00 * * andl $7, (%rax) +# CHECK-NEXT: 1 1 0.33 andl %esi, %edi +# CHECK-NEXT: 3 7 1.00 * * andl %esi, (%rax) +# CHECK-NEXT: 2 6 0.50 * andl (%rax), %edi +# CHECK-NEXT: 1 1 0.33 andq $665536, %rax +# CHECK-NEXT: 1 1 0.33 andq $665536, %rdi +# CHECK-NEXT: 3 7 1.00 * * andq $665536, (%rax) +# CHECK-NEXT: 1 1 0.33 andq $7, %rdi +# CHECK-NEXT: 3 7 1.00 * * andq $7, (%rax) +# CHECK-NEXT: 1 1 0.33 andq %rsi, %rdi +# CHECK-NEXT: 3 7 1.00 * * andq %rsi, (%rax) +# CHECK-NEXT: 2 6 0.50 * andq (%rax), %rdi +# CHECK-NEXT: 1 3 1.00 bsfw %si, %di +# CHECK-NEXT: 1 3 1.00 bsrw %si, %di +# CHECK-NEXT: 2 8 1.00 * bsfw (%rax), %di +# CHECK-NEXT: 2 8 1.00 * bsrw (%rax), %di +# CHECK-NEXT: 1 3 1.00 bsfl %esi, %edi +# CHECK-NEXT: 1 3 1.00 bsrl %esi, %edi +# CHECK-NEXT: 2 8 1.00 * bsfl (%rax), %edi +# CHECK-NEXT: 2 8 1.00 * bsrl (%rax), %edi +# CHECK-NEXT: 1 3 1.00 bsfq %rsi, %rdi +# CHECK-NEXT: 1 3 1.00 bsrq %rsi, %rdi +# CHECK-NEXT: 2 8 1.00 * bsfq (%rax), %rdi +# CHECK-NEXT: 2 8 1.00 * bsrq (%rax), %rdi +# CHECK-NEXT: 1 1 1.00 bswapl %eax +# CHECK-NEXT: 2 2 1.00 bswapq %rax +# CHECK-NEXT: 1 1 0.50 btw %si, %di +# CHECK-NEXT: 1 1 0.50 btcw %si, %di +# CHECK-NEXT: 1 1 0.50 btrw %si, %di +# CHECK-NEXT: 1 1 0.50 btsw %si, %di +# CHECK-NEXT: 6 9 1.00 * btw %si, (%rax) +# CHECK-NEXT: 6 9 1.00 * * btcw %si, (%rax) +# CHECK-NEXT: 6 9 1.00 * * btrw %si, (%rax) +# CHECK-NEXT: 6 9 1.00 * * btsw %si, (%rax) +# CHECK-NEXT: 1 1 0.50 btw $7, %di +# CHECK-NEXT: 1 1 0.50 btcw $7, %di +# CHECK-NEXT: 1 1 0.50 btrw $7, %di +# CHECK-NEXT: 1 1 0.50 btsw $7, %di +# CHECK-NEXT: 2 6 0.50 * btw $7, (%rax) +# CHECK-NEXT: 4 7 1.00 * * btcw $7, (%rax) +# CHECK-NEXT: 4 7 1.00 * * btrw $7, (%rax) +# CHECK-NEXT: 4 7 1.00 * * btsw $7, (%rax) +# CHECK-NEXT: 1 1 0.50 btl %esi, %edi +# CHECK-NEXT: 1 1 0.50 btcl %esi, %edi +# CHECK-NEXT: 1 1 0.50 btrl %esi, %edi +# CHECK-NEXT: 1 1 0.50 btsl %esi, %edi +# CHECK-NEXT: 6 9 1.00 * btl %esi, (%rax) +# CHECK-NEXT: 6 9 1.00 * * btcl %esi, (%rax) +# CHECK-NEXT: 6 9 1.00 * * btrl %esi, (%rax) +# CHECK-NEXT: 6 9 1.00 * * btsl %esi, (%rax) +# CHECK-NEXT: 1 1 0.50 btl $7, %edi +# CHECK-NEXT: 1 1 0.50 btcl $7, %edi +# CHECK-NEXT: 1 1 0.50 btrl $7, %edi +# CHECK-NEXT: 1 1 0.50 btsl $7, %edi +# CHECK-NEXT: 2 6 0.50 * btl $7, (%rax) +# CHECK-NEXT: 4 7 1.00 * * btcl $7, (%rax) +# CHECK-NEXT: 4 7 1.00 * * btrl $7, (%rax) +# CHECK-NEXT: 4 7 1.00 * * btsl $7, (%rax) +# CHECK-NEXT: 1 1 0.50 btq %rsi, %rdi +# CHECK-NEXT: 1 1 0.50 btcq %rsi, %rdi +# CHECK-NEXT: 1 1 0.50 btrq %rsi, %rdi +# CHECK-NEXT: 1 1 0.50 btsq %rsi, %rdi +# CHECK-NEXT: 6 9 1.00 * btq %rsi, (%rax) +# CHECK-NEXT: 6 9 1.00 * * btcq %rsi, (%rax) +# CHECK-NEXT: 6 9 1.00 * * btrq %rsi, (%rax) +# CHECK-NEXT: 6 9 1.00 * * btsq %rsi, (%rax) +# CHECK-NEXT: 1 1 0.50 btq $7, %rdi +# CHECK-NEXT: 1 1 0.50 btcq $7, %rdi +# CHECK-NEXT: 1 1 0.50 btrq $7, %rdi +# CHECK-NEXT: 1 1 0.50 btsq $7, %rdi +# CHECK-NEXT: 2 6 0.50 * btq $7, (%rax) +# CHECK-NEXT: 4 7 1.00 * * btcq $7, (%rax) +# CHECK-NEXT: 4 7 1.00 * * btrq $7, (%rax) +# CHECK-NEXT: 4 7 1.00 * * btsq $7, (%rax) +# CHECK-NEXT: 1 1 0.33 cbtw +# CHECK-NEXT: 1 1 0.33 cwtl +# CHECK-NEXT: 1 1 0.33 cltq +# CHECK-NEXT: 2 2 1.00 cwtd +# CHECK-NEXT: 1 1 0.50 cltd +# CHECK-NEXT: 1 1 0.50 cqto +# CHECK-NEXT: 1 1 0.25 U clc +# CHECK-NEXT: 1 1 0.33 U cld +# CHECK-NEXT: 1 1 0.33 U cmc +# CHECK-NEXT: 1 1 0.33 cmpb $7, %al +# CHECK-NEXT: 1 1 0.33 cmpb $7, %dil +# CHECK-NEXT: 2 6 0.50 * cmpb $7, (%rax) +# CHECK-NEXT: 1 1 0.33 cmpb %sil, %dil +# CHECK-NEXT: 2 6 0.50 * cmpb %sil, (%rax) +# CHECK-NEXT: 2 6 0.50 * cmpb (%rax), %dil +# CHECK-NEXT: 1 1 0.33 cmpw $511, %ax +# CHECK-NEXT: 1 1 0.33 cmpw $511, %di +# CHECK-NEXT: 2 6 0.50 * cmpw $511, (%rax) +# CHECK-NEXT: 1 1 0.33 cmpw $7, %di +# CHECK-NEXT: 2 6 0.50 * cmpw $7, (%rax) +# CHECK-NEXT: 1 1 0.33 cmpw %si, %di +# CHECK-NEXT: 2 6 0.50 * cmpw %si, (%rax) +# CHECK-NEXT: 2 6 0.50 * cmpw (%rax), %di +# CHECK-NEXT: 1 1 0.33 cmpl $665536, %eax +# CHECK-NEXT: 1 1 0.33 cmpl $665536, %edi +# CHECK-NEXT: 2 6 0.50 * cmpl $665536, (%rax) +# CHECK-NEXT: 1 1 0.33 cmpl $7, %edi +# CHECK-NEXT: 2 6 0.50 * cmpl $7, (%rax) +# CHECK-NEXT: 1 1 0.33 cmpl %esi, %edi +# CHECK-NEXT: 2 6 0.50 * cmpl %esi, (%rax) +# CHECK-NEXT: 2 6 0.50 * cmpl (%rax), %edi +# CHECK-NEXT: 1 1 0.33 cmpq $665536, %rax +# CHECK-NEXT: 1 1 0.33 cmpq $665536, %rdi +# CHECK-NEXT: 2 6 0.50 * cmpq $665536, (%rax) +# CHECK-NEXT: 1 1 0.33 cmpq $7, %rdi +# CHECK-NEXT: 2 6 0.50 * cmpq $7, (%rax) +# CHECK-NEXT: 1 1 0.33 cmpq %rsi, %rdi +# CHECK-NEXT: 2 6 0.50 * cmpq %rsi, (%rax) +# CHECK-NEXT: 2 6 0.50 * cmpq (%rax), %rdi +# CHECK-NEXT: 5 8 1.00 U cmpsb %es:(%rdi), (%rsi) +# CHECK-NEXT: 5 8 1.00 U cmpsw %es:(%rdi), (%rsi) +# CHECK-NEXT: 5 8 1.00 U cmpsl %es:(%rdi), (%rsi) +# CHECK-NEXT: 5 8 1.00 U cmpsq %es:(%rdi), (%rsi) +# CHECK-NEXT: 4 5 1.33 cmpxchgb %cl, %bl +# CHECK-NEXT: 6 8 2.00 * * cmpxchgb %cl, (%rbx) +# CHECK-NEXT: 4 5 1.33 cmpxchgw %cx, %bx +# CHECK-NEXT: 6 8 2.00 * * cmpxchgw %cx, (%rbx) +# CHECK-NEXT: 4 5 1.33 cmpxchgl %ecx, %ebx +# CHECK-NEXT: 6 8 2.00 * * cmpxchgl %ecx, (%rbx) +# CHECK-NEXT: 4 5 1.33 cmpxchgq %rcx, %rbx +# CHECK-NEXT: 6 8 2.00 * * cmpxchgq %rcx, (%rbx) +# CHECK-NEXT: 1 100 0.33 U cpuid +# CHECK-NEXT: 1 1 0.33 decb %dil +# CHECK-NEXT: 3 7 1.00 * * decb (%rax) +# CHECK-NEXT: 1 1 0.33 decw %di +# CHECK-NEXT: 3 7 1.00 * * decw (%rax) +# CHECK-NEXT: 1 1 0.33 decl %edi +# CHECK-NEXT: 3 7 1.00 * * decl (%rax) +# CHECK-NEXT: 1 1 0.33 decq %rdi +# CHECK-NEXT: 3 7 1.00 * * decq (%rax) +# CHECK-NEXT: 1 25 10.00 U divb %dil +# CHECK-NEXT: 2 30 10.00 * U divb (%rax) +# CHECK-NEXT: 1 25 10.00 U divw %si +# CHECK-NEXT: 2 30 10.00 * U divw (%rax) +# CHECK-NEXT: 1 25 10.00 U divl %edx +# CHECK-NEXT: 2 30 10.00 * U divl (%rax) +# CHECK-NEXT: 1 25 10.00 U divq %rcx +# CHECK-NEXT: 2 30 10.00 * U divq (%rax) +# CHECK-NEXT: 1 25 10.00 U idivb %dil +# CHECK-NEXT: 2 30 10.00 * U idivb (%rax) +# CHECK-NEXT: 1 25 10.00 U idivw %si +# CHECK-NEXT: 2 30 10.00 * U idivw (%rax) +# CHECK-NEXT: 1 25 10.00 U idivl %edx +# CHECK-NEXT: 2 30 10.00 * U idivl (%rax) +# CHECK-NEXT: 1 25 10.00 U idivq %rcx +# CHECK-NEXT: 2 30 10.00 * U idivq (%rax) +# CHECK-NEXT: 1 3 1.00 imulb %dil +# CHECK-NEXT: 2 8 1.00 * imulb (%rax) +# CHECK-NEXT: 4 4 1.33 imulw %di +# CHECK-NEXT: 5 9 1.33 * imulw (%rax) +# CHECK-NEXT: 1 3 1.00 imulw %si, %di +# CHECK-NEXT: 2 8 1.00 * imulw (%rax), %di +# CHECK-NEXT: 2 4 1.00 imulw $511, %si, %di +# CHECK-NEXT: 3 8 1.00 * imulw $511, (%rax), %di +# CHECK-NEXT: 2 4 1.00 imulw $7, %si, %di +# CHECK-NEXT: 3 8 1.00 * imulw $7, (%rax), %di +# CHECK-NEXT: 3 4 1.00 imull %edi +# CHECK-NEXT: 4 9 1.00 * imull (%rax) +# CHECK-NEXT: 1 3 1.00 imull %esi, %edi +# CHECK-NEXT: 2 8 1.00 * imull (%rax), %edi +# CHECK-NEXT: 1 3 1.00 imull $665536, %esi, %edi +# CHECK-NEXT: 2 8 1.00 * imull $665536, (%rax), %edi +# CHECK-NEXT: 1 3 1.00 imull $7, %esi, %edi +# CHECK-NEXT: 2 8 1.00 * imull $7, (%rax), %edi +# CHECK-NEXT: 2 4 1.00 imulq %rdi +# CHECK-NEXT: 3 9 1.00 * imulq (%rax) +# CHECK-NEXT: 1 3 1.00 imulq %rsi, %rdi +# CHECK-NEXT: 2 8 1.00 * imulq (%rax), %rdi +# CHECK-NEXT: 1 3 1.00 imulq $665536, %rsi, %rdi +# CHECK-NEXT: 2 8 1.00 * imulq $665536, (%rax), %rdi +# CHECK-NEXT: 1 3 1.00 imulq $7, %rsi, %rdi +# CHECK-NEXT: 2 8 1.00 * imulq $7, (%rax), %rdi +# CHECK-NEXT: 1 100 0.33 U inb $7, %al +# CHECK-NEXT: 1 100 0.33 U inb %dx, %al +# CHECK-NEXT: 1 100 0.33 U inw $7, %ax +# CHECK-NEXT: 1 100 0.33 U inw %dx, %ax +# CHECK-NEXT: 1 100 0.33 U inl $7, %eax +# CHECK-NEXT: 1 100 0.33 U inl %dx, %eax +# CHECK-NEXT: 1 1 0.33 incb %dil +# CHECK-NEXT: 3 7 1.00 * * incb (%rax) +# CHECK-NEXT: 1 1 0.33 incw %di +# CHECK-NEXT: 3 7 1.00 * * incw (%rax) +# CHECK-NEXT: 1 1 0.33 incl %edi +# CHECK-NEXT: 3 7 1.00 * * incl (%rax) +# CHECK-NEXT: 1 1 0.33 incq %rdi +# CHECK-NEXT: 3 7 1.00 * * incq (%rax) +# CHECK-NEXT: 1 100 0.33 U insb %dx, %es:(%rdi) +# CHECK-NEXT: 1 100 0.33 U insw %dx, %es:(%rdi) +# CHECK-NEXT: 1 100 0.33 U insl %dx, %es:(%rdi) +# CHECK-NEXT: 1 100 0.33 * * U int $7 +# CHECK-NEXT: 1 1 0.50 lahf +# CHECK-NEXT: 3 7 0.67 U lodsb (%rsi), %al +# CHECK-NEXT: 3 7 0.67 U lodsw (%rsi), %ax +# CHECK-NEXT: 2 6 0.50 U lodsl (%rsi), %eax +# CHECK-NEXT: 2 6 0.50 U lodsq (%rsi), %rax +# CHECK-NEXT: 5 8 1.00 U movsb (%rsi), %es:(%rdi) +# CHECK-NEXT: 5 8 1.00 U movsw (%rsi), %es:(%rdi) +# CHECK-NEXT: 5 8 1.00 U movsl (%rsi), %es:(%rdi) +# CHECK-NEXT: 5 8 1.00 U movsq (%rsi), %es:(%rdi) +# CHECK-NEXT: 1 1 0.33 movsbw %al, %di +# CHECK-NEXT: 1 1 0.33 movzbw %al, %di +# CHECK-NEXT: 1 5 0.50 * movsbw (%rax), %di +# CHECK-NEXT: 1 5 0.50 * movzbw (%rax), %di +# CHECK-NEXT: 1 1 0.33 movsbl %al, %edi +# CHECK-NEXT: 1 1 0.33 movzbl %al, %edi +# CHECK-NEXT: 1 5 0.50 * movsbl (%rax), %edi +# CHECK-NEXT: 1 5 0.50 * movzbl (%rax), %edi +# CHECK-NEXT: 1 1 0.33 movsbq %al, %rdi +# CHECK-NEXT: 1 1 0.33 movzbq %al, %rdi +# CHECK-NEXT: 1 5 0.50 * movsbq (%rax), %rdi +# CHECK-NEXT: 1 5 0.50 * movzbq (%rax), %rdi +# CHECK-NEXT: 1 1 0.33 movswl %ax, %edi +# CHECK-NEXT: 1 1 0.33 movzwl %ax, %edi +# CHECK-NEXT: 1 5 0.50 * movswl (%rax), %edi +# CHECK-NEXT: 1 5 0.50 * movzwl (%rax), %edi +# CHECK-NEXT: 1 1 0.33 movswq %ax, %rdi +# CHECK-NEXT: 1 1 0.33 movzwq %ax, %rdi +# CHECK-NEXT: 1 5 0.50 * movswq (%rax), %rdi +# CHECK-NEXT: 1 5 0.50 * movzwq (%rax), %rdi +# CHECK-NEXT: 1 1 0.33 movslq %eax, %rdi +# CHECK-NEXT: 1 5 0.50 * movslq (%rax), %rdi +# CHECK-NEXT: 1 3 1.00 mulb %dil +# CHECK-NEXT: 2 8 1.00 * mulb (%rax) +# CHECK-NEXT: 4 4 1.33 mulw %si +# CHECK-NEXT: 5 9 1.33 * mulw (%rax) +# CHECK-NEXT: 3 4 1.00 mull %edx +# CHECK-NEXT: 4 9 1.00 * mull (%rax) +# CHECK-NEXT: 2 4 1.00 mulq %rcx +# CHECK-NEXT: 3 9 1.00 * mulq (%rax) +# CHECK-NEXT: 1 1 0.33 negb %dil +# CHECK-NEXT: 3 7 1.00 * * negb (%r8) +# CHECK-NEXT: 1 1 0.33 negw %si +# CHECK-NEXT: 3 7 1.00 * * negw (%r9) +# CHECK-NEXT: 1 1 0.33 negl %edx +# CHECK-NEXT: 3 7 1.00 * * negl (%rax) +# CHECK-NEXT: 1 1 0.33 negq %rcx +# CHECK-NEXT: 3 7 1.00 * * negq (%r10) +# CHECK-NEXT: 1 1 0.25 nop +# CHECK-NEXT: 1 1 0.25 nopw %di +# CHECK-NEXT: 1 1 0.25 nopw (%rcx) +# CHECK-NEXT: 1 1 0.25 nopl %esi +# CHECK-NEXT: 1 1 0.25 nopl (%r8) +# CHECK-NEXT: 1 1 0.25 nopq %rdx +# CHECK-NEXT: 1 1 0.25 nopq (%r9) +# CHECK-NEXT: 1 1 0.33 notb %dil +# CHECK-NEXT: 3 7 1.00 * * notb (%r8) +# CHECK-NEXT: 1 1 0.33 notw %si +# CHECK-NEXT: 3 7 1.00 * * notw (%r9) +# CHECK-NEXT: 1 1 0.33 notl %edx +# CHECK-NEXT: 3 7 1.00 * * notl (%rax) +# CHECK-NEXT: 1 1 0.33 notq %rcx +# CHECK-NEXT: 3 7 1.00 * * notq (%r10) +# CHECK-NEXT: 1 1 0.33 orb $7, %al +# CHECK-NEXT: 1 1 0.33 orb $7, %dil +# CHECK-NEXT: 3 7 1.00 * * orb $7, (%rax) +# CHECK-NEXT: 1 1 0.33 orb %sil, %dil +# CHECK-NEXT: 3 7 1.00 * * orb %sil, (%rax) +# CHECK-NEXT: 2 6 0.50 * orb (%rax), %dil +# CHECK-NEXT: 1 1 0.33 orw $511, %ax +# CHECK-NEXT: 1 1 0.33 orw $511, %di +# CHECK-NEXT: 3 7 1.00 * * orw $511, (%rax) +# CHECK-NEXT: 1 1 0.33 orw $7, %di +# CHECK-NEXT: 3 7 1.00 * * orw $7, (%rax) +# CHECK-NEXT: 1 1 0.33 orw %si, %di +# CHECK-NEXT: 3 7 1.00 * * orw %si, (%rax) +# CHECK-NEXT: 2 6 0.50 * orw (%rax), %di +# CHECK-NEXT: 1 1 0.33 orl $665536, %eax +# CHECK-NEXT: 1 1 0.33 orl $665536, %edi +# CHECK-NEXT: 3 7 1.00 * * orl $665536, (%rax) +# CHECK-NEXT: 1 1 0.33 orl $7, %edi +# CHECK-NEXT: 3 7 1.00 * * orl $7, (%rax) +# CHECK-NEXT: 1 1 0.33 orl %esi, %edi +# CHECK-NEXT: 3 7 1.00 * * orl %esi, (%rax) +# CHECK-NEXT: 2 6 0.50 * orl (%rax), %edi +# CHECK-NEXT: 1 1 0.33 orq $665536, %rax +# CHECK-NEXT: 1 1 0.33 orq $665536, %rdi +# CHECK-NEXT: 3 7 1.00 * * orq $665536, (%rax) +# CHECK-NEXT: 1 1 0.33 orq $7, %rdi +# CHECK-NEXT: 3 7 1.00 * * orq $7, (%rax) +# CHECK-NEXT: 1 1 0.33 orq %rsi, %rdi +# CHECK-NEXT: 3 7 1.00 * * orq %rsi, (%rax) +# CHECK-NEXT: 2 6 0.50 * orq (%rax), %rdi +# CHECK-NEXT: 1 100 0.33 U outb %al, $7 +# CHECK-NEXT: 1 100 0.33 U outb %al, %dx +# CHECK-NEXT: 1 100 0.33 U outw %ax, $7 +# CHECK-NEXT: 1 100 0.33 U outw %ax, %dx +# CHECK-NEXT: 1 100 0.33 U outl %eax, $7 +# CHECK-NEXT: 1 100 0.33 U outl %eax, %dx +# CHECK-NEXT: 1 100 0.33 U outsb (%rsi), %dx +# CHECK-NEXT: 1 100 0.33 U outsw (%rsi), %dx +# CHECK-NEXT: 1 100 0.33 U outsl (%rsi), %dx +# CHECK-NEXT: 4 4 1.33 * * U pause +# CHECK-NEXT: 3 2 1.50 rclb %dil +# CHECK-NEXT: 3 2 1.50 rcrb %dil +# CHECK-NEXT: 11 11 3.50 * rclb (%rax) +# CHECK-NEXT: 11 11 3.50 * rcrb (%rax) +# CHECK-NEXT: 8 5 4.00 rclb $7, %dil +# CHECK-NEXT: 8 5 4.00 rcrb $7, %dil +# CHECK-NEXT: 11 11 3.50 * rclb $7, (%rax) +# CHECK-NEXT: 11 11 3.50 * rcrb $7, (%rax) +# CHECK-NEXT: 8 5 4.00 rclb %cl, %dil +# CHECK-NEXT: 8 5 4.00 rcrb %cl, %dil +# CHECK-NEXT: 11 11 3.50 * rclb %cl, (%rax) +# CHECK-NEXT: 11 11 3.50 * rcrb %cl, (%rax) +# CHECK-NEXT: 3 2 1.50 rclw %di +# CHECK-NEXT: 3 2 1.50 rcrw %di +# CHECK-NEXT: 11 11 3.50 * rclw (%rax) +# CHECK-NEXT: 11 11 3.50 * rcrw (%rax) +# CHECK-NEXT: 8 5 4.00 rclw $7, %di +# CHECK-NEXT: 8 5 4.00 rcrw $7, %di +# CHECK-NEXT: 11 11 3.50 * rclw $7, (%rax) +# CHECK-NEXT: 11 11 3.50 * rcrw $7, (%rax) +# CHECK-NEXT: 8 5 4.00 rclw %cl, %di +# CHECK-NEXT: 8 5 4.00 rcrw %cl, %di +# CHECK-NEXT: 11 11 3.50 * rclw %cl, (%rax) +# CHECK-NEXT: 11 11 3.50 * rcrw %cl, (%rax) +# CHECK-NEXT: 3 2 1.50 rcll %edi +# CHECK-NEXT: 3 2 1.50 rcrl %edi +# CHECK-NEXT: 11 11 3.50 * rcll (%rax) +# CHECK-NEXT: 11 11 3.50 * rcrl (%rax) +# CHECK-NEXT: 8 5 4.00 rcll $7, %edi +# CHECK-NEXT: 8 5 4.00 rcrl $7, %edi +# CHECK-NEXT: 11 11 3.50 * rcll $7, (%rax) +# CHECK-NEXT: 11 11 3.50 * rcrl $7, (%rax) +# CHECK-NEXT: 8 5 4.00 rcll %cl, %edi +# CHECK-NEXT: 8 5 4.00 rcrl %cl, %edi +# CHECK-NEXT: 11 11 3.50 * rcll %cl, (%rax) +# CHECK-NEXT: 11 11 3.50 * rcrl %cl, (%rax) +# CHECK-NEXT: 3 2 1.50 rclq %rdi +# CHECK-NEXT: 3 2 1.50 rcrq %rdi +# CHECK-NEXT: 11 11 3.50 * rclq (%rax) +# CHECK-NEXT: 11 11 3.50 * rcrq (%rax) +# CHECK-NEXT: 8 5 4.00 rclq $7, %rdi +# CHECK-NEXT: 8 5 4.00 rcrq $7, %rdi +# CHECK-NEXT: 11 11 3.50 * rclq $7, (%rax) +# CHECK-NEXT: 11 11 3.50 * rcrq $7, (%rax) +# CHECK-NEXT: 8 5 4.00 rclq %cl, %rdi +# CHECK-NEXT: 8 5 4.00 rcrq %cl, %rdi +# CHECK-NEXT: 11 11 3.50 * rclq %cl, (%rax) +# CHECK-NEXT: 11 11 3.50 * rcrq %cl, (%rax) +# CHECK-NEXT: 2 2 1.00 rolb %dil +# CHECK-NEXT: 2 2 1.00 rorb %dil +# CHECK-NEXT: 5 8 1.00 * * rolb (%rax) +# CHECK-NEXT: 5 8 1.00 * * rorb (%rax) +# CHECK-NEXT: 2 2 1.00 rolb $7, %dil +# CHECK-NEXT: 2 2 1.00 rorb $7, %dil +# CHECK-NEXT: 5 8 1.00 * * rolb $7, (%rax) +# CHECK-NEXT: 5 8 1.00 * * rorb $7, (%rax) +# CHECK-NEXT: 3 3 1.50 rolb %cl, %dil +# CHECK-NEXT: 3 3 1.50 rorb %cl, %dil +# CHECK-NEXT: 6 9 1.50 * * rolb %cl, (%rax) +# CHECK-NEXT: 6 9 1.50 * * rorb %cl, (%rax) +# CHECK-NEXT: 2 2 1.00 rolw %di +# CHECK-NEXT: 2 2 1.00 rorw %di +# CHECK-NEXT: 5 8 1.00 * * rolw (%rax) +# CHECK-NEXT: 5 8 1.00 * * rorw (%rax) +# CHECK-NEXT: 2 2 1.00 rolw $7, %di +# CHECK-NEXT: 2 2 1.00 rorw $7, %di +# CHECK-NEXT: 5 8 1.00 * * rolw $7, (%rax) +# CHECK-NEXT: 5 8 1.00 * * rorw $7, (%rax) +# CHECK-NEXT: 3 3 1.50 rolw %cl, %di +# CHECK-NEXT: 3 3 1.50 rorw %cl, %di +# CHECK-NEXT: 6 9 1.50 * * rolw %cl, (%rax) +# CHECK-NEXT: 6 9 1.50 * * rorw %cl, (%rax) +# CHECK-NEXT: 2 2 1.00 roll %edi +# CHECK-NEXT: 2 2 1.00 rorl %edi +# CHECK-NEXT: 5 8 1.00 * * roll (%rax) +# CHECK-NEXT: 5 8 1.00 * * rorl (%rax) +# CHECK-NEXT: 2 2 1.00 roll $7, %edi +# CHECK-NEXT: 2 2 1.00 rorl $7, %edi +# CHECK-NEXT: 5 8 1.00 * * roll $7, (%rax) +# CHECK-NEXT: 5 8 1.00 * * rorl $7, (%rax) +# CHECK-NEXT: 3 3 1.50 roll %cl, %edi +# CHECK-NEXT: 3 3 1.50 rorl %cl, %edi +# CHECK-NEXT: 6 9 1.50 * * roll %cl, (%rax) +# CHECK-NEXT: 6 9 1.50 * * rorl %cl, (%rax) +# CHECK-NEXT: 2 2 1.00 rolq %rdi +# CHECK-NEXT: 2 2 1.00 rorq %rdi +# CHECK-NEXT: 5 8 1.00 * * rolq (%rax) +# CHECK-NEXT: 5 8 1.00 * * rorq (%rax) +# CHECK-NEXT: 2 2 1.00 rolq $7, %rdi +# CHECK-NEXT: 2 2 1.00 rorq $7, %rdi +# CHECK-NEXT: 5 8 1.00 * * rolq $7, (%rax) +# CHECK-NEXT: 5 8 1.00 * * rorq $7, (%rax) +# CHECK-NEXT: 3 3 1.50 rolq %cl, %rdi +# CHECK-NEXT: 3 3 1.50 rorq %cl, %rdi +# CHECK-NEXT: 6 9 1.50 * * rolq %cl, (%rax) +# CHECK-NEXT: 6 9 1.50 * * rorq %cl, (%rax) +# CHECK-NEXT: 1 1 0.50 sahf +# CHECK-NEXT: 1 1 0.50 sarb %dil +# CHECK-NEXT: 1 1 0.50 shlb %dil +# CHECK-NEXT: 1 1 0.50 shrb %dil +# CHECK-NEXT: 4 7 1.00 * * sarb (%rax) +# CHECK-NEXT: 4 7 1.00 * * shlb (%rax) +# CHECK-NEXT: 4 7 1.00 * * shrb (%rax) +# CHECK-NEXT: 1 1 0.50 sarb $7, %dil +# CHECK-NEXT: 1 1 0.50 shlb $7, %dil +# CHECK-NEXT: 1 1 0.50 shrb $7, %dil +# CHECK-NEXT: 4 7 1.00 * * sarb $7, (%rax) +# CHECK-NEXT: 4 7 1.00 * * shlb $7, (%rax) +# CHECK-NEXT: 4 7 1.00 * * shrb $7, (%rax) +# CHECK-NEXT: 3 3 1.50 sarb %cl, %dil +# CHECK-NEXT: 3 3 1.50 shlb %cl, %dil +# CHECK-NEXT: 3 3 1.50 shrb %cl, %dil +# CHECK-NEXT: 6 9 1.50 * * sarb %cl, (%rax) +# CHECK-NEXT: 6 9 1.50 * * shlb %cl, (%rax) +# CHECK-NEXT: 6 9 1.50 * * shrb %cl, (%rax) +# CHECK-NEXT: 1 1 0.50 sarw %di +# CHECK-NEXT: 1 1 0.50 shlw %di +# CHECK-NEXT: 1 1 0.50 shrw %di +# CHECK-NEXT: 4 7 1.00 * * sarw (%rax) +# CHECK-NEXT: 4 7 1.00 * * shlw (%rax) +# CHECK-NEXT: 4 7 1.00 * * shrw (%rax) +# CHECK-NEXT: 1 1 0.50 sarw $7, %di +# CHECK-NEXT: 1 1 0.50 shlw $7, %di +# CHECK-NEXT: 1 1 0.50 shrw $7, %di +# CHECK-NEXT: 4 7 1.00 * * sarw $7, (%rax) +# CHECK-NEXT: 4 7 1.00 * * shlw $7, (%rax) +# CHECK-NEXT: 4 7 1.00 * * shrw $7, (%rax) +# CHECK-NEXT: 3 3 1.50 sarw %cl, %di +# CHECK-NEXT: 3 3 1.50 shlw %cl, %di +# CHECK-NEXT: 3 3 1.50 shrw %cl, %di +# CHECK-NEXT: 6 9 1.50 * * sarw %cl, (%rax) +# CHECK-NEXT: 6 9 1.50 * * shlw %cl, (%rax) +# CHECK-NEXT: 6 9 1.50 * * shrw %cl, (%rax) +# CHECK-NEXT: 1 1 0.50 sarl %edi +# CHECK-NEXT: 1 1 0.50 shll %edi +# CHECK-NEXT: 1 1 0.50 shrl %edi +# CHECK-NEXT: 4 7 1.00 * * sarl (%rax) +# CHECK-NEXT: 4 7 1.00 * * shll (%rax) +# CHECK-NEXT: 4 7 1.00 * * shrl (%rax) +# CHECK-NEXT: 1 1 0.50 sarl $7, %edi +# CHECK-NEXT: 1 1 0.50 shll $7, %edi +# CHECK-NEXT: 1 1 0.50 shrl $7, %edi +# CHECK-NEXT: 4 7 1.00 * * sarl $7, (%rax) +# CHECK-NEXT: 4 7 1.00 * * shll $7, (%rax) +# CHECK-NEXT: 4 7 1.00 * * shrl $7, (%rax) +# CHECK-NEXT: 3 3 1.50 sarl %cl, %edi +# CHECK-NEXT: 3 3 1.50 shll %cl, %edi +# CHECK-NEXT: 3 3 1.50 shrl %cl, %edi +# CHECK-NEXT: 6 9 1.50 * * sarl %cl, (%rax) +# CHECK-NEXT: 6 9 1.50 * * shll %cl, (%rax) +# CHECK-NEXT: 6 9 1.50 * * shrl %cl, (%rax) +# CHECK-NEXT: 1 1 0.50 sarq %rdi +# CHECK-NEXT: 1 1 0.50 shlq %rdi +# CHECK-NEXT: 1 1 0.50 shrq %rdi +# CHECK-NEXT: 4 7 1.00 * * sarq (%rax) +# CHECK-NEXT: 4 7 1.00 * * shlq (%rax) +# CHECK-NEXT: 4 7 1.00 * * shrq (%rax) +# CHECK-NEXT: 1 1 0.50 sarq $7, %rdi +# CHECK-NEXT: 1 1 0.50 shlq $7, %rdi +# CHECK-NEXT: 1 1 0.50 shrq $7, %rdi +# CHECK-NEXT: 4 7 1.00 * * sarq $7, (%rax) +# CHECK-NEXT: 4 7 1.00 * * shlq $7, (%rax) +# CHECK-NEXT: 4 7 1.00 * * shrq $7, (%rax) +# CHECK-NEXT: 3 3 1.50 sarq %cl, %rdi +# CHECK-NEXT: 3 3 1.50 shlq %cl, %rdi +# CHECK-NEXT: 3 3 1.50 shrq %cl, %rdi +# CHECK-NEXT: 6 9 1.50 * * sarq %cl, (%rax) +# CHECK-NEXT: 6 9 1.50 * * shlq %cl, (%rax) +# CHECK-NEXT: 6 9 1.50 * * shrq %cl, (%rax) +# CHECK-NEXT: 2 2 0.67 sbbb $7, %al +# CHECK-NEXT: 2 2 0.67 sbbb $7, %dil +# CHECK-NEXT: 6 9 1.00 * * sbbb $7, (%rax) +# CHECK-NEXT: 2 2 0.67 sbbb %sil, %dil +# CHECK-NEXT: 6 9 1.00 * * sbbb %sil, (%rax) +# CHECK-NEXT: 3 7 0.67 * sbbb (%rax), %dil +# CHECK-NEXT: 2 2 0.67 sbbw $511, %ax +# CHECK-NEXT: 2 2 0.67 sbbw $511, %di +# CHECK-NEXT: 6 9 1.00 * * sbbw $511, (%rax) +# CHECK-NEXT: 2 2 0.67 sbbw $7, %di +# CHECK-NEXT: 6 9 1.00 * * sbbw $7, (%rax) +# CHECK-NEXT: 2 2 0.67 sbbw %si, %di +# CHECK-NEXT: 6 9 1.00 * * sbbw %si, (%rax) +# CHECK-NEXT: 3 7 0.67 * sbbw (%rax), %di +# CHECK-NEXT: 2 2 0.67 sbbl $665536, %eax +# CHECK-NEXT: 2 2 0.67 sbbl $665536, %edi +# CHECK-NEXT: 6 9 1.00 * * sbbl $665536, (%rax) +# CHECK-NEXT: 2 2 0.67 sbbl $7, %edi +# CHECK-NEXT: 6 9 1.00 * * sbbl $7, (%rax) +# CHECK-NEXT: 2 2 0.67 sbbl %esi, %edi +# CHECK-NEXT: 6 9 1.00 * * sbbl %esi, (%rax) +# CHECK-NEXT: 3 7 0.67 * sbbl (%rax), %edi +# CHECK-NEXT: 2 2 0.67 sbbq $665536, %rax +# CHECK-NEXT: 2 2 0.67 sbbq $665536, %rdi +# CHECK-NEXT: 6 9 1.00 * * sbbq $665536, (%rax) +# CHECK-NEXT: 2 2 0.67 sbbq $7, %rdi +# CHECK-NEXT: 6 9 1.00 * * sbbq $7, (%rax) +# CHECK-NEXT: 2 2 0.67 sbbq %rsi, %rdi +# CHECK-NEXT: 6 9 1.00 * * sbbq %rsi, (%rax) +# CHECK-NEXT: 3 7 0.67 * sbbq (%rax), %rdi +# CHECK-NEXT: 2 2 0.67 U scasb %es:(%rdi), %al +# CHECK-NEXT: 2 2 0.67 U scasw %es:(%rdi), %ax +# CHECK-NEXT: 2 2 0.67 U scasl %es:(%rdi), %eax +# CHECK-NEXT: 2 2 0.67 U scasq %es:(%rdi), %rax +# CHECK-NEXT: 1 1 0.50 seto %al +# CHECK-NEXT: 3 2 1.00 * seto (%rax) +# CHECK-NEXT: 1 1 0.50 setno %al +# CHECK-NEXT: 3 2 1.00 * setno (%rax) +# CHECK-NEXT: 1 1 0.50 setb %al +# CHECK-NEXT: 3 2 1.00 * setb (%rax) +# CHECK-NEXT: 1 1 0.50 setae %al +# CHECK-NEXT: 3 2 1.00 * setae (%rax) +# CHECK-NEXT: 1 1 0.50 sete %al +# CHECK-NEXT: 3 2 1.00 * sete (%rax) +# CHECK-NEXT: 1 1 0.50 setne %al +# CHECK-NEXT: 3 2 1.00 * setne (%rax) +# CHECK-NEXT: 2 2 1.00 seta %al +# CHECK-NEXT: 4 3 1.00 * seta (%rax) +# CHECK-NEXT: 2 2 1.00 setbe %al +# CHECK-NEXT: 4 3 1.00 * setbe (%rax) +# CHECK-NEXT: 1 1 0.50 sets %al +# CHECK-NEXT: 3 2 1.00 * sets (%rax) +# CHECK-NEXT: 1 1 0.50 setns %al +# CHECK-NEXT: 3 2 1.00 * setns (%rax) +# CHECK-NEXT: 1 1 0.50 setp %al +# CHECK-NEXT: 3 2 1.00 * setp (%rax) +# CHECK-NEXT: 1 1 0.50 setnp %al +# CHECK-NEXT: 3 2 1.00 * setnp (%rax) +# CHECK-NEXT: 1 1 0.50 setl %al +# CHECK-NEXT: 3 2 1.00 * setl (%rax) +# CHECK-NEXT: 1 1 0.50 setge %al +# CHECK-NEXT: 3 2 1.00 * setge (%rax) +# CHECK-NEXT: 1 1 0.50 setg %al +# CHECK-NEXT: 3 2 1.00 * setg (%rax) +# CHECK-NEXT: 1 1 0.50 setle %al +# CHECK-NEXT: 3 2 1.00 * setle (%rax) +# CHECK-NEXT: 4 4 1.50 shldw %cl, %si, %di +# CHECK-NEXT: 4 4 1.50 shrdw %cl, %si, %di +# CHECK-NEXT: 7 10 1.50 * * shldw %cl, %si, (%rax) +# CHECK-NEXT: 7 10 1.50 * * shrdw %cl, %si, (%rax) +# CHECK-NEXT: 2 2 0.67 shldw $7, %si, %di +# CHECK-NEXT: 2 2 0.67 shrdw $7, %si, %di +# CHECK-NEXT: 5 8 1.00 * * shldw $7, %si, (%rax) +# CHECK-NEXT: 5 8 1.00 * * shrdw $7, %si, (%rax) +# CHECK-NEXT: 4 4 1.50 shldl %cl, %esi, %edi +# CHECK-NEXT: 4 4 1.50 shrdl %cl, %esi, %edi +# CHECK-NEXT: 7 10 1.50 * * shldl %cl, %esi, (%rax) +# CHECK-NEXT: 7 10 1.50 * * shrdl %cl, %esi, (%rax) +# CHECK-NEXT: 2 2 0.67 shldl $7, %esi, %edi +# CHECK-NEXT: 2 2 0.67 shrdl $7, %esi, %edi +# CHECK-NEXT: 5 8 1.00 * * shldl $7, %esi, (%rax) +# CHECK-NEXT: 5 8 1.00 * * shrdl $7, %esi, (%rax) +# CHECK-NEXT: 4 4 1.50 shldq %cl, %rsi, %rdi +# CHECK-NEXT: 4 4 1.50 shrdq %cl, %rsi, %rdi +# CHECK-NEXT: 7 10 1.50 * * shldq %cl, %rsi, (%rax) +# CHECK-NEXT: 7 10 1.50 * * shrdq %cl, %rsi, (%rax) +# CHECK-NEXT: 2 2 0.67 shldq $7, %rsi, %rdi +# CHECK-NEXT: 2 2 0.67 shrdq $7, %rsi, %rdi +# CHECK-NEXT: 5 8 1.00 * * shldq $7, %rsi, (%rax) +# CHECK-NEXT: 5 8 1.00 * * shrdq $7, %rsi, (%rax) +# CHECK-NEXT: 1 1 0.33 U stc +# CHECK-NEXT: 1 1 0.33 U std +# CHECK-NEXT: 3 5 1.00 U stosb %al, %es:(%rdi) +# CHECK-NEXT: 3 5 1.00 U stosw %ax, %es:(%rdi) +# CHECK-NEXT: 3 5 1.00 U stosl %eax, %es:(%rdi) +# CHECK-NEXT: 3 5 1.00 U stosq %rax, %es:(%rdi) +# CHECK-NEXT: 1 1 0.33 subb $7, %al +# CHECK-NEXT: 1 1 0.33 subb $7, %dil +# CHECK-NEXT: 3 7 1.00 * * subb $7, (%rax) +# CHECK-NEXT: 1 1 0.33 subb %sil, %dil +# CHECK-NEXT: 3 7 1.00 * * subb %sil, (%rax) +# CHECK-NEXT: 2 6 0.50 * subb (%rax), %dil +# CHECK-NEXT: 1 1 0.33 subw $511, %ax +# CHECK-NEXT: 1 1 0.33 subw $511, %di +# CHECK-NEXT: 3 7 1.00 * * subw $511, (%rax) +# CHECK-NEXT: 1 1 0.33 subw $7, %di +# CHECK-NEXT: 3 7 1.00 * * subw $7, (%rax) +# CHECK-NEXT: 1 1 0.33 subw %si, %di +# CHECK-NEXT: 3 7 1.00 * * subw %si, (%rax) +# CHECK-NEXT: 2 6 0.50 * subw (%rax), %di +# CHECK-NEXT: 1 1 0.33 subl $665536, %eax +# CHECK-NEXT: 1 1 0.33 subl $665536, %edi +# CHECK-NEXT: 3 7 1.00 * * subl $665536, (%rax) +# CHECK-NEXT: 1 1 0.33 subl $7, %edi +# CHECK-NEXT: 3 7 1.00 * * subl $7, (%rax) +# CHECK-NEXT: 1 1 0.33 subl %esi, %edi +# CHECK-NEXT: 3 7 1.00 * * subl %esi, (%rax) +# CHECK-NEXT: 2 6 0.50 * subl (%rax), %edi +# CHECK-NEXT: 1 1 0.33 subq $665536, %rax +# CHECK-NEXT: 1 1 0.33 subq $665536, %rdi +# CHECK-NEXT: 3 7 1.00 * * subq $665536, (%rax) +# CHECK-NEXT: 1 1 0.33 subq $7, %rdi +# CHECK-NEXT: 3 7 1.00 * * subq $7, (%rax) +# CHECK-NEXT: 1 1 0.33 subq %rsi, %rdi +# CHECK-NEXT: 3 7 1.00 * * subq %rsi, (%rax) +# CHECK-NEXT: 2 6 0.50 * subq (%rax), %rdi +# CHECK-NEXT: 1 1 0.33 testb $7, %al +# CHECK-NEXT: 1 1 0.33 testb $7, %dil +# CHECK-NEXT: 2 6 0.50 * testb $7, (%rax) +# CHECK-NEXT: 1 1 0.33 testb %sil, %dil +# CHECK-NEXT: 2 6 0.50 * testb %sil, (%rax) +# CHECK-NEXT: 1 1 0.33 testw $511, %ax +# CHECK-NEXT: 1 1 0.33 testw $511, %di +# CHECK-NEXT: 2 6 0.50 * testw $511, (%rax) +# CHECK-NEXT: 1 1 0.33 testw $7, %di +# CHECK-NEXT: 2 6 0.50 * testw $7, (%rax) +# CHECK-NEXT: 1 1 0.33 testw %si, %di +# CHECK-NEXT: 2 6 0.50 * testw %si, (%rax) +# CHECK-NEXT: 1 1 0.33 testl $665536, %eax +# CHECK-NEXT: 1 1 0.33 testl $665536, %edi +# CHECK-NEXT: 2 6 0.50 * testl $665536, (%rax) +# CHECK-NEXT: 1 1 0.33 testl $7, %edi +# CHECK-NEXT: 2 6 0.50 * testl $7, (%rax) +# CHECK-NEXT: 1 1 0.33 testl %esi, %edi +# CHECK-NEXT: 2 6 0.50 * testl %esi, (%rax) +# CHECK-NEXT: 1 1 0.33 testq $665536, %rax +# CHECK-NEXT: 1 1 0.33 testq $665536, %rdi +# CHECK-NEXT: 2 6 0.50 * testq $665536, (%rax) +# CHECK-NEXT: 1 1 0.33 testq $7, %rdi +# CHECK-NEXT: 2 6 0.50 * testq $7, (%rax) +# CHECK-NEXT: 1 1 0.33 testq %rsi, %rdi +# CHECK-NEXT: 2 6 0.50 * testq %rsi, (%rax) +# CHECK-NEXT: 1 100 0.33 * U ud2 +# CHECK-NEXT: 3 2 1.00 xaddb %bl, %cl +# CHECK-NEXT: 5 8 1.00 * * xaddb %bl, (%rcx) +# CHECK-NEXT: 3 2 1.00 xaddw %bx, %cx +# CHECK-NEXT: 5 8 1.00 * * xaddw %ax, (%rbx) +# CHECK-NEXT: 3 2 1.00 xaddl %ebx, %ecx +# CHECK-NEXT: 5 8 1.00 * * xaddl %eax, (%rbx) +# CHECK-NEXT: 3 2 1.00 xaddq %rbx, %rcx +# CHECK-NEXT: 5 8 1.00 * * xaddq %rax, (%rbx) +# CHECK-NEXT: 3 2 1.00 xchgb %bl, %cl +# CHECK-NEXT: 3 6 1.00 * * xchgb %bl, (%rbx) +# CHECK-NEXT: 3 2 1.00 xchgw %bx, %ax +# CHECK-NEXT: 3 2 1.00 xchgw %bx, %cx +# CHECK-NEXT: 3 6 1.00 * * xchgw %ax, (%rbx) +# CHECK-NEXT: 3 2 1.00 xchgl %ebx, %eax +# CHECK-NEXT: 3 2 1.00 xchgl %ebx, %ecx +# CHECK-NEXT: 3 6 1.00 * * xchgl %eax, (%rbx) +# CHECK-NEXT: 3 2 1.00 xchgq %rbx, %rax +# CHECK-NEXT: 3 2 1.00 xchgq %rbx, %rcx +# CHECK-NEXT: 3 6 1.00 * * xchgq %rax, (%rbx) +# CHECK-NEXT: 1 5 0.50 * xlatb +# CHECK-NEXT: 1 1 0.33 xorb $7, %al +# CHECK-NEXT: 1 1 0.33 xorb $7, %dil +# CHECK-NEXT: 3 7 1.00 * * xorb $7, (%rax) +# CHECK-NEXT: 1 1 0.33 xorb %sil, %dil +# CHECK-NEXT: 3 7 1.00 * * xorb %sil, (%rax) +# CHECK-NEXT: 2 6 0.50 * xorb (%rax), %dil +# CHECK-NEXT: 1 1 0.33 xorw $511, %ax +# CHECK-NEXT: 1 1 0.33 xorw $511, %di +# CHECK-NEXT: 3 7 1.00 * * xorw $511, (%rax) +# CHECK-NEXT: 1 1 0.33 xorw $7, %di +# CHECK-NEXT: 3 7 1.00 * * xorw $7, (%rax) +# CHECK-NEXT: 1 1 0.33 xorw %si, %di +# CHECK-NEXT: 3 7 1.00 * * xorw %si, (%rax) +# CHECK-NEXT: 2 6 0.50 * xorw (%rax), %di +# CHECK-NEXT: 1 1 0.33 xorl $665536, %eax +# CHECK-NEXT: 1 1 0.33 xorl $665536, %edi +# CHECK-NEXT: 3 7 1.00 * * xorl $665536, (%rax) +# CHECK-NEXT: 1 1 0.33 xorl $7, %edi +# CHECK-NEXT: 3 7 1.00 * * xorl $7, (%rax) +# CHECK-NEXT: 1 1 0.33 xorl %esi, %edi +# CHECK-NEXT: 3 7 1.00 * * xorl %esi, (%rax) +# CHECK-NEXT: 2 6 0.50 * xorl (%rax), %edi +# CHECK-NEXT: 1 1 0.33 xorq $665536, %rax +# CHECK-NEXT: 1 1 0.33 xorq $665536, %rdi +# CHECK-NEXT: 3 7 1.00 * * xorq $665536, (%rax) +# CHECK-NEXT: 1 1 0.33 xorq $7, %rdi +# CHECK-NEXT: 3 7 1.00 * * xorq $7, (%rax) +# CHECK-NEXT: 1 1 0.33 xorq %rsi, %rdi +# CHECK-NEXT: 3 7 1.00 * * xorq %rsi, (%rax) +# CHECK-NEXT: 2 6 0.50 * xorq (%rax), %rdi + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: 160.00 - 571.83 221.33 222.00 571.83 316.00 316.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcb $7, %al +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcb $7, %dil +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 adcb $7, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcb %sil, %dil +# CHECK-NEXT: - - 1.33 0.33 1.00 1.33 1.00 1.00 adcb %sil, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 adcb (%rax), %dil +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcw $511, %ax +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcw $511, %di +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 adcw $511, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcw $7, %di +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 adcw $7, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcw %si, %di +# CHECK-NEXT: - - 1.33 0.33 1.00 1.33 1.00 1.00 adcw %si, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 adcw (%rax), %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcl $665536, %eax +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcl $665536, %edi +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 adcl $665536, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcl $7, %edi +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 adcl $7, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcl %esi, %edi +# CHECK-NEXT: - - 1.33 0.33 1.00 1.33 1.00 1.00 adcl %esi, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 adcl (%rax), %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcq $665536, %rax +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcq $665536, %rdi +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 adcq $665536, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcq $7, %rdi +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 adcq $7, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcq %rsi, %rdi +# CHECK-NEXT: - - 1.33 0.33 1.00 1.33 1.00 1.00 adcq %rsi, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 adcq (%rax), %rdi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addb $7, %al +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addb $7, %dil +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 addb $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addb %sil, %dil +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 addb %sil, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 addb (%rax), %dil +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addw $511, %ax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addw $511, %di +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 addw $511, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addw $7, %di +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 addw $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addw %si, %di +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 addw %si, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 addw (%rax), %di +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addl $665536, %eax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addl $665536, %edi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 addl $665536, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addl $7, %edi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 addl $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addl %esi, %edi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 addl %esi, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 addl (%rax), %edi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addq $665536, %rax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addq $665536, %rdi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 addq $665536, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addq $7, %rdi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 addq $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addq %rsi, %rdi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 addq %rsi, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 addq (%rax), %rdi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andb $7, %al +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andb $7, %dil +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 andb $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andb %sil, %dil +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 andb %sil, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 andb (%rax), %dil +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andw $511, %ax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andw $511, %di +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 andw $511, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andw $7, %di +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 andw $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andw %si, %di +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 andw %si, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 andw (%rax), %di +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andl $665536, %eax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andl $665536, %edi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 andl $665536, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andl $7, %edi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 andl $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andl %esi, %edi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 andl %esi, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 andl (%rax), %edi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andq $665536, %rax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andq $665536, %rdi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 andq $665536, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andq $7, %rdi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 andq $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andq %rsi, %rdi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 andq %rsi, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 andq (%rax), %rdi +# CHECK-NEXT: - - - 1.00 - - - - bsfw %si, %di +# CHECK-NEXT: - - - 1.00 - - - - bsrw %si, %di +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 bsfw (%rax), %di +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 bsrw (%rax), %di +# CHECK-NEXT: - - - 1.00 - - - - bsfl %esi, %edi +# CHECK-NEXT: - - - 1.00 - - - - bsrl %esi, %edi +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 bsfl (%rax), %edi +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 bsrl (%rax), %edi +# CHECK-NEXT: - - - 1.00 - - - - bsfq %rsi, %rdi +# CHECK-NEXT: - - - 1.00 - - - - bsrq %rsi, %rdi +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 bsfq (%rax), %rdi +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 bsrq (%rax), %rdi +# CHECK-NEXT: - - - 1.00 - - - - bswapl %eax +# CHECK-NEXT: - - 0.50 1.00 - 0.50 - - bswapq %rax +# CHECK-NEXT: - - 0.50 - - 0.50 - - btw %si, %di +# CHECK-NEXT: - - 0.50 - - 0.50 - - btcw %si, %di +# CHECK-NEXT: - - 0.50 - - 0.50 - - btrw %si, %di +# CHECK-NEXT: - - 0.50 - - 0.50 - - btsw %si, %di +# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btw %si, (%rax) +# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btcw %si, (%rax) +# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btrw %si, (%rax) +# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btsw %si, (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - btw $7, %di +# CHECK-NEXT: - - 0.50 - - 0.50 - - btcw $7, %di +# CHECK-NEXT: - - 0.50 - - 0.50 - - btrw $7, %di +# CHECK-NEXT: - - 0.50 - - 0.50 - - btsw $7, %di +# CHECK-NEXT: - - 0.50 - - 0.50 0.50 0.50 btw $7, (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 btcw $7, (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 btrw $7, (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 btsw $7, (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - btl %esi, %edi +# CHECK-NEXT: - - 0.50 - - 0.50 - - btcl %esi, %edi +# CHECK-NEXT: - - 0.50 - - 0.50 - - btrl %esi, %edi +# CHECK-NEXT: - - 0.50 - - 0.50 - - btsl %esi, %edi +# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btl %esi, (%rax) +# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btcl %esi, (%rax) +# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btrl %esi, (%rax) +# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btsl %esi, (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - btl $7, %edi +# CHECK-NEXT: - - 0.50 - - 0.50 - - btcl $7, %edi +# CHECK-NEXT: - - 0.50 - - 0.50 - - btrl $7, %edi +# CHECK-NEXT: - - 0.50 - - 0.50 - - btsl $7, %edi +# CHECK-NEXT: - - 0.50 - - 0.50 0.50 0.50 btl $7, (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 btcl $7, (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 btrl $7, (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 btsl $7, (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - btq %rsi, %rdi +# CHECK-NEXT: - - 0.50 - - 0.50 - - btcq %rsi, %rdi +# CHECK-NEXT: - - 0.50 - - 0.50 - - btrq %rsi, %rdi +# CHECK-NEXT: - - 0.50 - - 0.50 - - btsq %rsi, %rdi +# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btq %rsi, (%rax) +# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btcq %rsi, (%rax) +# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btrq %rsi, (%rax) +# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btsq %rsi, (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - btq $7, %rdi +# CHECK-NEXT: - - 0.50 - - 0.50 - - btcq $7, %rdi +# CHECK-NEXT: - - 0.50 - - 0.50 - - btrq $7, %rdi +# CHECK-NEXT: - - 0.50 - - 0.50 - - btsq $7, %rdi +# CHECK-NEXT: - - 0.50 - - 0.50 0.50 0.50 btq $7, (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 btcq $7, (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 btrq $7, (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 btsq $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cbtw +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cwtl +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cltq +# CHECK-NEXT: - - 1.33 0.33 - 0.33 - - cwtd +# CHECK-NEXT: - - 0.50 - - 0.50 - - cltd +# CHECK-NEXT: - - 0.50 - - 0.50 - - cqto +# CHECK-NEXT: - - - - - - - - clc +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cld +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmc +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpb $7, %al +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpb $7, %dil +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpb $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpb %sil, %dil +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpb %sil, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpb (%rax), %dil +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpw $511, %ax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpw $511, %di +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpw $511, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpw $7, %di +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpw $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpw %si, %di +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpw %si, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpw (%rax), %di +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpl $665536, %eax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpl $665536, %edi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpl $665536, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpl $7, %edi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpl $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpl %esi, %edi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpl %esi, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpl (%rax), %edi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpq $665536, %rax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpq $665536, %rdi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpq $665536, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpq $7, %rdi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpq $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpq %rsi, %rdi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpq %rsi, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpq (%rax), %rdi +# CHECK-NEXT: - - 1.00 1.00 - 1.00 1.00 1.00 cmpsb %es:(%rdi), (%rsi) +# CHECK-NEXT: - - 1.00 1.00 - 1.00 1.00 1.00 cmpsw %es:(%rdi), (%rsi) +# CHECK-NEXT: - - 1.00 1.00 - 1.00 1.00 1.00 cmpsl %es:(%rdi), (%rsi) +# CHECK-NEXT: - - 1.00 1.00 - 1.00 1.00 1.00 cmpsq %es:(%rdi), (%rsi) +# CHECK-NEXT: - - 1.50 1.00 - 1.50 - - cmpxchgb %cl, %bl +# CHECK-NEXT: - - 0.33 0.33 1.00 2.33 1.00 1.00 cmpxchgb %cl, (%rbx) +# CHECK-NEXT: - - 1.50 1.00 - 1.50 - - cmpxchgw %cx, %bx +# CHECK-NEXT: - - 0.33 0.33 1.00 2.33 1.00 1.00 cmpxchgw %cx, (%rbx) +# CHECK-NEXT: - - 1.50 1.00 - 1.50 - - cmpxchgl %ecx, %ebx +# CHECK-NEXT: - - 0.33 0.33 1.00 2.33 1.00 1.00 cmpxchgl %ecx, (%rbx) +# CHECK-NEXT: - - 1.50 1.00 - 1.50 - - cmpxchgq %rcx, %rbx +# CHECK-NEXT: - - 0.33 0.33 1.00 2.33 1.00 1.00 cmpxchgq %rcx, (%rbx) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cpuid +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - decb %dil +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 decb (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - decw %di +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 decw (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - decl %edi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 decl (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - decq %rdi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 decq (%rax) +# CHECK-NEXT: 10.00 - 1.00 - - - - - divb %dil +# CHECK-NEXT: 10.00 - 1.00 - - - 0.50 0.50 divb (%rax) +# CHECK-NEXT: 10.00 - 1.00 - - - - - divw %si +# CHECK-NEXT: 10.00 - 1.00 - - - 0.50 0.50 divw (%rax) +# CHECK-NEXT: 10.00 - 1.00 - - - - - divl %edx +# CHECK-NEXT: 10.00 - 1.00 - - - 0.50 0.50 divl (%rax) +# CHECK-NEXT: 10.00 - 1.00 - - - - - divq %rcx +# CHECK-NEXT: 10.00 - 1.00 - - - 0.50 0.50 divq (%rax) +# CHECK-NEXT: 10.00 - 1.00 - - - - - idivb %dil +# CHECK-NEXT: 10.00 - 1.00 - - - 0.50 0.50 idivb (%rax) +# CHECK-NEXT: 10.00 - 1.00 - - - - - idivw %si +# CHECK-NEXT: 10.00 - 1.00 - - - 0.50 0.50 idivw (%rax) +# CHECK-NEXT: 10.00 - 1.00 - - - - - idivl %edx +# CHECK-NEXT: 10.00 - 1.00 - - - 0.50 0.50 idivl (%rax) +# CHECK-NEXT: 10.00 - 1.00 - - - - - idivq %rcx +# CHECK-NEXT: 10.00 - 1.00 - - - 0.50 0.50 idivq (%rax) +# CHECK-NEXT: - - - 1.00 - - - - imulb %dil +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 imulb (%rax) +# CHECK-NEXT: - - 1.17 1.67 - 1.17 - - imulw %di +# CHECK-NEXT: - - 1.17 1.67 - 1.17 0.50 0.50 imulw (%rax) +# CHECK-NEXT: - - - 1.00 - - - - imulw %si, %di +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 imulw (%rax), %di +# CHECK-NEXT: - - 0.33 1.33 - 0.33 - - imulw $511, %si, %di +# CHECK-NEXT: - - 0.33 1.33 - 0.33 0.50 0.50 imulw $511, (%rax), %di +# CHECK-NEXT: - - 0.33 1.33 - 0.33 - - imulw $7, %si, %di +# CHECK-NEXT: - - 0.33 1.33 - 0.33 0.50 0.50 imulw $7, (%rax), %di +# CHECK-NEXT: - - 0.83 1.33 - 0.83 - - imull %edi +# CHECK-NEXT: - - 0.83 1.33 - 0.83 0.50 0.50 imull (%rax) +# CHECK-NEXT: - - - 1.00 - - - - imull %esi, %edi +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 imull (%rax), %edi +# CHECK-NEXT: - - - 1.00 - - - - imull $665536, %esi, %edi +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 imull $665536, (%rax), %edi +# CHECK-NEXT: - - - 1.00 - - - - imull $7, %esi, %edi +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 imull $7, (%rax), %edi +# CHECK-NEXT: - - 1.00 1.00 - - - - imulq %rdi +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 imulq (%rax) +# CHECK-NEXT: - - - 1.00 - - - - imulq %rsi, %rdi +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 imulq (%rax), %rdi +# CHECK-NEXT: - - - 1.00 - - - - imulq $665536, %rsi, %rdi +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 imulq $665536, (%rax), %rdi +# CHECK-NEXT: - - - 1.00 - - - - imulq $7, %rsi, %rdi +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 imulq $7, (%rax), %rdi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - inb $7, %al +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - inb %dx, %al +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - inw $7, %ax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - inw %dx, %ax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - inl $7, %eax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - inl %dx, %eax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - incb %dil +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 incb (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - incw %di +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 incw (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - incl %edi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 incl (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - incq %rdi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 incq (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - insb %dx, %es:(%rdi) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - insw %dx, %es:(%rdi) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - insl %dx, %es:(%rdi) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - int $7 +# CHECK-NEXT: - - 0.50 - - 0.50 - - lahf +# CHECK-NEXT: - - 0.67 0.67 - 0.67 0.50 0.50 lodsb (%rsi), %al +# CHECK-NEXT: - - 0.67 0.67 - 0.67 0.50 0.50 lodsw (%rsi), %ax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 lodsl (%rsi), %eax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 lodsq (%rsi), %rax +# CHECK-NEXT: - - 0.67 0.67 1.00 0.67 1.00 1.00 movsb (%rsi), %es:(%rdi) +# CHECK-NEXT: - - 0.67 0.67 1.00 0.67 1.00 1.00 movsw (%rsi), %es:(%rdi) +# CHECK-NEXT: - - 0.67 0.67 1.00 0.67 1.00 1.00 movsl (%rsi), %es:(%rdi) +# CHECK-NEXT: - - 0.67 0.67 1.00 0.67 1.00 1.00 movsq (%rsi), %es:(%rdi) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movsbw %al, %di +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movzbw %al, %di +# CHECK-NEXT: - - - - - - 0.50 0.50 movsbw (%rax), %di +# CHECK-NEXT: - - - - - - 0.50 0.50 movzbw (%rax), %di +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movsbl %al, %edi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movzbl %al, %edi +# CHECK-NEXT: - - - - - - 0.50 0.50 movsbl (%rax), %edi +# CHECK-NEXT: - - - - - - 0.50 0.50 movzbl (%rax), %edi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movsbq %al, %rdi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movzbq %al, %rdi +# CHECK-NEXT: - - - - - - 0.50 0.50 movsbq (%rax), %rdi +# CHECK-NEXT: - - - - - - 0.50 0.50 movzbq (%rax), %rdi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movswl %ax, %edi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movzwl %ax, %edi +# CHECK-NEXT: - - - - - - 0.50 0.50 movswl (%rax), %edi +# CHECK-NEXT: - - - - - - 0.50 0.50 movzwl (%rax), %edi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movswq %ax, %rdi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movzwq %ax, %rdi +# CHECK-NEXT: - - - - - - 0.50 0.50 movswq (%rax), %rdi +# CHECK-NEXT: - - - - - - 0.50 0.50 movzwq (%rax), %rdi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movslq %eax, %rdi +# CHECK-NEXT: - - - - - - 0.50 0.50 movslq (%rax), %rdi +# CHECK-NEXT: - - - 1.00 - - - - mulb %dil +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 mulb (%rax) +# CHECK-NEXT: - - 1.17 1.67 - 1.17 - - mulw %si +# CHECK-NEXT: - - 1.17 1.67 - 1.17 0.50 0.50 mulw (%rax) +# CHECK-NEXT: - - 0.83 1.33 - 0.83 - - mull %edx +# CHECK-NEXT: - - 0.83 1.33 - 0.83 0.50 0.50 mull (%rax) +# CHECK-NEXT: - - 1.00 1.00 - - - - mulq %rcx +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 mulq (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - negb %dil +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 negb (%r8) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - negw %si +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 negw (%r9) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - negl %edx +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 negl (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - negq %rcx +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 negq (%r10) +# CHECK-NEXT: - - - - - - - - nop +# CHECK-NEXT: - - - - - - - - nopw %di +# CHECK-NEXT: - - - - - - - - nopw (%rcx) +# CHECK-NEXT: - - - - - - - - nopl %esi +# CHECK-NEXT: - - - - - - - - nopl (%r8) +# CHECK-NEXT: - - - - - - - - nopq %rdx +# CHECK-NEXT: - - - - - - - - nopq (%r9) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - notb %dil +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 notb (%r8) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - notw %si +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 notw (%r9) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - notl %edx +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 notl (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - notq %rcx +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 notq (%r10) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orb $7, %al +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orb $7, %dil +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 orb $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orb %sil, %dil +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 orb %sil, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 orb (%rax), %dil +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orw $511, %ax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orw $511, %di +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 orw $511, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orw $7, %di +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 orw $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orw %si, %di +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 orw %si, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 orw (%rax), %di +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orl $665536, %eax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orl $665536, %edi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 orl $665536, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orl $7, %edi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 orl $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orl %esi, %edi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 orl %esi, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 orl (%rax), %edi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orq $665536, %rax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orq $665536, %rdi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 orq $665536, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orq $7, %rdi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 orq $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orq %rsi, %rdi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 orq %rsi, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 orq (%rax), %rdi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - outb %al, $7 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - outb %al, %dx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - outw %ax, $7 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - outw %ax, %dx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - outl %eax, $7 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - outl %eax, %dx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - outsb (%rsi), %dx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - outsw (%rsi), %dx +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - outsl (%rsi), %dx +# CHECK-NEXT: - - 1.00 1.00 - 2.00 - - pause +# CHECK-NEXT: - - 1.50 - - 1.50 - - rclb %dil +# CHECK-NEXT: - - 1.50 - - 1.50 - - rcrb %dil +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rclb (%rax) +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrb (%rax) +# CHECK-NEXT: - - 4.00 - - 4.00 - - rclb $7, %dil +# CHECK-NEXT: - - 4.00 - - 4.00 - - rcrb $7, %dil +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rclb $7, (%rax) +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrb $7, (%rax) +# CHECK-NEXT: - - 4.00 - - 4.00 - - rclb %cl, %dil +# CHECK-NEXT: - - 4.00 - - 4.00 - - rcrb %cl, %dil +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rclb %cl, (%rax) +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrb %cl, (%rax) +# CHECK-NEXT: - - 1.50 - - 1.50 - - rclw %di +# CHECK-NEXT: - - 1.50 - - 1.50 - - rcrw %di +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rclw (%rax) +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrw (%rax) +# CHECK-NEXT: - - 4.00 - - 4.00 - - rclw $7, %di +# CHECK-NEXT: - - 4.00 - - 4.00 - - rcrw $7, %di +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rclw $7, (%rax) +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrw $7, (%rax) +# CHECK-NEXT: - - 4.00 - - 4.00 - - rclw %cl, %di +# CHECK-NEXT: - - 4.00 - - 4.00 - - rcrw %cl, %di +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rclw %cl, (%rax) +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrw %cl, (%rax) +# CHECK-NEXT: - - 1.50 - - 1.50 - - rcll %edi +# CHECK-NEXT: - - 1.50 - - 1.50 - - rcrl %edi +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcll (%rax) +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrl (%rax) +# CHECK-NEXT: - - 4.00 - - 4.00 - - rcll $7, %edi +# CHECK-NEXT: - - 4.00 - - 4.00 - - rcrl $7, %edi +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcll $7, (%rax) +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrl $7, (%rax) +# CHECK-NEXT: - - 4.00 - - 4.00 - - rcll %cl, %edi +# CHECK-NEXT: - - 4.00 - - 4.00 - - rcrl %cl, %edi +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcll %cl, (%rax) +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrl %cl, (%rax) +# CHECK-NEXT: - - 1.50 - - 1.50 - - rclq %rdi +# CHECK-NEXT: - - 1.50 - - 1.50 - - rcrq %rdi +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rclq (%rax) +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrq (%rax) +# CHECK-NEXT: - - 4.00 - - 4.00 - - rclq $7, %rdi +# CHECK-NEXT: - - 4.00 - - 4.00 - - rcrq $7, %rdi +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rclq $7, (%rax) +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrq $7, (%rax) +# CHECK-NEXT: - - 4.00 - - 4.00 - - rclq %cl, %rdi +# CHECK-NEXT: - - 4.00 - - 4.00 - - rcrq %cl, %rdi +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rclq %cl, (%rax) +# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrq %cl, (%rax) +# CHECK-NEXT: - - 1.00 - - 1.00 - - rolb %dil +# CHECK-NEXT: - - 1.00 - - 1.00 - - rorb %dil +# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rolb (%rax) +# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rorb (%rax) +# CHECK-NEXT: - - 1.00 - - 1.00 - - rolb $7, %dil +# CHECK-NEXT: - - 1.00 - - 1.00 - - rorb $7, %dil +# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rolb $7, (%rax) +# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rorb $7, (%rax) +# CHECK-NEXT: - - 1.50 - - 1.50 - - rolb %cl, %dil +# CHECK-NEXT: - - 1.50 - - 1.50 - - rorb %cl, %dil +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 rolb %cl, (%rax) +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 rorb %cl, (%rax) +# CHECK-NEXT: - - 1.00 - - 1.00 - - rolw %di +# CHECK-NEXT: - - 1.00 - - 1.00 - - rorw %di +# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rolw (%rax) +# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rorw (%rax) +# CHECK-NEXT: - - 1.00 - - 1.00 - - rolw $7, %di +# CHECK-NEXT: - - 1.00 - - 1.00 - - rorw $7, %di +# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rolw $7, (%rax) +# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rorw $7, (%rax) +# CHECK-NEXT: - - 1.50 - - 1.50 - - rolw %cl, %di +# CHECK-NEXT: - - 1.50 - - 1.50 - - rorw %cl, %di +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 rolw %cl, (%rax) +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 rorw %cl, (%rax) +# CHECK-NEXT: - - 1.00 - - 1.00 - - roll %edi +# CHECK-NEXT: - - 1.00 - - 1.00 - - rorl %edi +# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 roll (%rax) +# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rorl (%rax) +# CHECK-NEXT: - - 1.00 - - 1.00 - - roll $7, %edi +# CHECK-NEXT: - - 1.00 - - 1.00 - - rorl $7, %edi +# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 roll $7, (%rax) +# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rorl $7, (%rax) +# CHECK-NEXT: - - 1.50 - - 1.50 - - roll %cl, %edi +# CHECK-NEXT: - - 1.50 - - 1.50 - - rorl %cl, %edi +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 roll %cl, (%rax) +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 rorl %cl, (%rax) +# CHECK-NEXT: - - 1.00 - - 1.00 - - rolq %rdi +# CHECK-NEXT: - - 1.00 - - 1.00 - - rorq %rdi +# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rolq (%rax) +# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rorq (%rax) +# CHECK-NEXT: - - 1.00 - - 1.00 - - rolq $7, %rdi +# CHECK-NEXT: - - 1.00 - - 1.00 - - rorq $7, %rdi +# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rolq $7, (%rax) +# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rorq $7, (%rax) +# CHECK-NEXT: - - 1.50 - - 1.50 - - rolq %cl, %rdi +# CHECK-NEXT: - - 1.50 - - 1.50 - - rorq %cl, %rdi +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 rolq %cl, (%rax) +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 rorq %cl, (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - sahf +# CHECK-NEXT: - - 0.50 - - 0.50 - - sarb %dil +# CHECK-NEXT: - - 0.50 - - 0.50 - - shlb %dil +# CHECK-NEXT: - - 0.50 - - 0.50 - - shrb %dil +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 sarb (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shlb (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shrb (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - sarb $7, %dil +# CHECK-NEXT: - - 0.50 - - 0.50 - - shlb $7, %dil +# CHECK-NEXT: - - 0.50 - - 0.50 - - shrb $7, %dil +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 sarb $7, (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shlb $7, (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shrb $7, (%rax) +# CHECK-NEXT: - - 1.50 - - 1.50 - - sarb %cl, %dil +# CHECK-NEXT: - - 1.50 - - 1.50 - - shlb %cl, %dil +# CHECK-NEXT: - - 1.50 - - 1.50 - - shrb %cl, %dil +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 sarb %cl, (%rax) +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 shlb %cl, (%rax) +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 shrb %cl, (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - sarw %di +# CHECK-NEXT: - - 0.50 - - 0.50 - - shlw %di +# CHECK-NEXT: - - 0.50 - - 0.50 - - shrw %di +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 sarw (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shlw (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shrw (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - sarw $7, %di +# CHECK-NEXT: - - 0.50 - - 0.50 - - shlw $7, %di +# CHECK-NEXT: - - 0.50 - - 0.50 - - shrw $7, %di +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 sarw $7, (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shlw $7, (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shrw $7, (%rax) +# CHECK-NEXT: - - 1.50 - - 1.50 - - sarw %cl, %di +# CHECK-NEXT: - - 1.50 - - 1.50 - - shlw %cl, %di +# CHECK-NEXT: - - 1.50 - - 1.50 - - shrw %cl, %di +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 sarw %cl, (%rax) +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 shlw %cl, (%rax) +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 shrw %cl, (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - sarl %edi +# CHECK-NEXT: - - 0.50 - - 0.50 - - shll %edi +# CHECK-NEXT: - - 0.50 - - 0.50 - - shrl %edi +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 sarl (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shll (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shrl (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - sarl $7, %edi +# CHECK-NEXT: - - 0.50 - - 0.50 - - shll $7, %edi +# CHECK-NEXT: - - 0.50 - - 0.50 - - shrl $7, %edi +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 sarl $7, (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shll $7, (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shrl $7, (%rax) +# CHECK-NEXT: - - 1.50 - - 1.50 - - sarl %cl, %edi +# CHECK-NEXT: - - 1.50 - - 1.50 - - shll %cl, %edi +# CHECK-NEXT: - - 1.50 - - 1.50 - - shrl %cl, %edi +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 sarl %cl, (%rax) +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 shll %cl, (%rax) +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 shrl %cl, (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - sarq %rdi +# CHECK-NEXT: - - 0.50 - - 0.50 - - shlq %rdi +# CHECK-NEXT: - - 0.50 - - 0.50 - - shrq %rdi +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 sarq (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shlq (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shrq (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - sarq $7, %rdi +# CHECK-NEXT: - - 0.50 - - 0.50 - - shlq $7, %rdi +# CHECK-NEXT: - - 0.50 - - 0.50 - - shrq $7, %rdi +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 sarq $7, (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shlq $7, (%rax) +# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shrq $7, (%rax) +# CHECK-NEXT: - - 1.50 - - 1.50 - - sarq %cl, %rdi +# CHECK-NEXT: - - 1.50 - - 1.50 - - shlq %cl, %rdi +# CHECK-NEXT: - - 1.50 - - 1.50 - - shrq %cl, %rdi +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 sarq %cl, (%rax) +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 shlq %cl, (%rax) +# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 shrq %cl, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbb $7, %al +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbb $7, %dil +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 sbbb $7, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbb %sil, %dil +# CHECK-NEXT: - - 1.33 0.33 1.00 1.33 1.00 1.00 sbbb %sil, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 sbbb (%rax), %dil +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbw $511, %ax +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbw $511, %di +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 sbbw $511, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbw $7, %di +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 sbbw $7, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbw %si, %di +# CHECK-NEXT: - - 1.33 0.33 1.00 1.33 1.00 1.00 sbbw %si, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 sbbw (%rax), %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbl $665536, %eax +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbl $665536, %edi +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 sbbl $665536, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbl $7, %edi +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 sbbl $7, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbl %esi, %edi +# CHECK-NEXT: - - 1.33 0.33 1.00 1.33 1.00 1.00 sbbl %esi, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 sbbl (%rax), %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbq $665536, %rax +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbq $665536, %rdi +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 sbbq $665536, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbq $7, %rdi +# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 sbbq $7, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbq %rsi, %rdi +# CHECK-NEXT: - - 1.33 0.33 1.00 1.33 1.00 1.00 sbbq %rsi, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 sbbq (%rax), %rdi +# CHECK-NEXT: - - 0.67 0.67 - 0.67 - - scasb %es:(%rdi), %al +# CHECK-NEXT: - - 0.67 0.67 - 0.67 - - scasw %es:(%rdi), %ax +# CHECK-NEXT: - - 0.67 0.67 - 0.67 - - scasl %es:(%rdi), %eax +# CHECK-NEXT: - - 0.67 0.67 - 0.67 - - scasq %es:(%rdi), %rax +# CHECK-NEXT: - - 0.50 - - 0.50 - - seto %al +# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 seto (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - setno %al +# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 setno (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - setb %al +# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 setb (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - setae %al +# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 setae (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - sete %al +# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 sete (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - setne %al +# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 setne (%rax) +# CHECK-NEXT: - - 1.00 - - 1.00 - - seta %al +# CHECK-NEXT: - - 1.00 - 1.00 1.00 0.50 0.50 seta (%rax) +# CHECK-NEXT: - - 1.00 - - 1.00 - - setbe %al +# CHECK-NEXT: - - 1.00 - 1.00 1.00 0.50 0.50 setbe (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - sets %al +# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 sets (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - setns %al +# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 setns (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - setp %al +# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 setp (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - setnp %al +# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 setnp (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - setl %al +# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 setl (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - setge %al +# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 setge (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - setg %al +# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 setg (%rax) +# CHECK-NEXT: - - 0.50 - - 0.50 - - setle %al +# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 setle (%rax) +# CHECK-NEXT: - - 1.83 0.33 - 1.83 - - shldw %cl, %si, %di +# CHECK-NEXT: - - 1.83 0.33 - 1.83 - - shrdw %cl, %si, %di +# CHECK-NEXT: - - 1.83 0.33 1.00 1.83 1.00 1.00 shldw %cl, %si, (%rax) +# CHECK-NEXT: - - 1.83 0.33 1.00 1.83 1.00 1.00 shrdw %cl, %si, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - shldw $7, %si, %di +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - shrdw $7, %si, %di +# CHECK-NEXT: - - 0.83 0.33 1.00 0.83 1.00 1.00 shldw $7, %si, (%rax) +# CHECK-NEXT: - - 0.83 0.33 1.00 0.83 1.00 1.00 shrdw $7, %si, (%rax) +# CHECK-NEXT: - - 1.83 0.33 - 1.83 - - shldl %cl, %esi, %edi +# CHECK-NEXT: - - 1.83 0.33 - 1.83 - - shrdl %cl, %esi, %edi +# CHECK-NEXT: - - 1.83 0.33 1.00 1.83 1.00 1.00 shldl %cl, %esi, (%rax) +# CHECK-NEXT: - - 1.83 0.33 1.00 1.83 1.00 1.00 shrdl %cl, %esi, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - shldl $7, %esi, %edi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - shrdl $7, %esi, %edi +# CHECK-NEXT: - - 0.83 0.33 1.00 0.83 1.00 1.00 shldl $7, %esi, (%rax) +# CHECK-NEXT: - - 0.83 0.33 1.00 0.83 1.00 1.00 shrdl $7, %esi, (%rax) +# CHECK-NEXT: - - 1.83 0.33 - 1.83 - - shldq %cl, %rsi, %rdi +# CHECK-NEXT: - - 1.83 0.33 - 1.83 - - shrdq %cl, %rsi, %rdi +# CHECK-NEXT: - - 1.83 0.33 1.00 1.83 1.00 1.00 shldq %cl, %rsi, (%rax) +# CHECK-NEXT: - - 1.83 0.33 1.00 1.83 1.00 1.00 shrdq %cl, %rsi, (%rax) +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - shldq $7, %rsi, %rdi +# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - shrdq $7, %rsi, %rdi +# CHECK-NEXT: - - 0.83 0.33 1.00 0.83 1.00 1.00 shldq $7, %rsi, (%rax) +# CHECK-NEXT: - - 0.83 0.33 1.00 0.83 1.00 1.00 shrdq $7, %rsi, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - stc +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - std +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 0.50 0.50 stosb %al, %es:(%rdi) +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 0.50 0.50 stosw %ax, %es:(%rdi) +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 0.50 0.50 stosl %eax, %es:(%rdi) +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 0.50 0.50 stosq %rax, %es:(%rdi) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subb $7, %al +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subb $7, %dil +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 subb $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subb %sil, %dil +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 subb %sil, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 subb (%rax), %dil +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subw $511, %ax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subw $511, %di +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 subw $511, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subw $7, %di +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 subw $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subw %si, %di +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 subw %si, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 subw (%rax), %di +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subl $665536, %eax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subl $665536, %edi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 subl $665536, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subl $7, %edi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 subl $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subl %esi, %edi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 subl %esi, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 subl (%rax), %edi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subq $665536, %rax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subq $665536, %rdi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 subq $665536, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subq $7, %rdi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 subq $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subq %rsi, %rdi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 subq %rsi, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 subq (%rax), %rdi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testb $7, %al +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testb $7, %dil +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 testb $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testb %sil, %dil +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 testb %sil, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testw $511, %ax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testw $511, %di +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 testw $511, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testw $7, %di +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 testw $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testw %si, %di +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 testw %si, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testl $665536, %eax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testl $665536, %edi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 testl $665536, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testl $7, %edi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 testl $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testl %esi, %edi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 testl %esi, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testq $665536, %rax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testq $665536, %rdi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 testq $665536, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testq $7, %rdi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 testq $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testq %rsi, %rdi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 testq %rsi, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - ud2 +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - xaddb %bl, %cl +# CHECK-NEXT: - - 0.67 0.67 1.00 0.67 1.00 1.00 xaddb %bl, (%rcx) +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - xaddw %bx, %cx +# CHECK-NEXT: - - 0.67 0.67 1.00 0.67 1.00 1.00 xaddw %ax, (%rbx) +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - xaddl %ebx, %ecx +# CHECK-NEXT: - - 0.67 0.67 1.00 0.67 1.00 1.00 xaddl %eax, (%rbx) +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - xaddq %rbx, %rcx +# CHECK-NEXT: - - 0.67 0.67 1.00 0.67 1.00 1.00 xaddq %rax, (%rbx) +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - xchgb %bl, %cl +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xchgb %bl, (%rbx) +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - xchgw %bx, %ax +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - xchgw %bx, %cx +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xchgw %ax, (%rbx) +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - xchgl %ebx, %eax +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - xchgl %ebx, %ecx +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xchgl %eax, (%rbx) +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - xchgq %rbx, %rax +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - xchgq %rbx, %rcx +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xchgq %rax, (%rbx) +# CHECK-NEXT: - - - - - - 0.50 0.50 xlatb +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorb $7, %al +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorb $7, %dil +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xorb $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorb %sil, %dil +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xorb %sil, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 xorb (%rax), %dil +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorw $511, %ax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorw $511, %di +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xorw $511, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorw $7, %di +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xorw $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorw %si, %di +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xorw %si, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 xorw (%rax), %di +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorl $665536, %eax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorl $665536, %edi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xorl $665536, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorl $7, %edi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xorl $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorl %esi, %edi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xorl %esi, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 xorl (%rax), %edi +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorq $665536, %rax +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorq $665536, %rdi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xorq $665536, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorq $7, %rdi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xorq $7, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorq %rsi, %rdi +# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xorq %rsi, (%rax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 xorq (%rax), %rdi diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/resources-x87.s b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-x87.s new file mode 100644 index 00000000000..1cba9a7d77f --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-x87.s @@ -0,0 +1,521 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +f2xm1 + +fabs + +fadd %st(0), %st(1) +fadd %st(2) +fadds (%ecx) +faddl (%ecx) +faddp %st(1) +faddp %st(2) +fiadds (%ecx) +fiaddl (%ecx) + +fbld (%ecx) +fbstp (%eax) + +fchs + +fnclex + +fcmovb %st(1), %st(0) +fcmovbe %st(1), %st(0) +fcmove %st(1), %st(0) +fcmovnb %st(1), %st(0) +fcmovnbe %st(1), %st(0) +fcmovne %st(1), %st(0) +fcmovnu %st(1), %st(0) +fcmovu %st(1), %st(0) + +fcom %st(1) +fcom %st(3) +fcoms (%ecx) +fcoml (%eax) +fcomp %st(1) +fcomp %st(3) +fcomps (%ecx) +fcompl (%eax) +fcompp + +fcomi %st(3) +fcompi %st(3) + +fcos + +fdecstp + +fdiv %st(0), %st(1) +fdiv %st(2) +fdivs (%ecx) +fdivl (%eax) +fdivp %st(1) +fdivp %st(2) +fidivs (%ecx) +fidivl (%eax) + +fdivr %st(0), %st(1) +fdivr %st(2) +fdivrs (%ecx) +fdivrl (%eax) +fdivrp %st(1) +fdivrp %st(2) +fidivrs (%ecx) +fidivrl (%eax) + +ffree %st(0) + +ficoms (%ecx) +ficoml (%eax) +ficomps (%ecx) +ficompl (%eax) + +filds (%edx) +fildl (%ecx) +fildll (%eax) + +fincstp + +fninit + +fists (%edx) +fistl (%ecx) +fistps (%edx) +fistpl (%ecx) +fistpll (%eax) + +fisttps (%edx) +fisttpl (%ecx) +fisttpll (%eax) + +fld %st(0) +flds (%edx) +fldl (%ecx) +fldt (%eax) + +fldcw (%eax) +fldenv (%eax) + +fld1 +fldl2e +fldl2t +fldlg2 +fldln2 +fldpi +fldz + +fmul %st(0), %st(1) +fmul %st(2) +fmuls (%ecx) +fmull (%eax) +fmulp %st(1) +fmulp %st(2) +fimuls (%ecx) +fimull (%eax) + +fnop + +fpatan + +fprem +fprem1 + +fptan + +frndint + +frstor (%eax) + +fnsave (%eax) + +fscale + +fsin + +fsincos + +fsqrt + +fst %st(0) +fsts (%edx) +fstl (%ecx) +fstp %st(0) +fstpl (%edx) +fstpl (%ecx) +fstpt (%eax) + +fnstcw (%eax) +fnstenv (%eax) +fnstsw (%eax) + +frstor (%eax) +fsave (%eax) + +fsub %st(0), %st(1) +fsub %st(2) +fsubs (%ecx) +fsubl (%eax) +fsubp %st(1) +fsubp %st(2) +fisubs (%ecx) +fisubl (%eax) + +fsubr %st(0), %st(1) +fsubr %st(2) +fsubrs (%ecx) +fsubrl (%eax) +fsubrp %st(1) +fsubrp %st(2) +fisubrs (%ecx) +fisubrl (%eax) + +ftst + +fucom %st(1) +fucom %st(3) +fucomp %st(1) +fucomp %st(3) +fucompp + +fucomi %st(3) +fucompi %st(3) + +fwait + +fxam + +fxch %st(1) +fxch %st(3) + +fxrstor (%eax) +fxsave (%eax) + +fxtract + +fyl2x +fyl2xp1 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 100 0.33 U f2xm1 +# CHECK-NEXT: 1 1 1.00 U fabs +# CHECK-NEXT: 1 3 1.00 U fadd %st(0), %st(1) +# CHECK-NEXT: 1 3 1.00 U fadd %st(2) +# CHECK-NEXT: 2 10 1.00 * U fadds (%ecx) +# CHECK-NEXT: 2 10 1.00 * U faddl (%ecx) +# CHECK-NEXT: 1 3 1.00 U faddp %st(1) +# CHECK-NEXT: 1 3 1.00 U faddp %st(2) +# CHECK-NEXT: 3 13 2.00 * U fiadds (%ecx) +# CHECK-NEXT: 3 13 2.00 * U fiaddl (%ecx) +# CHECK-NEXT: 1 100 0.33 U fbld (%ecx) +# CHECK-NEXT: 1 100 0.33 U fbstp (%eax) +# CHECK-NEXT: 1 1 1.00 U fchs +# CHECK-NEXT: 1 100 0.33 U fnclex +# CHECK-NEXT: 3 3 2.00 U fcmovb %st(1), %st(0) +# CHECK-NEXT: 3 3 2.00 U fcmovbe %st(1), %st(0) +# CHECK-NEXT: 3 3 2.00 U fcmove %st(1), %st(0) +# CHECK-NEXT: 3 3 2.00 U fcmovnb %st(1), %st(0) +# CHECK-NEXT: 3 3 2.00 U fcmovnbe %st(1), %st(0) +# CHECK-NEXT: 3 3 2.00 U fcmovne %st(1), %st(0) +# CHECK-NEXT: 3 3 2.00 U fcmovnu %st(1), %st(0) +# CHECK-NEXT: 3 3 2.00 U fcmovu %st(1), %st(0) +# CHECK-NEXT: 1 1 1.00 U fcom %st(1) +# CHECK-NEXT: 1 1 1.00 U fcom %st(3) +# CHECK-NEXT: 2 8 1.00 U fcoms (%ecx) +# CHECK-NEXT: 2 8 1.00 U fcoml (%eax) +# CHECK-NEXT: 1 1 1.00 U fcomp %st(1) +# CHECK-NEXT: 1 1 1.00 U fcomp %st(3) +# CHECK-NEXT: 2 8 1.00 U fcomps (%ecx) +# CHECK-NEXT: 2 8 1.00 U fcompl (%eax) +# CHECK-NEXT: 1 100 0.33 U fcompp +# CHECK-NEXT: 3 3 1.00 U fcomi %st(3) +# CHECK-NEXT: 3 3 1.00 U fcompi %st(3) +# CHECK-NEXT: 1 100 0.33 U fcos +# CHECK-NEXT: 1 1 1.00 U fdecstp +# CHECK-NEXT: 1 14 14.00 U fdiv %st(0), %st(1) +# CHECK-NEXT: 1 14 14.00 U fdiv %st(2) +# CHECK-NEXT: 2 31 1.00 * U fdivs (%ecx) +# CHECK-NEXT: 2 31 1.00 * U fdivl (%eax) +# CHECK-NEXT: 1 14 14.00 U fdivp %st(1) +# CHECK-NEXT: 1 14 14.00 U fdivp %st(2) +# CHECK-NEXT: 3 34 1.00 * U fidivs (%ecx) +# CHECK-NEXT: 3 34 1.00 * U fidivl (%eax) +# CHECK-NEXT: 1 14 14.00 U fdivr %st(0), %st(1) +# CHECK-NEXT: 1 14 14.00 U fdivr %st(2) +# CHECK-NEXT: 2 31 1.00 * U fdivrs (%ecx) +# CHECK-NEXT: 2 31 1.00 * U fdivrl (%eax) +# CHECK-NEXT: 1 14 14.00 U fdivrp %st(1) +# CHECK-NEXT: 1 14 14.00 U fdivrp %st(2) +# CHECK-NEXT: 3 34 1.00 * U fidivrs (%ecx) +# CHECK-NEXT: 3 34 1.00 * U fidivrl (%eax) +# CHECK-NEXT: 1 1 1.00 U ffree %st(0) +# CHECK-NEXT: 3 11 2.00 U ficoms (%ecx) +# CHECK-NEXT: 3 11 2.00 U ficoml (%eax) +# CHECK-NEXT: 3 11 2.00 U ficomps (%ecx) +# CHECK-NEXT: 3 11 2.00 U ficompl (%eax) +# CHECK-NEXT: 2 10 1.00 * U filds (%edx) +# CHECK-NEXT: 2 10 1.00 * U fildl (%ecx) +# CHECK-NEXT: 2 10 1.00 * U fildll (%eax) +# CHECK-NEXT: 1 1 1.00 U fincstp +# CHECK-NEXT: 4 5 1.33 U fninit +# CHECK-NEXT: 4 9 1.00 * U fists (%edx) +# CHECK-NEXT: 4 9 1.00 * U fistl (%ecx) +# CHECK-NEXT: 4 9 1.00 * U fistps (%edx) +# CHECK-NEXT: 4 9 1.00 * U fistpl (%ecx) +# CHECK-NEXT: 4 9 1.00 * U fistpll (%eax) +# CHECK-NEXT: 3 5 1.00 * U fisttps (%edx) +# CHECK-NEXT: 3 5 1.00 * U fisttpl (%ecx) +# CHECK-NEXT: 3 5 1.00 * U fisttpll (%eax) +# CHECK-NEXT: 1 1 1.00 U fld %st(0) +# CHECK-NEXT: 3 9 1.00 * U flds (%edx) +# CHECK-NEXT: 3 9 1.00 * U fldl (%ecx) +# CHECK-NEXT: 3 9 1.00 * U fldt (%eax) +# CHECK-NEXT: 5 8 2.00 * U fldcw (%eax) +# CHECK-NEXT: 1 100 0.33 U fldenv (%eax) +# CHECK-NEXT: 2 1 1.00 U fld1 +# CHECK-NEXT: 2 1 1.00 U fldl2e +# CHECK-NEXT: 2 1 1.00 U fldl2t +# CHECK-NEXT: 2 1 1.00 U fldlg2 +# CHECK-NEXT: 2 1 1.00 U fldln2 +# CHECK-NEXT: 2 1 1.00 U fldpi +# CHECK-NEXT: 1 1 1.00 U fldz +# CHECK-NEXT: 1 5 1.00 U fmul %st(0), %st(1) +# CHECK-NEXT: 1 5 1.00 U fmul %st(2) +# CHECK-NEXT: 2 12 1.00 * U fmuls (%ecx) +# CHECK-NEXT: 2 12 1.00 * U fmull (%eax) +# CHECK-NEXT: 1 5 1.00 U fmulp %st(1) +# CHECK-NEXT: 1 5 1.00 U fmulp %st(2) +# CHECK-NEXT: 3 15 1.00 * U fimuls (%ecx) +# CHECK-NEXT: 3 15 1.00 * U fimull (%eax) +# CHECK-NEXT: 1 1 1.00 U fnop +# CHECK-NEXT: 1 100 0.33 U fpatan +# CHECK-NEXT: 1 100 0.33 U fprem +# CHECK-NEXT: 1 100 0.33 U fprem1 +# CHECK-NEXT: 1 100 0.33 U fptan +# CHECK-NEXT: 1 100 0.33 U frndint +# CHECK-NEXT: 1 100 0.33 U frstor (%eax) +# CHECK-NEXT: 1 100 0.33 U fnsave (%eax) +# CHECK-NEXT: 1 100 0.33 U fscale +# CHECK-NEXT: 1 100 0.33 U fsin +# CHECK-NEXT: 1 100 0.33 U fsincos +# CHECK-NEXT: 1 24 24.00 U fsqrt +# CHECK-NEXT: 1 1 1.00 U fst %st(0) +# CHECK-NEXT: 3 6 1.00 * U fsts (%edx) +# CHECK-NEXT: 3 6 1.00 * U fstl (%ecx) +# CHECK-NEXT: 1 1 1.00 U fstp %st(0) +# CHECK-NEXT: 3 6 1.00 * U fstpl (%edx) +# CHECK-NEXT: 3 6 1.00 * U fstpl (%ecx) +# CHECK-NEXT: 3 6 1.00 * U fstpt (%eax) +# CHECK-NEXT: 4 7 1.00 * U fnstcw (%eax) +# CHECK-NEXT: 1 100 0.33 U fnstenv (%eax) +# CHECK-NEXT: 4 7 1.00 U fnstsw (%eax) +# CHECK-NEXT: 1 100 0.33 U frstor (%eax) +# CHECK-NEXT: 1 100 0.33 U wait +# CHECK-NEXT: 1 100 0.33 U fnsave (%eax) +# CHECK-NEXT: 1 3 1.00 U fsub %st(0), %st(1) +# CHECK-NEXT: 1 3 1.00 U fsub %st(2) +# CHECK-NEXT: 2 10 1.00 * U fsubs (%ecx) +# CHECK-NEXT: 2 10 1.00 * U fsubl (%eax) +# CHECK-NEXT: 1 3 1.00 U fsubp %st(1) +# CHECK-NEXT: 1 3 1.00 U fsubp %st(2) +# CHECK-NEXT: 3 13 2.00 * U fisubs (%ecx) +# CHECK-NEXT: 3 13 2.00 * U fisubl (%eax) +# CHECK-NEXT: 1 3 1.00 U fsubr %st(0), %st(1) +# CHECK-NEXT: 1 3 1.00 U fsubr %st(2) +# CHECK-NEXT: 2 10 1.00 * U fsubrs (%ecx) +# CHECK-NEXT: 2 10 1.00 * U fsubrl (%eax) +# CHECK-NEXT: 1 3 1.00 U fsubrp %st(1) +# CHECK-NEXT: 1 3 1.00 U fsubrp %st(2) +# CHECK-NEXT: 3 13 2.00 * U fisubrs (%ecx) +# CHECK-NEXT: 3 13 2.00 * U fisubrl (%eax) +# CHECK-NEXT: 1 3 1.00 U ftst +# CHECK-NEXT: 1 1 1.00 U fucom %st(1) +# CHECK-NEXT: 1 1 1.00 U fucom %st(3) +# CHECK-NEXT: 1 1 1.00 U fucomp %st(1) +# CHECK-NEXT: 1 1 1.00 U fucomp %st(3) +# CHECK-NEXT: 1 3 1.00 U fucompp +# CHECK-NEXT: 3 3 1.00 U fucomi %st(3) +# CHECK-NEXT: 3 3 1.00 U fucompi %st(3) +# CHECK-NEXT: 1 100 0.33 U wait +# CHECK-NEXT: 1 100 0.33 U fxam +# CHECK-NEXT: 1 1 0.33 U fxch %st(1) +# CHECK-NEXT: 1 1 0.33 U fxch %st(3) +# CHECK-NEXT: 5 5 2.00 * * U fxrstor (%eax) +# CHECK-NEXT: 1 100 0.33 * * U fxsave (%eax) +# CHECK-NEXT: 1 100 0.33 U fxtract +# CHECK-NEXT: 1 100 0.33 U fyl2x +# CHECK-NEXT: 1 100 0.33 U fyl2xp1 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - 136.00 52.67 90.67 17.00 54.67 34.00 34.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - f2xm1 +# CHECK-NEXT: - - - - - 1.00 - - fabs +# CHECK-NEXT: - - - 1.00 - - - - fadd %st(0), %st(1) +# CHECK-NEXT: - - - 1.00 - - - - fadd %st(2) +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 fadds (%ecx) +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 faddl (%ecx) +# CHECK-NEXT: - - - 1.00 - - - - faddp %st(1) +# CHECK-NEXT: - - - 1.00 - - - - faddp %st(2) +# CHECK-NEXT: - - - 2.00 - - 0.50 0.50 fiadds (%ecx) +# CHECK-NEXT: - - - 2.00 - - 0.50 0.50 fiaddl (%ecx) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fbld (%ecx) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fbstp (%eax) +# CHECK-NEXT: - - - - - 1.00 - - fchs +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fnclex +# CHECK-NEXT: - - 0.50 - - 2.50 - - fcmovb %st(1), %st(0) +# CHECK-NEXT: - - 0.50 - - 2.50 - - fcmovbe %st(1), %st(0) +# CHECK-NEXT: - - 0.50 - - 2.50 - - fcmove %st(1), %st(0) +# CHECK-NEXT: - - 0.50 - - 2.50 - - fcmovnb %st(1), %st(0) +# CHECK-NEXT: - - 0.50 - - 2.50 - - fcmovnbe %st(1), %st(0) +# CHECK-NEXT: - - 0.50 - - 2.50 - - fcmovne %st(1), %st(0) +# CHECK-NEXT: - - 0.50 - - 2.50 - - fcmovnu %st(1), %st(0) +# CHECK-NEXT: - - 0.50 - - 2.50 - - fcmovu %st(1), %st(0) +# CHECK-NEXT: - - - 1.00 - - - - fcom %st(1) +# CHECK-NEXT: - - - 1.00 - - - - fcom %st(3) +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 fcoms (%ecx) +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 fcoml (%eax) +# CHECK-NEXT: - - - 1.00 - - - - fcomp %st(1) +# CHECK-NEXT: - - - 1.00 - - - - fcomp %st(3) +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 fcomps (%ecx) +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 fcompl (%eax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fcompp +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - fcomi %st(3) +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - fcompi %st(3) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fcos +# CHECK-NEXT: - - - - - 1.00 - - fdecstp +# CHECK-NEXT: - 14.00 1.00 - - - - - fdiv %st(0), %st(1) +# CHECK-NEXT: - 14.00 1.00 - - - - - fdiv %st(2) +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 fdivs (%ecx) +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 fdivl (%eax) +# CHECK-NEXT: - 14.00 1.00 - - - - - fdivp %st(1) +# CHECK-NEXT: - 14.00 1.00 - - - - - fdivp %st(2) +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 fidivs (%ecx) +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 fidivl (%eax) +# CHECK-NEXT: - 14.00 1.00 - - - - - fdivr %st(0), %st(1) +# CHECK-NEXT: - 14.00 1.00 - - - - - fdivr %st(2) +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 fdivrs (%ecx) +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 fdivrl (%eax) +# CHECK-NEXT: - 14.00 1.00 - - - - - fdivrp %st(1) +# CHECK-NEXT: - 14.00 1.00 - - - - - fdivrp %st(2) +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 fidivrs (%ecx) +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 fidivrl (%eax) +# CHECK-NEXT: - - - - - 1.00 - - ffree %st(0) +# CHECK-NEXT: - - - 2.00 - - 0.50 0.50 ficoms (%ecx) +# CHECK-NEXT: - - - 2.00 - - 0.50 0.50 ficoml (%eax) +# CHECK-NEXT: - - - 2.00 - - 0.50 0.50 ficomps (%ecx) +# CHECK-NEXT: - - - 2.00 - - 0.50 0.50 ficompl (%eax) +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 filds (%edx) +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 fildl (%ecx) +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 fildll (%eax) +# CHECK-NEXT: - - - - - 1.00 - - fincstp +# CHECK-NEXT: - - 1.00 1.00 - 2.00 - - fninit +# CHECK-NEXT: - - - 1.00 1.00 - 1.00 1.00 fists (%edx) +# CHECK-NEXT: - - - 1.00 1.00 - 1.00 1.00 fistl (%ecx) +# CHECK-NEXT: - - - 1.00 1.00 - 1.00 1.00 fistps (%edx) +# CHECK-NEXT: - - - 1.00 1.00 - 1.00 1.00 fistpl (%ecx) +# CHECK-NEXT: - - - 1.00 1.00 - 1.00 1.00 fistpll (%eax) +# CHECK-NEXT: - - - 1.00 1.00 - 0.50 0.50 fisttps (%edx) +# CHECK-NEXT: - - - 1.00 1.00 - 0.50 0.50 fisttpl (%ecx) +# CHECK-NEXT: - - - 1.00 1.00 - 0.50 0.50 fisttpll (%eax) +# CHECK-NEXT: - - - - - 1.00 - - fld %st(0) +# CHECK-NEXT: - - 0.50 0.50 - 1.00 0.50 0.50 flds (%edx) +# CHECK-NEXT: - - 0.50 0.50 - 1.00 0.50 0.50 fldl (%ecx) +# CHECK-NEXT: - - 0.50 0.50 - 1.00 0.50 0.50 fldt (%eax) +# CHECK-NEXT: - - - - 1.00 2.00 1.00 1.00 fldcw (%eax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fldenv (%eax) +# CHECK-NEXT: - - 1.00 - - 1.00 - - fld1 +# CHECK-NEXT: - - 1.00 1.00 - - - - fldl2e +# CHECK-NEXT: - - 1.00 1.00 - - - - fldl2t +# CHECK-NEXT: - - 1.00 1.00 - - - - fldlg2 +# CHECK-NEXT: - - 1.00 1.00 - - - - fldln2 +# CHECK-NEXT: - - 1.00 1.00 - - - - fldpi +# CHECK-NEXT: - - - - - 1.00 - - fldz +# CHECK-NEXT: - - 1.00 - - - - - fmul %st(0), %st(1) +# CHECK-NEXT: - - 1.00 - - - - - fmul %st(2) +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 fmuls (%ecx) +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 fmull (%eax) +# CHECK-NEXT: - - 1.00 - - - - - fmulp %st(1) +# CHECK-NEXT: - - 1.00 - - - - - fmulp %st(2) +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 fimuls (%ecx) +# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 fimull (%eax) +# CHECK-NEXT: - - - - - 1.00 - - fnop +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fpatan +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fprem +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fprem1 +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fptan +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - frndint +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - frstor (%eax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fnsave (%eax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fscale +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fsin +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fsincos +# CHECK-NEXT: - 24.00 1.00 - - - - - fsqrt +# CHECK-NEXT: - - - - - 1.00 - - fst %st(0) +# CHECK-NEXT: - - - - 1.00 - 1.00 1.00 fsts (%edx) +# CHECK-NEXT: - - - - 1.00 - 1.00 1.00 fstl (%ecx) +# CHECK-NEXT: - - - - - 1.00 - - fstp %st(0) +# CHECK-NEXT: - - - - 1.00 - 1.00 1.00 fstpl (%edx) +# CHECK-NEXT: - - - - 1.00 - 1.00 1.00 fstpl (%ecx) +# CHECK-NEXT: - - - - 1.00 - 1.00 1.00 fstpt (%eax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 1.00 fnstcw (%eax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fnstenv (%eax) +# CHECK-NEXT: - - 1.00 - 1.00 - 1.00 1.00 fnstsw (%eax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - frstor (%eax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - wait +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fnsave (%eax) +# CHECK-NEXT: - - - 1.00 - - - - fsub %st(0), %st(1) +# CHECK-NEXT: - - - 1.00 - - - - fsub %st(2) +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 fsubs (%ecx) +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 fsubl (%eax) +# CHECK-NEXT: - - - 1.00 - - - - fsubp %st(1) +# CHECK-NEXT: - - - 1.00 - - - - fsubp %st(2) +# CHECK-NEXT: - - - 2.00 - - 0.50 0.50 fisubs (%ecx) +# CHECK-NEXT: - - - 2.00 - - 0.50 0.50 fisubl (%eax) +# CHECK-NEXT: - - - 1.00 - - - - fsubr %st(0), %st(1) +# CHECK-NEXT: - - - 1.00 - - - - fsubr %st(2) +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 fsubrs (%ecx) +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 fsubrl (%eax) +# CHECK-NEXT: - - - 1.00 - - - - fsubrp %st(1) +# CHECK-NEXT: - - - 1.00 - - - - fsubrp %st(2) +# CHECK-NEXT: - - - 2.00 - - 0.50 0.50 fisubrs (%ecx) +# CHECK-NEXT: - - - 2.00 - - 0.50 0.50 fisubrl (%eax) +# CHECK-NEXT: - - - 1.00 - - - - ftst +# CHECK-NEXT: - - - 1.00 - - - - fucom %st(1) +# CHECK-NEXT: - - - 1.00 - - - - fucom %st(3) +# CHECK-NEXT: - - - 1.00 - - - - fucomp %st(1) +# CHECK-NEXT: - - - 1.00 - - - - fucomp %st(3) +# CHECK-NEXT: - - - 1.00 - - - - fucompp +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - fucomi %st(3) +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - fucompi %st(3) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - wait +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fxam +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fxch %st(1) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fxch %st(3) +# CHECK-NEXT: - - 0.50 0.50 1.00 2.00 0.50 0.50 fxrstor (%eax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fxsave (%eax) +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fxtract +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fyl2x +# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fyl2xp1 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/resources-xop.s b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-xop.s new file mode 100644 index 00000000000..61f39f07d78 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-xop.s @@ -0,0 +1,534 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s + +vfrczpd %xmm0, %xmm3 +vfrczpd (%rax), %xmm3 + +vfrczpd %ymm0, %ymm3 +vfrczpd (%rax), %ymm3 + +vfrczps %xmm0, %xmm3 +vfrczps (%rax), %xmm3 + +vfrczps %ymm0, %ymm3 +vfrczps (%rax), %ymm3 + +vfrczsd %xmm0, %xmm3 +vfrczsd (%rax), %xmm3 + +vfrczss %xmm0, %xmm3 +vfrczss (%rax), %xmm3 + +vpcmov %xmm0, %xmm1, %xmm2, %xmm3 +vpcmov (%rax), %xmm0, %xmm1, %xmm3 +vpcmov %xmm0, (%rax), %xmm1, %xmm3 + +vpcmov %ymm0, %ymm1, %ymm2, %ymm3 +vpcmov (%rax), %ymm0, %ymm1, %ymm3 +vpcmov %ymm0, (%rax), %ymm1, %ymm3 + +vpcomb $0, %xmm0, %xmm1, %xmm3 +vpcomb $0, (%rax), %xmm0, %xmm3 + +vpcomd $0, %xmm0, %xmm1, %xmm3 +vpcomd $0, (%rax), %xmm0, %xmm3 + +vpcomq $0, %xmm0, %xmm1, %xmm3 +vpcomq $0, (%rax), %xmm0, %xmm3 + +vpcomub $0, %xmm0, %xmm1, %xmm3 +vpcomub $0, (%rax), %xmm0, %xmm3 + +vpcomud $0, %xmm0, %xmm1, %xmm3 +vpcomud $0, (%rax), %xmm0, %xmm3 + +vpcomuq $0, %xmm0, %xmm1, %xmm3 +vpcomuq $0, (%rax), %xmm0, %xmm3 + +vpcomuw $0, %xmm0, %xmm1, %xmm3 +vpcomuw $0, (%rax), %xmm0, %xmm3 + +vpcomw $0, %xmm0, %xmm1, %xmm3 +vpcomw $0, (%rax), %xmm0, %xmm3 + +vpermil2pd $0, %xmm0, %xmm1, %xmm2, %xmm3 +vpermil2pd $0, (%rax), %xmm0, %xmm1, %xmm3 +vpermil2pd $0, %xmm0, (%rax), %xmm1, %xmm3 + +vpermil2pd $0, %ymm0, %ymm1, %ymm2, %ymm3 +vpermil2pd $0, (%rax), %ymm0, %ymm1, %ymm3 +vpermil2pd $0, %ymm0, (%rax), %ymm1, %ymm3 + +vpermil2ps $0, %xmm0, %xmm1, %xmm2, %xmm3 +vpermil2ps $0, (%rax), %xmm0, %xmm1, %xmm3 +vpermil2ps $0, %xmm0, (%rax), %xmm1, %xmm3 + +vpermil2ps $0, %ymm0, %ymm1, %ymm2, %ymm3 +vpermil2ps $0, (%rax), %ymm0, %ymm1, %ymm3 +vpermil2ps $0, %ymm0, (%rax), %ymm1, %ymm3 + +vphaddbd %xmm0, %xmm3 +vphaddbd (%rax), %xmm3 + +vphaddbq %xmm0, %xmm3 +vphaddbq (%rax), %xmm3 + +vphaddbw %xmm0, %xmm3 +vphaddbw (%rax), %xmm3 + +vphadddq %xmm0, %xmm3 +vphadddq (%rax), %xmm3 + +vphaddubd %xmm0, %xmm3 +vphaddubd (%rax), %xmm3 + +vphaddubq %xmm0, %xmm3 +vphaddubq (%rax), %xmm3 + +vphaddubw %xmm0, %xmm3 +vphaddubw (%rax), %xmm3 + +vphaddudq %xmm0, %xmm3 +vphaddudq (%rax), %xmm3 + +vphadduwd %xmm0, %xmm3 +vphadduwd (%rax), %xmm3 + +vphadduwq %xmm0, %xmm3 +vphadduwq (%rax), %xmm3 + +vphaddwd %xmm0, %xmm3 +vphaddwd (%rax), %xmm3 + +vphaddwq %xmm0, %xmm3 +vphaddwq (%rax), %xmm3 + +vphsubbw %xmm0, %xmm3 +vphsubbw (%rax), %xmm3 + +vphsubdq %xmm0, %xmm3 +vphsubdq (%rax), %xmm3 + +vphsubwd %xmm0, %xmm3 +vphsubwd (%rax), %xmm3 + +vpmacsdd %xmm0, %xmm1, %xmm2, %xmm3 +vpmacsdd %xmm0, (%rax), %xmm1, %xmm3 + +vpmacsdqh %xmm0, %xmm1, %xmm2, %xmm3 +vpmacsdqh %xmm0, (%rax), %xmm1, %xmm3 + +vpmacsdql %xmm0, %xmm1, %xmm2, %xmm3 +vpmacsdql %xmm0, (%rax), %xmm1, %xmm3 + +vpmacssdd %xmm0, %xmm1, %xmm2, %xmm3 +vpmacssdd %xmm0, (%rax), %xmm1, %xmm3 + +vpmacssdqh %xmm0, %xmm1, %xmm2, %xmm3 +vpmacssdqh %xmm0, (%rax), %xmm1, %xmm3 + +vpmacssdql %xmm0, %xmm1, %xmm2, %xmm3 +vpmacssdql %xmm0, (%rax), %xmm1, %xmm3 + +vpmacsswd %xmm0, %xmm1, %xmm2, %xmm3 +vpmacsswd %xmm0, (%rax), %xmm1, %xmm3 + +vpmacssww %xmm0, %xmm1, %xmm2, %xmm3 +vpmacssww %xmm0, (%rax), %xmm1, %xmm3 + +vpmacswd %xmm0, %xmm1, %xmm2, %xmm3 +vpmacswd %xmm0, (%rax), %xmm1, %xmm3 + +vpmacsww %xmm0, %xmm1, %xmm2, %xmm3 +vpmacsww %xmm0, (%rax), %xmm1, %xmm3 + +vpmadcsswd %xmm0, %xmm1, %xmm2, %xmm3 +vpmadcsswd %xmm0, (%rax), %xmm1, %xmm3 + +vpmadcswd %xmm0, %xmm1, %xmm2, %xmm3 +vpmadcswd %xmm0, (%rax), %xmm1, %xmm3 + +vpperm %xmm0, %xmm1, %xmm2, %xmm3 +vpperm (%rax), %xmm0, %xmm1, %xmm3 +vpperm %xmm0, (%rax), %xmm1, %xmm3 + +vprotb %xmm0, %xmm1, %xmm3 +vprotb (%rax), %xmm0, %xmm3 +vprotb %xmm0, (%rax), %xmm3 + +vprotb $0, %xmm0, %xmm3 +vprotb $0, (%rax), %xmm3 + +vprotd %xmm0, %xmm1, %xmm3 +vprotd (%rax), %xmm0, %xmm3 +vprotd %xmm0, (%rax), %xmm3 + +vprotd $0, %xmm0, %xmm3 +vprotd $0, (%rax), %xmm3 + +vprotq %xmm0, %xmm1, %xmm3 +vprotq (%rax), %xmm0, %xmm3 +vprotq %xmm0, (%rax), %xmm3 + +vprotq $0, %xmm0, %xmm3 +vprotq $0, (%rax), %xmm3 + +vprotw %xmm0, %xmm1, %xmm3 +vprotw (%rax), %xmm0, %xmm3 +vprotw %xmm0, (%rax), %xmm3 + +vprotw $0, %xmm0, %xmm3 +vprotw $0, (%rax), %xmm3 + +vpshab %xmm0, %xmm1, %xmm3 +vpshab (%rax), %xmm0, %xmm3 +vpshab %xmm0, (%rax), %xmm3 + +vpshad %xmm0, %xmm1, %xmm3 +vpshad (%rax), %xmm0, %xmm3 +vpshad %xmm0, (%rax), %xmm3 + +vpshaq %xmm0, %xmm1, %xmm3 +vpshaq (%rax), %xmm0, %xmm3 +vpshaq %xmm0, (%rax), %xmm3 + +vpshaw %xmm0, %xmm1, %xmm3 +vpshaw (%rax), %xmm0, %xmm3 +vpshaw %xmm0, (%rax), %xmm3 + +vpshlb %xmm0, %xmm1, %xmm3 +vpshlb (%rax), %xmm0, %xmm3 +vpshlb %xmm0, (%rax), %xmm3 + +vpshld %xmm0, %xmm1, %xmm3 +vpshld (%rax), %xmm0, %xmm3 +vpshld %xmm0, (%rax), %xmm3 + +vpshlq %xmm0, %xmm1, %xmm3 +vpshlq (%rax), %xmm0, %xmm3 +vpshlq %xmm0, (%rax), %xmm3 + +vpshlw %xmm0, %xmm1, %xmm3 +vpshlw (%rax), %xmm0, %xmm3 +vpshlw %xmm0, (%rax), %xmm3 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 vfrczpd %xmm0, %xmm3 +# CHECK-NEXT: 2 9 1.00 * vfrczpd (%rax), %xmm3 +# CHECK-NEXT: 1 3 1.00 vfrczpd %ymm0, %ymm3 +# CHECK-NEXT: 2 10 1.00 * vfrczpd (%rax), %ymm3 +# CHECK-NEXT: 1 3 1.00 vfrczps %xmm0, %xmm3 +# CHECK-NEXT: 2 9 1.00 * vfrczps (%rax), %xmm3 +# CHECK-NEXT: 1 3 1.00 vfrczps %ymm0, %ymm3 +# CHECK-NEXT: 2 10 1.00 * vfrczps (%rax), %ymm3 +# CHECK-NEXT: 1 3 1.00 vfrczsd %xmm0, %xmm3 +# CHECK-NEXT: 2 9 1.00 * vfrczsd (%rax), %xmm3 +# CHECK-NEXT: 1 3 1.00 vfrczss %xmm0, %xmm3 +# CHECK-NEXT: 2 9 1.00 * vfrczss (%rax), %xmm3 +# CHECK-NEXT: 1 1 0.50 vpcmov %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 7 0.50 * vpcmov (%rax), %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: 2 7 0.50 * vpcmov %xmm0, (%rax), %xmm1, %xmm3 +# CHECK-NEXT: 1 1 1.00 vpcmov %ymm0, %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: 2 8 1.00 * vpcmov (%rax), %ymm0, %ymm1, %ymm3 +# CHECK-NEXT: 2 8 1.00 * vpcmov %ymm0, (%rax), %ymm1, %ymm3 +# CHECK-NEXT: 1 1 0.50 vpcomb $0, %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: 2 7 0.50 * vpcomb $0, (%rax), %xmm0, %xmm3 +# CHECK-NEXT: 1 1 0.50 vpcomd $0, %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: 2 7 0.50 * vpcomd $0, (%rax), %xmm0, %xmm3 +# CHECK-NEXT: 1 1 0.50 vpcomq $0, %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: 2 7 0.50 * vpcomq $0, (%rax), %xmm0, %xmm3 +# CHECK-NEXT: 1 1 0.50 vpcomub $0, %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: 2 7 0.50 * vpcomub $0, (%rax), %xmm0, %xmm3 +# CHECK-NEXT: 1 1 0.50 vpcomud $0, %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: 2 7 0.50 * vpcomud $0, (%rax), %xmm0, %xmm3 +# CHECK-NEXT: 1 1 0.50 vpcomuq $0, %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: 2 7 0.50 * vpcomuq $0, (%rax), %xmm0, %xmm3 +# CHECK-NEXT: 1 1 0.50 vpcomuw $0, %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: 2 7 0.50 * vpcomuw $0, (%rax), %xmm0, %xmm3 +# CHECK-NEXT: 1 1 0.50 vpcomw $0, %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: 2 7 0.50 * vpcomw $0, (%rax), %xmm0, %xmm3 +# CHECK-NEXT: 1 1 1.00 vpermil2pd $0, %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 7 1.00 * vpermil2pd $0, (%rax), %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: 2 7 1.00 * vpermil2pd $0, %xmm0, (%rax), %xmm1, %xmm3 +# CHECK-NEXT: 1 1 1.00 vpermil2pd $0, %ymm0, %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: 2 8 1.00 * vpermil2pd $0, (%rax), %ymm0, %ymm1, %ymm3 +# CHECK-NEXT: 2 8 1.00 * vpermil2pd $0, %ymm0, (%rax), %ymm1, %ymm3 +# CHECK-NEXT: 1 1 1.00 vpermil2ps $0, %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 7 1.00 * vpermil2ps $0, (%rax), %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: 2 7 1.00 * vpermil2ps $0, %xmm0, (%rax), %xmm1, %xmm3 +# CHECK-NEXT: 1 1 1.00 vpermil2ps $0, %ymm0, %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: 2 8 1.00 * vpermil2ps $0, (%rax), %ymm0, %ymm1, %ymm3 +# CHECK-NEXT: 2 8 1.00 * vpermil2ps $0, %ymm0, (%rax), %ymm1, %ymm3 +# CHECK-NEXT: 3 3 1.50 vphaddbd %xmm0, %xmm3 +# CHECK-NEXT: 4 9 1.50 * vphaddbd (%rax), %xmm3 +# CHECK-NEXT: 3 3 1.50 vphaddbq %xmm0, %xmm3 +# CHECK-NEXT: 4 9 1.50 * vphaddbq (%rax), %xmm3 +# CHECK-NEXT: 3 3 1.50 vphaddbw %xmm0, %xmm3 +# CHECK-NEXT: 4 9 1.50 * vphaddbw (%rax), %xmm3 +# CHECK-NEXT: 3 3 1.50 vphadddq %xmm0, %xmm3 +# CHECK-NEXT: 4 9 1.50 * vphadddq (%rax), %xmm3 +# CHECK-NEXT: 3 3 1.50 vphaddubd %xmm0, %xmm3 +# CHECK-NEXT: 4 9 1.50 * vphaddubd (%rax), %xmm3 +# CHECK-NEXT: 3 3 1.50 vphaddubq %xmm0, %xmm3 +# CHECK-NEXT: 4 9 1.50 * vphaddubq (%rax), %xmm3 +# CHECK-NEXT: 3 3 1.50 vphaddubw %xmm0, %xmm3 +# CHECK-NEXT: 4 9 1.50 * vphaddubw (%rax), %xmm3 +# CHECK-NEXT: 3 3 1.50 vphaddudq %xmm0, %xmm3 +# CHECK-NEXT: 4 9 1.50 * vphaddudq (%rax), %xmm3 +# CHECK-NEXT: 3 3 1.50 vphadduwd %xmm0, %xmm3 +# CHECK-NEXT: 4 9 1.50 * vphadduwd (%rax), %xmm3 +# CHECK-NEXT: 3 3 1.50 vphadduwq %xmm0, %xmm3 +# CHECK-NEXT: 4 9 1.50 * vphadduwq (%rax), %xmm3 +# CHECK-NEXT: 3 3 1.50 vphaddwd %xmm0, %xmm3 +# CHECK-NEXT: 4 9 1.50 * vphaddwd (%rax), %xmm3 +# CHECK-NEXT: 3 3 1.50 vphaddwq %xmm0, %xmm3 +# CHECK-NEXT: 4 9 1.50 * vphaddwq (%rax), %xmm3 +# CHECK-NEXT: 3 3 1.50 vphsubbw %xmm0, %xmm3 +# CHECK-NEXT: 4 9 1.50 * vphsubbw (%rax), %xmm3 +# CHECK-NEXT: 3 3 1.50 vphsubdq %xmm0, %xmm3 +# CHECK-NEXT: 4 9 1.50 * vphsubdq (%rax), %xmm3 +# CHECK-NEXT: 3 3 1.50 vphsubwd %xmm0, %xmm3 +# CHECK-NEXT: 4 9 1.50 * vphsubwd (%rax), %xmm3 +# CHECK-NEXT: 1 5 1.00 vpmacsdd %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 11 1.00 * vpmacsdd %xmm0, (%rax), %xmm1, %xmm3 +# CHECK-NEXT: 1 5 1.00 vpmacsdqh %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 11 1.00 * vpmacsdqh %xmm0, (%rax), %xmm1, %xmm3 +# CHECK-NEXT: 1 5 1.00 vpmacsdql %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 11 1.00 * vpmacsdql %xmm0, (%rax), %xmm1, %xmm3 +# CHECK-NEXT: 1 5 1.00 vpmacssdd %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 11 1.00 * vpmacssdd %xmm0, (%rax), %xmm1, %xmm3 +# CHECK-NEXT: 1 5 1.00 vpmacssdqh %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 11 1.00 * vpmacssdqh %xmm0, (%rax), %xmm1, %xmm3 +# CHECK-NEXT: 1 5 1.00 vpmacssdql %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 11 1.00 * vpmacssdql %xmm0, (%rax), %xmm1, %xmm3 +# CHECK-NEXT: 1 5 1.00 vpmacsswd %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 11 1.00 * vpmacsswd %xmm0, (%rax), %xmm1, %xmm3 +# CHECK-NEXT: 1 5 1.00 vpmacssww %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 11 1.00 * vpmacssww %xmm0, (%rax), %xmm1, %xmm3 +# CHECK-NEXT: 1 5 1.00 vpmacswd %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 11 1.00 * vpmacswd %xmm0, (%rax), %xmm1, %xmm3 +# CHECK-NEXT: 1 5 1.00 vpmacsww %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 11 1.00 * vpmacsww %xmm0, (%rax), %xmm1, %xmm3 +# CHECK-NEXT: 1 5 1.00 vpmadcsswd %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 11 1.00 * vpmadcsswd %xmm0, (%rax), %xmm1, %xmm3 +# CHECK-NEXT: 1 5 1.00 vpmadcswd %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 11 1.00 * vpmadcswd %xmm0, (%rax), %xmm1, %xmm3 +# CHECK-NEXT: 1 1 0.50 vpperm %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: 2 7 0.50 * vpperm (%rax), %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: 2 7 0.50 * vpperm %xmm0, (%rax), %xmm1, %xmm3 +# CHECK-NEXT: 1 1 1.00 vprotb %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: 2 7 1.00 * vprotb (%rax), %xmm0, %xmm3 +# CHECK-NEXT: 2 7 1.00 * vprotb %xmm0, (%rax), %xmm3 +# CHECK-NEXT: 1 1 1.00 vprotb $0, %xmm0, %xmm3 +# CHECK-NEXT: 2 7 1.00 * vprotb $0, (%rax), %xmm3 +# CHECK-NEXT: 1 1 1.00 vprotd %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: 2 7 1.00 * vprotd (%rax), %xmm0, %xmm3 +# CHECK-NEXT: 2 7 1.00 * vprotd %xmm0, (%rax), %xmm3 +# CHECK-NEXT: 1 1 1.00 vprotd $0, %xmm0, %xmm3 +# CHECK-NEXT: 2 7 1.00 * vprotd $0, (%rax), %xmm3 +# CHECK-NEXT: 1 1 1.00 vprotq %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: 2 7 1.00 * vprotq (%rax), %xmm0, %xmm3 +# CHECK-NEXT: 2 7 1.00 * vprotq %xmm0, (%rax), %xmm3 +# CHECK-NEXT: 1 1 1.00 vprotq $0, %xmm0, %xmm3 +# CHECK-NEXT: 2 7 1.00 * vprotq $0, (%rax), %xmm3 +# CHECK-NEXT: 1 1 1.00 vprotw %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: 2 7 1.00 * vprotw (%rax), %xmm0, %xmm3 +# CHECK-NEXT: 2 7 1.00 * vprotw %xmm0, (%rax), %xmm3 +# CHECK-NEXT: 1 1 1.00 vprotw $0, %xmm0, %xmm3 +# CHECK-NEXT: 2 7 1.00 * vprotw $0, (%rax), %xmm3 +# CHECK-NEXT: 1 1 1.00 vpshab %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: 2 7 1.00 * vpshab (%rax), %xmm0, %xmm3 +# CHECK-NEXT: 2 7 1.00 * vpshab %xmm0, (%rax), %xmm3 +# CHECK-NEXT: 1 1 1.00 vpshad %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: 2 7 1.00 * vpshad (%rax), %xmm0, %xmm3 +# CHECK-NEXT: 2 7 1.00 * vpshad %xmm0, (%rax), %xmm3 +# CHECK-NEXT: 1 1 1.00 vpshaq %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: 2 7 1.00 * vpshaq (%rax), %xmm0, %xmm3 +# CHECK-NEXT: 2 7 1.00 * vpshaq %xmm0, (%rax), %xmm3 +# CHECK-NEXT: 1 1 1.00 vpshaw %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: 2 7 1.00 * vpshaw (%rax), %xmm0, %xmm3 +# CHECK-NEXT: 2 7 1.00 * vpshaw %xmm0, (%rax), %xmm3 +# CHECK-NEXT: 1 1 1.00 vpshlb %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: 2 7 1.00 * vpshlb (%rax), %xmm0, %xmm3 +# CHECK-NEXT: 2 7 1.00 * vpshlb %xmm0, (%rax), %xmm3 +# CHECK-NEXT: 1 1 1.00 vpshld %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: 2 7 1.00 * vpshld (%rax), %xmm0, %xmm3 +# CHECK-NEXT: 2 7 1.00 * vpshld %xmm0, (%rax), %xmm3 +# CHECK-NEXT: 1 1 1.00 vpshlq %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: 2 7 1.00 * vpshlq (%rax), %xmm0, %xmm3 +# CHECK-NEXT: 2 7 1.00 * vpshlq %xmm0, (%rax), %xmm3 +# CHECK-NEXT: 1 1 1.00 vpshlw %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: 2 7 1.00 * vpshlw (%rax), %xmm0, %xmm3 +# CHECK-NEXT: 2 7 1.00 * vpshlw %xmm0, (%rax), %xmm3 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 68.00 68.00 - 71.00 41.50 41.50 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - - - - vfrczpd %xmm0, %xmm3 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vfrczpd (%rax), %xmm3 +# CHECK-NEXT: - - - 1.00 - - - - vfrczpd %ymm0, %ymm3 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vfrczpd (%rax), %ymm3 +# CHECK-NEXT: - - - 1.00 - - - - vfrczps %xmm0, %xmm3 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vfrczps (%rax), %xmm3 +# CHECK-NEXT: - - - 1.00 - - - - vfrczps %ymm0, %ymm3 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vfrczps (%rax), %ymm3 +# CHECK-NEXT: - - - 1.00 - - - - vfrczsd %xmm0, %xmm3 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vfrczsd (%rax), %xmm3 +# CHECK-NEXT: - - - 1.00 - - - - vfrczss %xmm0, %xmm3 +# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vfrczss (%rax), %xmm3 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpcmov %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpcmov (%rax), %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpcmov %xmm0, (%rax), %xmm1, %xmm3 +# CHECK-NEXT: - - - - - 1.00 - - vpcmov %ymm0, %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vpcmov (%rax), %ymm0, %ymm1, %ymm3 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vpcmov %ymm0, (%rax), %ymm1, %ymm3 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpcomb $0, %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpcomb $0, (%rax), %xmm0, %xmm3 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpcomd $0, %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpcomd $0, (%rax), %xmm0, %xmm3 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpcomq $0, %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpcomq $0, (%rax), %xmm0, %xmm3 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpcomub $0, %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpcomub $0, (%rax), %xmm0, %xmm3 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpcomud $0, %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpcomud $0, (%rax), %xmm0, %xmm3 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpcomuq $0, %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpcomuq $0, (%rax), %xmm0, %xmm3 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpcomuw $0, %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpcomuw $0, (%rax), %xmm0, %xmm3 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpcomw $0, %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpcomw $0, (%rax), %xmm0, %xmm3 +# CHECK-NEXT: - - - - - 1.00 - - vpermil2pd $0, %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vpermil2pd $0, (%rax), %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vpermil2pd $0, %xmm0, (%rax), %xmm1, %xmm3 +# CHECK-NEXT: - - - - - 1.00 - - vpermil2pd $0, %ymm0, %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vpermil2pd $0, (%rax), %ymm0, %ymm1, %ymm3 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vpermil2pd $0, %ymm0, (%rax), %ymm1, %ymm3 +# CHECK-NEXT: - - - - - 1.00 - - vpermil2ps $0, %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vpermil2ps $0, (%rax), %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vpermil2ps $0, %xmm0, (%rax), %xmm1, %xmm3 +# CHECK-NEXT: - - - - - 1.00 - - vpermil2ps $0, %ymm0, %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vpermil2ps $0, (%rax), %ymm0, %ymm1, %ymm3 +# CHECK-NEXT: - - - - - 1.00 0.50 0.50 vpermil2ps $0, %ymm0, (%rax), %ymm1, %ymm3 +# CHECK-NEXT: - - - 1.50 - 1.50 - - vphaddbd %xmm0, %xmm3 +# CHECK-NEXT: - - - 1.50 - 1.50 0.50 0.50 vphaddbd (%rax), %xmm3 +# CHECK-NEXT: - - - 1.50 - 1.50 - - vphaddbq %xmm0, %xmm3 +# CHECK-NEXT: - - - 1.50 - 1.50 0.50 0.50 vphaddbq (%rax), %xmm3 +# CHECK-NEXT: - - - 1.50 - 1.50 - - vphaddbw %xmm0, %xmm3 +# CHECK-NEXT: - - - 1.50 - 1.50 0.50 0.50 vphaddbw (%rax), %xmm3 +# CHECK-NEXT: - - - 1.50 - 1.50 - - vphadddq %xmm0, %xmm3 +# CHECK-NEXT: - - - 1.50 - 1.50 0.50 0.50 vphadddq (%rax), %xmm3 +# CHECK-NEXT: - - - 1.50 - 1.50 - - vphaddubd %xmm0, %xmm3 +# CHECK-NEXT: - - - 1.50 - 1.50 0.50 0.50 vphaddubd (%rax), %xmm3 +# CHECK-NEXT: - - - 1.50 - 1.50 - - vphaddubq %xmm0, %xmm3 +# CHECK-NEXT: - - - 1.50 - 1.50 0.50 0.50 vphaddubq (%rax), %xmm3 +# CHECK-NEXT: - - - 1.50 - 1.50 - - vphaddubw %xmm0, %xmm3 +# CHECK-NEXT: - - - 1.50 - 1.50 0.50 0.50 vphaddubw (%rax), %xmm3 +# CHECK-NEXT: - - - 1.50 - 1.50 - - vphaddudq %xmm0, %xmm3 +# CHECK-NEXT: - - - 1.50 - 1.50 0.50 0.50 vphaddudq (%rax), %xmm3 +# CHECK-NEXT: - - - 1.50 - 1.50 - - vphadduwd %xmm0, %xmm3 +# CHECK-NEXT: - - - 1.50 - 1.50 0.50 0.50 vphadduwd (%rax), %xmm3 +# CHECK-NEXT: - - - 1.50 - 1.50 - - vphadduwq %xmm0, %xmm3 +# CHECK-NEXT: - - - 1.50 - 1.50 0.50 0.50 vphadduwq (%rax), %xmm3 +# CHECK-NEXT: - - - 1.50 - 1.50 - - vphaddwd %xmm0, %xmm3 +# CHECK-NEXT: - - - 1.50 - 1.50 0.50 0.50 vphaddwd (%rax), %xmm3 +# CHECK-NEXT: - - - 1.50 - 1.50 - - vphaddwq %xmm0, %xmm3 +# CHECK-NEXT: - - - 1.50 - 1.50 0.50 0.50 vphaddwq (%rax), %xmm3 +# CHECK-NEXT: - - - 1.50 - 1.50 - - vphsubbw %xmm0, %xmm3 +# CHECK-NEXT: - - - 1.50 - 1.50 0.50 0.50 vphsubbw (%rax), %xmm3 +# CHECK-NEXT: - - - 1.50 - 1.50 - - vphsubdq %xmm0, %xmm3 +# CHECK-NEXT: - - - 1.50 - 1.50 0.50 0.50 vphsubdq (%rax), %xmm3 +# CHECK-NEXT: - - - 1.50 - 1.50 - - vphsubwd %xmm0, %xmm3 +# CHECK-NEXT: - - - 1.50 - 1.50 0.50 0.50 vphsubwd (%rax), %xmm3 +# CHECK-NEXT: - - 1.00 - - - - - vpmacsdd %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpmacsdd %xmm0, (%rax), %xmm1, %xmm3 +# CHECK-NEXT: - - 1.00 - - - - - vpmacsdqh %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpmacsdqh %xmm0, (%rax), %xmm1, %xmm3 +# CHECK-NEXT: - - 1.00 - - - - - vpmacsdql %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpmacsdql %xmm0, (%rax), %xmm1, %xmm3 +# CHECK-NEXT: - - 1.00 - - - - - vpmacssdd %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpmacssdd %xmm0, (%rax), %xmm1, %xmm3 +# CHECK-NEXT: - - 1.00 - - - - - vpmacssdqh %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpmacssdqh %xmm0, (%rax), %xmm1, %xmm3 +# CHECK-NEXT: - - 1.00 - - - - - vpmacssdql %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpmacssdql %xmm0, (%rax), %xmm1, %xmm3 +# CHECK-NEXT: - - 1.00 - - - - - vpmacsswd %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpmacsswd %xmm0, (%rax), %xmm1, %xmm3 +# CHECK-NEXT: - - 1.00 - - - - - vpmacssww %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpmacssww %xmm0, (%rax), %xmm1, %xmm3 +# CHECK-NEXT: - - 1.00 - - - - - vpmacswd %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpmacswd %xmm0, (%rax), %xmm1, %xmm3 +# CHECK-NEXT: - - 1.00 - - - - - vpmacsww %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpmacsww %xmm0, (%rax), %xmm1, %xmm3 +# CHECK-NEXT: - - 1.00 - - - - - vpmadcsswd %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpmadcsswd %xmm0, (%rax), %xmm1, %xmm3 +# CHECK-NEXT: - - 1.00 - - - - - vpmadcswd %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpmadcswd %xmm0, (%rax), %xmm1, %xmm3 +# CHECK-NEXT: - - - 0.50 - 0.50 - - vpperm %xmm0, %xmm1, %xmm2, %xmm3 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpperm (%rax), %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 vpperm %xmm0, (%rax), %xmm1, %xmm3 +# CHECK-NEXT: - - 1.00 - - - - - vprotb %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vprotb (%rax), %xmm0, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vprotb %xmm0, (%rax), %xmm3 +# CHECK-NEXT: - - 1.00 - - - - - vprotb $0, %xmm0, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vprotb $0, (%rax), %xmm3 +# CHECK-NEXT: - - 1.00 - - - - - vprotd %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vprotd (%rax), %xmm0, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vprotd %xmm0, (%rax), %xmm3 +# CHECK-NEXT: - - 1.00 - - - - - vprotd $0, %xmm0, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vprotd $0, (%rax), %xmm3 +# CHECK-NEXT: - - 1.00 - - - - - vprotq %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vprotq (%rax), %xmm0, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vprotq %xmm0, (%rax), %xmm3 +# CHECK-NEXT: - - 1.00 - - - - - vprotq $0, %xmm0, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vprotq $0, (%rax), %xmm3 +# CHECK-NEXT: - - 1.00 - - - - - vprotw %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vprotw (%rax), %xmm0, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vprotw %xmm0, (%rax), %xmm3 +# CHECK-NEXT: - - 1.00 - - - - - vprotw $0, %xmm0, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vprotw $0, (%rax), %xmm3 +# CHECK-NEXT: - - 1.00 - - - - - vpshab %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpshab (%rax), %xmm0, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpshab %xmm0, (%rax), %xmm3 +# CHECK-NEXT: - - 1.00 - - - - - vpshad %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpshad (%rax), %xmm0, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpshad %xmm0, (%rax), %xmm3 +# CHECK-NEXT: - - 1.00 - - - - - vpshaq %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpshaq (%rax), %xmm0, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpshaq %xmm0, (%rax), %xmm3 +# CHECK-NEXT: - - 1.00 - - - - - vpshaw %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpshaw (%rax), %xmm0, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpshaw %xmm0, (%rax), %xmm3 +# CHECK-NEXT: - - 1.00 - - - - - vpshlb %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpshlb (%rax), %xmm0, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpshlb %xmm0, (%rax), %xmm3 +# CHECK-NEXT: - - 1.00 - - - - - vpshld %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpshld (%rax), %xmm0, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpshld %xmm0, (%rax), %xmm3 +# CHECK-NEXT: - - 1.00 - - - - - vpshlq %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpshlq (%rax), %xmm0, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpshlq %xmm0, (%rax), %xmm3 +# CHECK-NEXT: - - 1.00 - - - - - vpshlw %xmm0, %xmm1, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpshlw (%rax), %xmm0, %xmm3 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpshlw %xmm0, (%rax), %xmm3 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/scheduler-queue-usage.s b/llvm/test/tools/llvm-mca/X86/BdVer2/scheduler-queue-usage.s new file mode 100644 index 00000000000..b2a8f4ac33e --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/scheduler-queue-usage.s @@ -0,0 +1,60 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -scheduler-stats < %s | FileCheck %s + +vmulps (%rsi), %xmm0, %xmm0 +add %rsi, %rsi + +# CHECK: Iterations: 1 +# CHECK-NEXT: Instructions: 2 +# CHECK-NEXT: Total Cycles: 14 +# CHECK-NEXT: Total uOps: 3 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.21 +# CHECK-NEXT: IPC: 0.14 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 2 11 1.00 * vmulps (%rsi), %xmm0, %xmm0 +# CHECK-NEXT: 1 1 0.33 addq %rsi, %rsi + +# CHECK: Schedulers - number of cycles where we saw N instructions issued: +# CHECK-NEXT: [# issued], [# cycles] +# CHECK-NEXT: 0, 13 (92.9%) +# CHECK-NEXT: 2, 1 (7.1%) + +# CHECK: Scheduler's queue usage: +# CHECK-NEXT: [1] Resource name. +# CHECK-NEXT: [2] Average number of used buffer entries. +# CHECK-NEXT: [3] Maximum number of used buffer entries. +# CHECK-NEXT: [4] Total number of buffer entries. + +# CHECK: [1] [2] [3] [4] +# CHECK-NEXT: SBPortAny 0 2 54 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 1.00 - - 1.00 - 1.00 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 1.00 - - - - 1.00 vmulps (%rsi), %xmm0, %xmm0 +# CHECK-NEXT: - - - - - 1.00 - - addq %rsi, %rsi diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/simple-test.s b/llvm/test/tools/llvm-mca/X86/BdVer2/simple-test.s new file mode 100644 index 00000000000..f0ff718c9e7 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/simple-test.s @@ -0,0 +1,43 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=100 < %s | FileCheck %s + +add %edi, %eax + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 100 +# CHECK-NEXT: Total Cycles: 103 +# CHECK-NEXT: Total uOps: 100 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.97 +# CHECK-NEXT: IPC: 0.97 +# CHECK-NEXT: Block RThroughput: 0.3 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 0.33 addl %edi, %eax + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 0.33 0.33 - 0.34 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 0.33 0.33 - 0.34 - - addl %edi, %eax diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/vbroadcast-operand-latency.s b/llvm/test/tools/llvm-mca/X86/BdVer2/vbroadcast-operand-latency.s new file mode 100644 index 00000000000..ee54b757da2 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/vbroadcast-operand-latency.s @@ -0,0 +1,67 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -timeline -timeline-max-iterations=3 < %s | FileCheck %s + +leaq 8(%rsp, %rdi, 2), %rax +vbroadcastss (%rax), %ymm0 + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 200 +# CHECK-NEXT: Total Cycles: 60 +# CHECK-NEXT: Total uOps: 200 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 3.33 +# CHECK-NEXT: IPC: 3.33 +# CHECK-NEXT: Block RThroughput: 0.5 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 0.50 leaq 8(%rsp,%rdi,2), %rax +# CHECK-NEXT: 1 7 0.50 * vbroadcastss (%rax), %ymm0 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 0.50 0.50 - - 0.50 0.50 + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 8(%rsp,%rdi,2), %rax +# CHECK-NEXT: - - - - - - 0.50 0.50 vbroadcastss (%rax), %ymm0 + +# CHECK: Timeline view: +# CHECK-NEXT: 01 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeER . .. leaq 8(%rsp,%rdi,2), %rax +# CHECK-NEXT: [0,1] D=eeeeeeeER. vbroadcastss (%rax), %ymm0 +# CHECK-NEXT: [1,0] DeE-------R. leaq 8(%rsp,%rdi,2), %rax +# CHECK-NEXT: [1,1] D=eeeeeeeER. vbroadcastss (%rax), %ymm0 +# CHECK-NEXT: [2,0] .DeE------R. leaq 8(%rsp,%rdi,2), %rax +# CHECK-NEXT: [2,1] .D=eeeeeeeER vbroadcastss (%rax), %ymm0 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 1.0 1.0 4.3 leaq 8(%rsp,%rdi,2), %rax +# CHECK-NEXT: 1. 3 2.0 0.0 0.0 vbroadcastss (%rax), %ymm0 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/vec-logic-read-after-ld-1.s b/llvm/test/tools/llvm-mca/X86/BdVer2/vec-logic-read-after-ld-1.s new file mode 100644 index 00000000000..721d276f2f4 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/vec-logic-read-after-ld-1.s @@ -0,0 +1,43 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -timeline -resource-pressure=false < %s | FileCheck %s + +vaddps %xmm0, %xmm0, %xmm1 +vandps (%rdi), %xmm1, %xmm2 + +# CHECK: Iterations: 1 +# CHECK-NEXT: Instructions: 2 +# CHECK-NEXT: Total Cycles: 10 +# CHECK-NEXT: Total uOps: 3 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.30 +# CHECK-NEXT: IPC: 0.20 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 vaddps %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: 2 7 1.00 * vandps (%rdi), %xmm1, %xmm2 + +# CHECK: Timeline view: +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeeeER . vaddps %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: [0,1] DeeeeeeeER vandps (%rdi), %xmm1, %xmm2 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 1 1.0 1.0 0.0 vaddps %xmm0, %xmm0, %xmm1 +# CHECK-NEXT: 1. 1 1.0 0.0 0.0 vandps (%rdi), %xmm1, %xmm2 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/vec-logic-read-after-ld-2.s b/llvm/test/tools/llvm-mca/X86/BdVer2/vec-logic-read-after-ld-2.s new file mode 100644 index 00000000000..4768971eb52 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/vec-logic-read-after-ld-2.s @@ -0,0 +1,44 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -timeline -resource-pressure=false < %s | FileCheck %s + +vaddps %ymm0, %ymm0, %ymm1 +vandps (%rdi), %ymm1, %ymm2 + +# CHECK: Iterations: 1 +# CHECK-NEXT: Instructions: 2 +# CHECK-NEXT: Total Cycles: 11 +# CHECK-NEXT: Total uOps: 3 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.27 +# CHECK-NEXT: IPC: 0.18 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 vaddps %ymm0, %ymm0, %ymm1 +# CHECK-NEXT: 2 8 1.00 * vandps (%rdi), %ymm1, %ymm2 + +# CHECK: Timeline view: +# CHECK-NEXT: 0 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeeeER . vaddps %ymm0, %ymm0, %ymm1 +# CHECK-NEXT: [0,1] DeeeeeeeeER vandps (%rdi), %ymm1, %ymm2 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 1 1.0 1.0 0.0 vaddps %ymm0, %ymm0, %ymm1 +# CHECK-NEXT: 1. 1 1.0 0.0 0.0 vandps (%rdi), %ymm1, %ymm2 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/xop-super-registers-1.s b/llvm/test/tools/llvm-mca/X86/BdVer2/xop-super-registers-1.s new file mode 100644 index 00000000000..d7d99861cfb --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/xop-super-registers-1.s @@ -0,0 +1,89 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -timeline -timeline-max-iterations=2 < %s | FileCheck %s + + vmulps %ymm0, %ymm1, %ymm2 + vfrczpd %xmm1, %xmm2 + vmulps %ymm2, %ymm3, %ymm4 + vaddps %ymm4, %ymm5, %ymm6 + vmulps %ymm6, %ymm3, %ymm4 + vaddps %ymm4, %ymm5, %ymm0 + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 600 +# CHECK-NEXT: Total Cycles: 318 +# CHECK-NEXT: Total uOps: 600 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.89 +# CHECK-NEXT: IPC: 1.89 +# CHECK-NEXT: Block RThroughput: 3.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 5 1.00 vmulps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 1 3 1.00 vfrczpd %xmm1, %xmm2 +# CHECK-NEXT: 1 5 1.00 vmulps %ymm2, %ymm3, %ymm4 +# CHECK-NEXT: 1 3 1.00 vaddps %ymm4, %ymm5, %ymm6 +# CHECK-NEXT: 1 5 1.00 vmulps %ymm6, %ymm3, %ymm4 +# CHECK-NEXT: 1 3 1.00 vaddps %ymm4, %ymm5, %ymm0 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 3.00 3.00 - - - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 1.00 - - - - - vmulps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - 1.00 - - - - vfrczpd %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - vmulps %ymm2, %ymm3, %ymm4 +# CHECK-NEXT: - - - 1.00 - - - - vaddps %ymm4, %ymm5, %ymm6 +# CHECK-NEXT: - - 1.00 - - - - - vmulps %ymm6, %ymm3, %ymm4 +# CHECK-NEXT: - - - 1.00 - - - - vaddps %ymm4, %ymm5, %ymm0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 0123456 + +# CHECK: [0,0] DeeeeeER . . . .. vmulps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: [0,1] DeeeE--R . . . .. vfrczpd %xmm1, %xmm2 +# CHECK-NEXT: [0,2] D===eeeeeER . . .. vmulps %ymm2, %ymm3, %ymm4 +# CHECK-NEXT: [0,3] D========eeeER . . .. vaddps %ymm4, %ymm5, %ymm6 +# CHECK-NEXT: [0,4] .D==========eeeeeER . .. vmulps %ymm6, %ymm3, %ymm4 +# CHECK-NEXT: [0,5] .D===============eeeER .. vaddps %ymm4, %ymm5, %ymm0 +# CHECK-NEXT: [1,0] .D==================eeeeeER vmulps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: [1,1] .DeeeE--------------------R vfrczpd %xmm1, %xmm2 +# CHECK-NEXT: [1,2] . D==eeeeeE---------------R vmulps %ymm2, %ymm3, %ymm4 +# CHECK-NEXT: [1,3] . D=======eeeE------------R vaddps %ymm4, %ymm5, %ymm6 +# CHECK-NEXT: [1,4] . D==========eeeeeE-------R vmulps %ymm6, %ymm3, %ymm4 +# CHECK-NEXT: [1,5] . D===============eeeE----R vaddps %ymm4, %ymm5, %ymm0 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 10.0 0.5 0.0 vmulps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 1. 2 1.0 1.0 11.0 vfrczpd %xmm1, %xmm2 +# CHECK-NEXT: 2. 2 3.5 0.0 7.5 vmulps %ymm2, %ymm3, %ymm4 +# CHECK-NEXT: 3. 2 8.5 0.0 6.0 vaddps %ymm4, %ymm5, %ymm6 +# CHECK-NEXT: 4. 2 11.0 0.0 3.5 vmulps %ymm6, %ymm3, %ymm4 +# CHECK-NEXT: 5. 2 16.0 0.0 2.0 vaddps %ymm4, %ymm5, %ymm0 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/xop-super-registers-2.s b/llvm/test/tools/llvm-mca/X86/BdVer2/xop-super-registers-2.s new file mode 100644 index 00000000000..ba59a86a048 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/xop-super-registers-2.s @@ -0,0 +1,89 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -timeline -timeline-max-iterations=2 < %s | FileCheck %s + + vmulps %ymm0, %ymm1, %ymm2 + vpermil2pd $16, %xmm3, %xmm5, %xmm1, %xmm2 + vmulps %ymm2, %ymm3, %ymm4 + vaddps %ymm4, %ymm5, %ymm6 + vmulps %ymm6, %ymm3, %ymm4 + vaddps %ymm4, %ymm5, %ymm0 + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 600 +# CHECK-NEXT: Total Cycles: 316 +# CHECK-NEXT: Total uOps: 600 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.90 +# CHECK-NEXT: IPC: 1.90 +# CHECK-NEXT: Block RThroughput: 3.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 5 1.00 vmulps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 1 1 1.00 vpermil2pd $16, %xmm3, %xmm5, %xmm1, %xmm2 +# CHECK-NEXT: 1 5 1.00 vmulps %ymm2, %ymm3, %ymm4 +# CHECK-NEXT: 1 3 1.00 vaddps %ymm4, %ymm5, %ymm6 +# CHECK-NEXT: 1 5 1.00 vmulps %ymm6, %ymm3, %ymm4 +# CHECK-NEXT: 1 3 1.00 vaddps %ymm4, %ymm5, %ymm0 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 3.00 2.00 - 1.00 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - 1.00 - - - - - vmulps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 - - vpermil2pd $16, %xmm3, %xmm5, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - vmulps %ymm2, %ymm3, %ymm4 +# CHECK-NEXT: - - - 1.00 - - - - vaddps %ymm4, %ymm5, %ymm6 +# CHECK-NEXT: - - 1.00 - - - - - vmulps %ymm6, %ymm3, %ymm4 +# CHECK-NEXT: - - - 1.00 - - - - vaddps %ymm4, %ymm5, %ymm0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 01234 + +# CHECK: [0,0] DeeeeeER . . . . vmulps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: [0,1] DeE----R . . . . vpermil2pd $16, %xmm3, %xmm5, %xmm1, %xmm2 +# CHECK-NEXT: [0,2] D=eeeeeER . . . . vmulps %ymm2, %ymm3, %ymm4 +# CHECK-NEXT: [0,3] D======eeeER . . . vaddps %ymm4, %ymm5, %ymm6 +# CHECK-NEXT: [0,4] .D========eeeeeER . . vmulps %ymm6, %ymm3, %ymm4 +# CHECK-NEXT: [0,5] .D=============eeeER. . vaddps %ymm4, %ymm5, %ymm0 +# CHECK-NEXT: [1,0] .D================eeeeeER vmulps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: [1,1] .DeE--------------------R vpermil2pd $16, %xmm3, %xmm5, %xmm1, %xmm2 +# CHECK-NEXT: [1,2] . DeeeeeE---------------R vmulps %ymm2, %ymm3, %ymm4 +# CHECK-NEXT: [1,3] . D=====eeeE------------R vaddps %ymm4, %ymm5, %ymm6 +# CHECK-NEXT: [1,4] . D========eeeeeE-------R vmulps %ymm6, %ymm3, %ymm4 +# CHECK-NEXT: [1,5] . D=============eeeE----R vaddps %ymm4, %ymm5, %ymm0 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 2 9.0 0.5 0.0 vmulps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 1. 2 1.0 1.0 12.0 vpermil2pd $16, %xmm3, %xmm5, %xmm1, %xmm2 +# CHECK-NEXT: 2. 2 1.5 0.0 7.5 vmulps %ymm2, %ymm3, %ymm4 +# CHECK-NEXT: 3. 2 6.5 0.0 6.0 vaddps %ymm4, %ymm5, %ymm6 +# CHECK-NEXT: 4. 2 9.0 0.0 3.5 vmulps %ymm6, %ymm3, %ymm4 +# CHECK-NEXT: 5. 2 14.0 0.0 2.0 vaddps %ymm4, %ymm5, %ymm0 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/zero-idioms-avx-256.s b/llvm/test/tools/llvm-mca/X86/BdVer2/zero-idioms-avx-256.s new file mode 100644 index 00000000000..8290cacdf05 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/zero-idioms-avx-256.s @@ -0,0 +1,365 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -timeline -timeline-max-iterations=3 < %s | FileCheck %s + +# TODO: Fix the processor resource usage for zero-idiom YMM XOR instructions. +# Those vector XOR instructions should only consume 1cy of JFPU1 (instead +# of 2cy). + +# LLVM-MCA-BEGIN ZERO-IDIOM-1 + +vaddps %ymm0, %ymm0, %ymm1 +vxorps %ymm1, %ymm1, %ymm1 +vblendps $2, %ymm1, %ymm2, %ymm3 + +# LLVM-MCA-END + +# LLVM-MCA-BEGIN ZERO-IDIOM-2 + +vaddpd %ymm0, %ymm0, %ymm1 +vxorpd %ymm1, %ymm1, %ymm1 +vblendpd $2, %ymm1, %ymm2, %ymm3 + +# LLVM-MCA-END + +# LLVM-MCA-BEGIN ZERO-IDIOM-3 +vaddps %ymm0, %ymm1, %ymm2 +vandnps %ymm2, %ymm2, %ymm3 +# LLVM-MCA-END + +# LLVM-MCA-BEGIN ZERO-IDIOM-4 +vaddps %ymm0, %ymm1, %ymm2 +vandnps %ymm2, %ymm2, %ymm3 +# LLVM-MCA-END + +# LLVM-MCA-BEGIN ZERO-IDIOM-5 +vperm2f128 $136, %ymm0, %ymm0, %ymm1 +vaddps %ymm1, %ymm1, %ymm0 +# LLVM-MCA-END + +# CHECK: [0] Code Region - ZERO-IDIOM-1 + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 300 +# CHECK-NEXT: Total Cycles: 107 +# CHECK-NEXT: Total uOps: 300 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 2.80 +# CHECK-NEXT: IPC: 2.80 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 vaddps %ymm0, %ymm0, %ymm1 +# CHECK-NEXT: 1 1 1.00 vxorps %ymm1, %ymm1, %ymm1 +# CHECK-NEXT: 1 1 0.50 vblendps $2, %ymm1, %ymm2, %ymm3 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - - - - vaddps %ymm0, %ymm0, %ymm1 +# CHECK-NEXT: - - - - - 1.00 - - vxorps %ymm1, %ymm1, %ymm1 +# CHECK-NEXT: - - 1.00 - - - - - vblendps $2, %ymm1, %ymm2, %ymm3 + +# CHECK: Timeline view: +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeeeER . vaddps %ymm0, %ymm0, %ymm1 +# CHECK-NEXT: [0,1] D===eER . vxorps %ymm1, %ymm1, %ymm1 +# CHECK-NEXT: [0,2] D====eER . vblendps $2, %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: [1,0] D=eeeE-R . vaddps %ymm0, %ymm0, %ymm1 +# CHECK-NEXT: [1,1] .D===eER . vxorps %ymm1, %ymm1, %ymm1 +# CHECK-NEXT: [1,2] .D====eER. vblendps $2, %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: [2,0] .D=eeeE-R. vaddps %ymm0, %ymm0, %ymm1 +# CHECK-NEXT: [2,1] .D====eER. vxorps %ymm1, %ymm1, %ymm1 +# CHECK-NEXT: [2,2] . D====eER vblendps $2, %ymm1, %ymm2, %ymm3 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 1.7 1.7 0.7 vaddps %ymm0, %ymm0, %ymm1 +# CHECK-NEXT: 1. 3 4.3 0.0 0.0 vxorps %ymm1, %ymm1, %ymm1 +# CHECK-NEXT: 2. 3 5.0 0.0 0.0 vblendps $2, %ymm1, %ymm2, %ymm3 + +# CHECK: [1] Code Region - ZERO-IDIOM-2 + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 300 +# CHECK-NEXT: Total Cycles: 107 +# CHECK-NEXT: Total uOps: 300 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 2.80 +# CHECK-NEXT: IPC: 2.80 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 vaddpd %ymm0, %ymm0, %ymm1 +# CHECK-NEXT: 1 1 1.00 vxorpd %ymm1, %ymm1, %ymm1 +# CHECK-NEXT: 1 1 0.50 vblendpd $2, %ymm1, %ymm2, %ymm3 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - - - - vaddpd %ymm0, %ymm0, %ymm1 +# CHECK-NEXT: - - - - - 1.00 - - vxorpd %ymm1, %ymm1, %ymm1 +# CHECK-NEXT: - - 1.00 - - - - - vblendpd $2, %ymm1, %ymm2, %ymm3 + +# CHECK: Timeline view: +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeeeER . vaddpd %ymm0, %ymm0, %ymm1 +# CHECK-NEXT: [0,1] D===eER . vxorpd %ymm1, %ymm1, %ymm1 +# CHECK-NEXT: [0,2] D====eER . vblendpd $2, %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: [1,0] D=eeeE-R . vaddpd %ymm0, %ymm0, %ymm1 +# CHECK-NEXT: [1,1] .D===eER . vxorpd %ymm1, %ymm1, %ymm1 +# CHECK-NEXT: [1,2] .D====eER. vblendpd $2, %ymm1, %ymm2, %ymm3 +# CHECK-NEXT: [2,0] .D=eeeE-R. vaddpd %ymm0, %ymm0, %ymm1 +# CHECK-NEXT: [2,1] .D====eER. vxorpd %ymm1, %ymm1, %ymm1 +# CHECK-NEXT: [2,2] . D====eER vblendpd $2, %ymm1, %ymm2, %ymm3 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 1.7 1.7 0.7 vaddpd %ymm0, %ymm0, %ymm1 +# CHECK-NEXT: 1. 3 4.3 0.0 0.0 vxorpd %ymm1, %ymm1, %ymm1 +# CHECK-NEXT: 2. 3 5.0 0.0 0.0 vblendpd $2, %ymm1, %ymm2, %ymm3 + +# CHECK: [2] Code Region - ZERO-IDIOM-3 + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 200 +# CHECK-NEXT: Total Cycles: 106 +# CHECK-NEXT: Total uOps: 200 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.89 +# CHECK-NEXT: IPC: 1.89 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 vaddps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 1 1 1.00 vandnps %ymm2, %ymm2, %ymm3 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - - 1.00 - 1.00 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - - - - vaddps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 - - vandnps %ymm2, %ymm2, %ymm3 + +# CHECK: Timeline view: +# CHECK-NEXT: Index 012345678 + +# CHECK: [0,0] DeeeER . vaddps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: [0,1] D===eER . vandnps %ymm2, %ymm2, %ymm3 +# CHECK-NEXT: [1,0] D=eeeER . vaddps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: [1,1] D====eER. vandnps %ymm2, %ymm2, %ymm3 +# CHECK-NEXT: [2,0] .D=eeeER. vaddps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: [2,1] .D====eER vandnps %ymm2, %ymm2, %ymm3 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 1.7 1.7 0.0 vaddps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 1. 3 4.7 0.0 0.0 vandnps %ymm2, %ymm2, %ymm3 + +# CHECK: [3] Code Region - ZERO-IDIOM-4 + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 200 +# CHECK-NEXT: Total Cycles: 106 +# CHECK-NEXT: Total uOps: 200 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.89 +# CHECK-NEXT: IPC: 1.89 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 vaddps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 1 1 1.00 vandnps %ymm2, %ymm2, %ymm3 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - - 1.00 - 1.00 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - 1.00 - - - - vaddps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - - - 1.00 - - vandnps %ymm2, %ymm2, %ymm3 + +# CHECK: Timeline view: +# CHECK-NEXT: Index 012345678 + +# CHECK: [0,0] DeeeER . vaddps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: [0,1] D===eER . vandnps %ymm2, %ymm2, %ymm3 +# CHECK-NEXT: [1,0] D=eeeER . vaddps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: [1,1] D====eER. vandnps %ymm2, %ymm2, %ymm3 +# CHECK-NEXT: [2,0] .D=eeeER. vaddps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: [2,1] .D====eER vandnps %ymm2, %ymm2, %ymm3 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 1.7 1.7 0.0 vaddps %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 1. 3 4.7 0.0 0.0 vandnps %ymm2, %ymm2, %ymm3 + +# CHECK: [4] Code Region - ZERO-IDIOM-5 + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 200 +# CHECK-NEXT: Total Cycles: 403 +# CHECK-NEXT: Total uOps: 200 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 0.50 +# CHECK-NEXT: IPC: 0.50 +# CHECK-NEXT: Block RThroughput: 1.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 1.00 vperm2f128 $136, %ymm0, %ymm0, %ymm1 +# CHECK-NEXT: 1 3 1.00 vaddps %ymm1, %ymm1, %ymm0 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - - 1.00 - 1.00 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - - - 1.00 - - vperm2f128 $136, %ymm0, %ymm0, %ymm1 +# CHECK-NEXT: - - - 1.00 - - - - vaddps %ymm1, %ymm1, %ymm0 + +# CHECK: Timeline view: +# CHECK-NEXT: 01234 +# CHECK-NEXT: Index 0123456789 + +# CHECK: [0,0] DeER . . . vperm2f128 $136, %ymm0, %ymm0, %ymm1 +# CHECK-NEXT: [0,1] D=eeeER . . vaddps %ymm1, %ymm1, %ymm0 +# CHECK-NEXT: [1,0] D====eER . . vperm2f128 $136, %ymm0, %ymm0, %ymm1 +# CHECK-NEXT: [1,1] D=====eeeER . vaddps %ymm1, %ymm1, %ymm0 +# CHECK-NEXT: [2,0] .D=======eER . vperm2f128 $136, %ymm0, %ymm0, %ymm1 +# CHECK-NEXT: [2,1] .D========eeeER vaddps %ymm1, %ymm1, %ymm0 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 3 4.7 0.3 0.0 vperm2f128 $136, %ymm0, %ymm0, %ymm1 +# CHECK-NEXT: 1. 3 5.7 0.0 0.0 vaddps %ymm1, %ymm1, %ymm0 diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/zero-idioms.s b/llvm/test/tools/llvm-mca/X86/BdVer2/zero-idioms.s new file mode 100644 index 00000000000..034542e655b --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BdVer2/zero-idioms.s @@ -0,0 +1,427 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -timeline -register-file-stats -iterations=1 < %s | FileCheck %s + +subl %eax, %eax +subq %rax, %rax +xorl %eax, %eax +xorq %rax, %rax + +pcmpgtb %mm2, %mm2 +pcmpgtd %mm2, %mm2 +# pcmpgtq %mm2, %mm2 # invalid operand for instruction +pcmpgtw %mm2, %mm2 + +pcmpgtb %xmm2, %xmm2 +pcmpgtd %xmm2, %xmm2 +pcmpgtq %xmm2, %xmm2 +pcmpgtw %xmm2, %xmm2 + +vpcmpgtb %xmm3, %xmm3, %xmm3 +vpcmpgtd %xmm3, %xmm3, %xmm3 +vpcmpgtq %xmm3, %xmm3, %xmm3 +vpcmpgtw %xmm3, %xmm3, %xmm3 + +vpcmpgtb %xmm3, %xmm3, %xmm5 +vpcmpgtd %xmm3, %xmm3, %xmm5 +vpcmpgtq %xmm3, %xmm3, %xmm5 +vpcmpgtw %xmm3, %xmm3, %xmm5 + +psubb %mm2, %mm2 +psubd %mm2, %mm2 +psubq %mm2, %mm2 +psubw %mm2, %mm2 +psubb %xmm2, %xmm2 +psubd %xmm2, %xmm2 +psubq %xmm2, %xmm2 +psubw %xmm2, %xmm2 +vpsubb %xmm3, %xmm3, %xmm3 +vpsubd %xmm3, %xmm3, %xmm3 +vpsubq %xmm3, %xmm3, %xmm3 +vpsubw %xmm3, %xmm3, %xmm3 + +vpsubb %xmm3, %xmm3, %xmm5 +vpsubd %xmm3, %xmm3, %xmm5 +vpsubq %xmm3, %xmm3, %xmm5 +vpsubw %xmm3, %xmm3, %xmm5 + +psubsb %mm2, %mm2 +psubsw %mm2, %mm2 +psubsb %xmm2, %xmm2 +psubsw %xmm2, %xmm2 +vpsubsb %xmm3, %xmm3, %xmm3 +vpsubsw %xmm3, %xmm3, %xmm3 + +vpsubsb %xmm3, %xmm3, %xmm5 +vpsubsw %xmm3, %xmm3, %xmm5 + +psubusb %mm2, %mm2 +psubusw %mm2, %mm2 +psubusb %xmm2, %xmm2 +psubusw %xmm2, %xmm2 +vpsubusb %xmm3, %xmm3, %xmm3 +vpsubusw %xmm3, %xmm3, %xmm3 + +vpsubsb %xmm3, %xmm3, %xmm5 +vpsubsw %xmm3, %xmm3, %xmm5 + +andnps %xmm0, %xmm0 +andnpd %xmm1, %xmm1 +vandnps %xmm2, %xmm2, %xmm2 +vandnpd %xmm1, %xmm1, %xmm1 +pandn %mm2, %mm2 +pandn %xmm2, %xmm2 +vpandn %xmm3, %xmm3, %xmm3 + +vandnps %xmm2, %xmm2, %xmm5 +vandnpd %xmm1, %xmm1, %xmm5 +vpandn %xmm3, %xmm3, %xmm5 + +xorps %xmm0, %xmm0 +xorpd %xmm1, %xmm1 +vxorps %xmm2, %xmm2, %xmm2 +vxorpd %xmm1, %xmm1, %xmm1 +pxor %mm2, %mm2 +pxor %xmm2, %xmm2 +vpxor %xmm3, %xmm3, %xmm3 + +vxorps %xmm4, %xmm4, %xmm5 +vxorpd %xmm1, %xmm1, %xmm3 +vpxor %xmm3, %xmm3, %xmm5 + +# CHECK: Iterations: 1 +# CHECK-NEXT: Instructions: 71 +# CHECK-NEXT: Total Cycles: 39 +# CHECK-NEXT: Total uOps: 71 + +# CHECK: Dispatch Width: 4 +# CHECK-NEXT: uOps Per Cycle: 1.82 +# CHECK-NEXT: IPC: 1.82 +# CHECK-NEXT: Block RThroughput: 17.8 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 0 0.25 subl %eax, %eax +# CHECK-NEXT: 1 0 0.25 subq %rax, %rax +# CHECK-NEXT: 1 0 0.25 xorl %eax, %eax +# CHECK-NEXT: 1 0 0.25 xorq %rax, %rax +# CHECK-NEXT: 1 3 1.00 pcmpgtb %mm2, %mm2 +# CHECK-NEXT: 1 3 1.00 pcmpgtd %mm2, %mm2 +# CHECK-NEXT: 1 3 1.00 pcmpgtw %mm2, %mm2 +# CHECK-NEXT: 1 0 0.25 pcmpgtb %xmm2, %xmm2 +# CHECK-NEXT: 1 0 0.25 pcmpgtd %xmm2, %xmm2 +# CHECK-NEXT: 1 0 0.25 pcmpgtq %xmm2, %xmm2 +# CHECK-NEXT: 1 0 0.25 pcmpgtw %xmm2, %xmm2 +# CHECK-NEXT: 1 0 0.25 vpcmpgtb %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 1 0 0.25 vpcmpgtd %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 1 0 0.25 vpcmpgtq %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 1 0 0.25 vpcmpgtw %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 1 0 0.25 vpcmpgtb %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 1 0 0.25 vpcmpgtd %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 1 0 0.25 vpcmpgtq %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 1 0 0.25 vpcmpgtw %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 1 3 1.00 psubb %mm2, %mm2 +# CHECK-NEXT: 1 3 1.00 psubd %mm2, %mm2 +# CHECK-NEXT: 1 3 1.00 psubq %mm2, %mm2 +# CHECK-NEXT: 1 3 1.00 psubw %mm2, %mm2 +# CHECK-NEXT: 1 0 0.25 psubb %xmm2, %xmm2 +# CHECK-NEXT: 1 0 0.25 psubd %xmm2, %xmm2 +# CHECK-NEXT: 1 0 0.25 psubq %xmm2, %xmm2 +# CHECK-NEXT: 1 0 0.25 psubw %xmm2, %xmm2 +# CHECK-NEXT: 1 0 0.25 vpsubb %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 1 0 0.25 vpsubd %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 1 0 0.25 vpsubq %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 1 0 0.25 vpsubw %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 1 0 0.25 vpsubb %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 1 0 0.25 vpsubd %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 1 0 0.25 vpsubq %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 1 0 0.25 vpsubw %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 1 3 1.00 psubsb %mm2, %mm2 +# CHECK-NEXT: 1 3 1.00 psubsw %mm2, %mm2 +# CHECK-NEXT: 1 1 0.50 psubsb %xmm2, %xmm2 +# CHECK-NEXT: 1 1 0.50 psubsw %xmm2, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpsubsb %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 1 1 0.50 vpsubsw %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 1 1 0.50 vpsubsb %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 1 1 0.50 vpsubsw %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 1 3 1.00 psubusb %mm2, %mm2 +# CHECK-NEXT: 1 3 1.00 psubusw %mm2, %mm2 +# CHECK-NEXT: 1 1 0.50 psubusb %xmm2, %xmm2 +# CHECK-NEXT: 1 1 0.50 psubusw %xmm2, %xmm2 +# CHECK-NEXT: 1 1 0.50 vpsubusb %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 1 1 0.50 vpsubusw %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 1 1 0.50 vpsubsb %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 1 1 0.50 vpsubsw %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 1 1 1.00 andnps %xmm0, %xmm0 +# CHECK-NEXT: 1 1 1.00 andnpd %xmm1, %xmm1 +# CHECK-NEXT: 1 1 1.00 vandnps %xmm2, %xmm2, %xmm2 +# CHECK-NEXT: 1 1 1.00 vandnpd %xmm1, %xmm1, %xmm1 +# CHECK-NEXT: 1 1 0.33 pandn %mm2, %mm2 +# CHECK-NEXT: 1 1 0.33 pandn %xmm2, %xmm2 +# CHECK-NEXT: 1 1 0.33 vpandn %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 1 1 1.00 vandnps %xmm2, %xmm2, %xmm5 +# CHECK-NEXT: 1 1 1.00 vandnpd %xmm1, %xmm1, %xmm5 +# CHECK-NEXT: 1 1 0.33 vpandn %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 1 0 0.25 xorps %xmm0, %xmm0 +# CHECK-NEXT: 1 0 0.25 xorpd %xmm1, %xmm1 +# CHECK-NEXT: 1 0 0.25 vxorps %xmm2, %xmm2, %xmm2 +# CHECK-NEXT: 1 0 0.25 vxorpd %xmm1, %xmm1, %xmm1 +# CHECK-NEXT: 1 1 0.33 pxor %mm2, %mm2 +# CHECK-NEXT: 1 0 0.25 pxor %xmm2, %xmm2 +# CHECK-NEXT: 1 0 0.25 vpxor %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 1 0 0.25 vxorps %xmm4, %xmm4, %xmm5 +# CHECK-NEXT: 1 0 0.25 vxorpd %xmm1, %xmm1, %xmm3 +# CHECK-NEXT: 1 0 0.25 vpxor %xmm3, %xmm3, %xmm5 + +# CHECK: Register File statistics: +# CHECK-NEXT: Total number of mappings created: 75 +# CHECK-NEXT: Max number of mappings used: 51 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SBDivider +# CHECK-NEXT: [1] - SBFPDivider +# CHECK-NEXT: [2] - SBPort0 +# CHECK-NEXT: [3] - SBPort1 +# CHECK-NEXT: [4] - SBPort4 +# CHECK-NEXT: [5] - SBPort5 +# CHECK-NEXT: [6.0] - SBPort23 +# CHECK-NEXT: [6.1] - SBPort23 + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] +# CHECK-NEXT: - - 5.00 16.00 - 13.00 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: +# CHECK-NEXT: - - - - - - - - subl %eax, %eax +# CHECK-NEXT: - - - - - - - - subq %rax, %rax +# CHECK-NEXT: - - - - - - - - xorl %eax, %eax +# CHECK-NEXT: - - - - - - - - xorq %rax, %rax +# CHECK-NEXT: - - - 1.00 - - - - pcmpgtb %mm2, %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pcmpgtd %mm2, %mm2 +# CHECK-NEXT: - - - 1.00 - - - - pcmpgtw %mm2, %mm2 +# CHECK-NEXT: - - - - - - - - pcmpgtb %xmm2, %xmm2 +# CHECK-NEXT: - - - - - - - - pcmpgtd %xmm2, %xmm2 +# CHECK-NEXT: - - - - - - - - pcmpgtq %xmm2, %xmm2 +# CHECK-NEXT: - - - - - - - - pcmpgtw %xmm2, %xmm2 +# CHECK-NEXT: - - - - - - - - vpcmpgtb %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: - - - - - - - - vpcmpgtd %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: - - - - - - - - vpcmpgtq %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: - - - - - - - - vpcmpgtw %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: - - - - - - - - vpcmpgtb %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: - - - - - - - - vpcmpgtd %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: - - - - - - - - vpcmpgtq %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: - - - - - - - - vpcmpgtw %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: - - - 1.00 - - - - psubb %mm2, %mm2 +# CHECK-NEXT: - - - 1.00 - - - - psubd %mm2, %mm2 +# CHECK-NEXT: - - - 1.00 - - - - psubq %mm2, %mm2 +# CHECK-NEXT: - - - 1.00 - - - - psubw %mm2, %mm2 +# CHECK-NEXT: - - - - - - - - psubb %xmm2, %xmm2 +# CHECK-NEXT: - - - - - - - - psubd %xmm2, %xmm2 +# CHECK-NEXT: - - - - - - - - psubq %xmm2, %xmm2 +# CHECK-NEXT: - - - - - - - - psubw %xmm2, %xmm2 +# CHECK-NEXT: - - - - - - - - vpsubb %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: - - - - - - - - vpsubd %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: - - - - - - - - vpsubq %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: - - - - - - - - vpsubw %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: - - - - - - - - vpsubb %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: - - - - - - - - vpsubd %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: - - - - - - - - vpsubq %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: - - - - - - - - vpsubw %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: - - - 1.00 - - - - psubsb %mm2, %mm2 +# CHECK-NEXT: - - - 1.00 - - - - psubsw %mm2, %mm2 +# CHECK-NEXT: - - - - - 1.00 - - psubsb %xmm2, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - psubsw %xmm2, %xmm2 +# CHECK-NEXT: - - - 1.00 - - - - vpsubsb %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: - - - - - 1.00 - - vpsubsw %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: - - - 1.00 - - - - vpsubsb %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: - - - - - 1.00 - - vpsubsw %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: - - - 1.00 - - - - psubusb %mm2, %mm2 +# CHECK-NEXT: - - - 1.00 - - - - psubusw %mm2, %mm2 +# CHECK-NEXT: - - - 1.00 - - - - psubusb %xmm2, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - psubusw %xmm2, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vpsubusb %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: - - - 1.00 - - - - vpsubusw %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: - - - - - 1.00 - - vpsubsb %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: - - - 1.00 - - - - vpsubsw %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: - - - - - 1.00 - - andnps %xmm0, %xmm0 +# CHECK-NEXT: - - - - - 1.00 - - andnpd %xmm1, %xmm1 +# CHECK-NEXT: - - - - - 1.00 - - vandnps %xmm2, %xmm2, %xmm2 +# CHECK-NEXT: - - - - - 1.00 - - vandnpd %xmm1, %xmm1, %xmm1 +# CHECK-NEXT: - - 1.00 - - - - - pandn %mm2, %mm2 +# CHECK-NEXT: - - 1.00 - - - - - pandn %xmm2, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - vpandn %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: - - - - - 1.00 - - vandnps %xmm2, %xmm2, %xmm5 +# CHECK-NEXT: - - - - - 1.00 - - vandnpd %xmm1, %xmm1, %xmm5 +# CHECK-NEXT: - - 1.00 - - - - - vpandn %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: - - - - - - - - xorps %xmm0, %xmm0 +# CHECK-NEXT: - - - - - - - - xorpd %xmm1, %xmm1 +# CHECK-NEXT: - - - - - - - - vxorps %xmm2, %xmm2, %xmm2 +# CHECK-NEXT: - - - - - - - - vxorpd %xmm1, %xmm1, %xmm1 +# CHECK-NEXT: - - 1.00 - - - - - pxor %mm2, %mm2 +# CHECK-NEXT: - - - - - - - - pxor %xmm2, %xmm2 +# CHECK-NEXT: - - - - - - - - vpxor %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: - - - - - - - - vxorps %xmm4, %xmm4, %xmm5 +# CHECK-NEXT: - - - - - - - - vxorpd %xmm1, %xmm1, %xmm3 +# CHECK-NEXT: - - - - - - - - vpxor %xmm3, %xmm3, %xmm5 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 012345678 +# CHECK-NEXT: Index 0123456789 0123456789 + +# CHECK: [0,0] DR . . . . . . . . subl %eax, %eax +# CHECK-NEXT: [0,1] DR . . . . . . . . subq %rax, %rax +# CHECK-NEXT: [0,2] DR . . . . . . . . xorl %eax, %eax +# CHECK-NEXT: [0,3] DR . . . . . . . . xorq %rax, %rax +# CHECK-NEXT: [0,4] .DeeeER . . . . . . . pcmpgtb %mm2, %mm2 +# CHECK-NEXT: [0,5] .D===eeeER. . . . . . . pcmpgtd %mm2, %mm2 +# CHECK-NEXT: [0,6] .D======eeeER . . . . . . pcmpgtw %mm2, %mm2 +# CHECK-NEXT: [0,7] .D----------R . . . . . . pcmpgtb %xmm2, %xmm2 +# CHECK-NEXT: [0,8] . D---------R . . . . . . pcmpgtd %xmm2, %xmm2 +# CHECK-NEXT: [0,9] . D---------R . . . . . . pcmpgtq %xmm2, %xmm2 +# CHECK-NEXT: [0,10] . D---------R . . . . . . pcmpgtw %xmm2, %xmm2 +# CHECK-NEXT: [0,11] . D---------R . . . . . . vpcmpgtb %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,12] . D--------R . . . . . . vpcmpgtd %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,13] . D--------R . . . . . . vpcmpgtq %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,14] . D--------R . . . . . . vpcmpgtw %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,15] . D--------R . . . . . . vpcmpgtb %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,16] . D-------R . . . . . . vpcmpgtd %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,17] . D-------R . . . . . . vpcmpgtq %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,18] . D-------R . . . . . . vpcmpgtw %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,19] . D======eeeER . . . . . psubb %mm2, %mm2 +# CHECK-NEXT: [0,20] . D========eeeER . . . . . psubd %mm2, %mm2 +# CHECK-NEXT: [0,21] . D===========eeeER . . . . psubq %mm2, %mm2 +# CHECK-NEXT: [0,22] . D==============eeeER. . . . psubw %mm2, %mm2 +# CHECK-NEXT: [0,23] . D------------------R. . . . psubb %xmm2, %xmm2 +# CHECK-NEXT: [0,24] . .D-----------------R. . . . psubd %xmm2, %xmm2 +# CHECK-NEXT: [0,25] . .D-----------------R. . . . psubq %xmm2, %xmm2 +# CHECK-NEXT: [0,26] . .D-----------------R. . . . psubw %xmm2, %xmm2 +# CHECK-NEXT: [0,27] . .D-----------------R. . . . vpsubb %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,28] . . D----------------R. . . . vpsubd %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,29] . . D----------------R. . . . vpsubq %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,30] . . D----------------R. . . . vpsubw %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,31] . . D----------------R. . . . vpsubb %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,32] . . D---------------R. . . . vpsubd %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,33] . . D---------------R. . . . vpsubq %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,34] . . D---------------R. . . . vpsubw %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,35] . . D==============eeeER . . . psubsb %mm2, %mm2 +# CHECK-NEXT: [0,36] . . D================eeeER . . psubsw %mm2, %mm2 +# CHECK-NEXT: [0,37] . . DeE------------------R . . psubsb %xmm2, %xmm2 +# CHECK-NEXT: [0,38] . . D==eE----------------R . . psubsw %xmm2, %xmm2 +# CHECK-NEXT: [0,39] . . DeE------------------R . . vpsubsb %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,40] . . DeE-----------------R . . vpsubsw %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,41] . . D=eE----------------R . . vpsubsb %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,42] . . D==eE---------------R . . vpsubsw %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,43] . . D==================eeeER . . psubusb %mm2, %mm2 +# CHECK-NEXT: [0,44] . . .D====================eeeER . psubusw %mm2, %mm2 +# CHECK-NEXT: [0,45] . . .D=eE---------------------R . psubusb %xmm2, %xmm2 +# CHECK-NEXT: [0,46] . . .D==eE--------------------R . psubusw %xmm2, %xmm2 +# CHECK-NEXT: [0,47] . . .D===eE-------------------R . vpsubusb %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,48] . . . D===eE------------------R . vpsubusw %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,49] . . . D====eE-----------------R . vpsubsb %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,50] . . . D=====eE----------------R . vpsubsw %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,51] . . . D===eE------------------R . andnps %xmm0, %xmm0 +# CHECK-NEXT: [0,52] . . . D====eE----------------R . andnpd %xmm1, %xmm1 +# CHECK-NEXT: [0,53] . . . D======eE--------------R . vandnps %xmm2, %xmm2, %xmm2 +# CHECK-NEXT: [0,54] . . . D=====eE---------------R . vandnpd %xmm1, %xmm1, %xmm1 +# CHECK-NEXT: [0,55] . . . D=====================eER. pandn %mm2, %mm2 +# CHECK-NEXT: [0,56] . . . D======eE--------------R. pandn %xmm2, %xmm2 +# CHECK-NEXT: [0,57] . . . D==eE------------------R. vpandn %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,58] . . . D=======eE-------------R. vandnps %xmm2, %xmm2, %xmm5 +# CHECK-NEXT: [0,59] . . . D======eE--------------R. vandnpd %xmm1, %xmm1, %xmm5 +# CHECK-NEXT: [0,60] . . . D==eE-----------------R. vpandn %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: [0,61] . . . D=E-------------------R. xorps %xmm0, %xmm0 +# CHECK-NEXT: [0,62] . . . D====E----------------R. xorpd %xmm1, %xmm1 +# CHECK-NEXT: [0,63] . . . D======E--------------R. vxorps %xmm2, %xmm2, %xmm2 +# CHECK-NEXT: [0,64] . . . .D===E----------------R. vxorpd %xmm1, %xmm1, %xmm1 +# CHECK-NEXT: [0,65] . . . .D===================eER pxor %mm2, %mm2 +# CHECK-NEXT: [0,66] . . . .D=====E---------------R pxor %xmm2, %xmm2 +# CHECK-NEXT: [0,67] . . . .D=E-------------------R vpxor %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: [0,68] . . . . D--------------------R vxorps %xmm4, %xmm4, %xmm5 +# CHECK-NEXT: [0,69] . . . . D==E-----------------R vxorpd %xmm1, %xmm1, %xmm3 +# CHECK-NEXT: [0,70] . . . . D==E-----------------R vpxor %xmm3, %xmm3, %xmm5 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 1 0.0 0.0 0.0 subl %eax, %eax +# CHECK-NEXT: 1. 1 0.0 0.0 0.0 subq %rax, %rax +# CHECK-NEXT: 2. 1 0.0 0.0 0.0 xorl %eax, %eax +# CHECK-NEXT: 3. 1 0.0 0.0 0.0 xorq %rax, %rax +# CHECK-NEXT: 4. 1 1.0 1.0 0.0 pcmpgtb %mm2, %mm2 +# CHECK-NEXT: 5. 1 4.0 0.0 0.0 pcmpgtd %mm2, %mm2 +# CHECK-NEXT: 6. 1 7.0 0.0 0.0 pcmpgtw %mm2, %mm2 +# CHECK-NEXT: 7. 1 0.0 0.0 10.0 pcmpgtb %xmm2, %xmm2 +# CHECK-NEXT: 8. 1 0.0 0.0 9.0 pcmpgtd %xmm2, %xmm2 +# CHECK-NEXT: 9. 1 0.0 0.0 9.0 pcmpgtq %xmm2, %xmm2 +# CHECK-NEXT: 10. 1 0.0 0.0 9.0 pcmpgtw %xmm2, %xmm2 +# CHECK-NEXT: 11. 1 0.0 0.0 9.0 vpcmpgtb %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 12. 1 0.0 0.0 8.0 vpcmpgtd %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 13. 1 0.0 0.0 8.0 vpcmpgtq %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 14. 1 0.0 0.0 8.0 vpcmpgtw %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 15. 1 0.0 0.0 8.0 vpcmpgtb %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 16. 1 0.0 0.0 7.0 vpcmpgtd %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 17. 1 0.0 0.0 7.0 vpcmpgtq %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 18. 1 0.0 0.0 7.0 vpcmpgtw %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 19. 1 7.0 0.0 0.0 psubb %mm2, %mm2 +# CHECK-NEXT: 20. 1 9.0 0.0 0.0 psubd %mm2, %mm2 +# CHECK-NEXT: 21. 1 12.0 0.0 0.0 psubq %mm2, %mm2 +# CHECK-NEXT: 22. 1 15.0 0.0 0.0 psubw %mm2, %mm2 +# CHECK-NEXT: 23. 1 0.0 0.0 18.0 psubb %xmm2, %xmm2 +# CHECK-NEXT: 24. 1 0.0 0.0 17.0 psubd %xmm2, %xmm2 +# CHECK-NEXT: 25. 1 0.0 0.0 17.0 psubq %xmm2, %xmm2 +# CHECK-NEXT: 26. 1 0.0 0.0 17.0 psubw %xmm2, %xmm2 +# CHECK-NEXT: 27. 1 0.0 0.0 17.0 vpsubb %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 28. 1 0.0 0.0 16.0 vpsubd %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 29. 1 0.0 0.0 16.0 vpsubq %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 30. 1 0.0 0.0 16.0 vpsubw %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 31. 1 0.0 0.0 16.0 vpsubb %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 32. 1 0.0 0.0 15.0 vpsubd %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 33. 1 0.0 0.0 15.0 vpsubq %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 34. 1 0.0 0.0 15.0 vpsubw %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 35. 1 15.0 0.0 0.0 psubsb %mm2, %mm2 +# CHECK-NEXT: 36. 1 17.0 0.0 0.0 psubsw %mm2, %mm2 +# CHECK-NEXT: 37. 1 1.0 1.0 18.0 psubsb %xmm2, %xmm2 +# CHECK-NEXT: 38. 1 3.0 1.0 16.0 psubsw %xmm2, %xmm2 +# CHECK-NEXT: 39. 1 1.0 1.0 18.0 vpsubsb %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 40. 1 1.0 0.0 17.0 vpsubsw %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 41. 1 2.0 0.0 16.0 vpsubsb %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 42. 1 3.0 1.0 15.0 vpsubsw %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 43. 1 19.0 0.0 0.0 psubusb %mm2, %mm2 +# CHECK-NEXT: 44. 1 21.0 0.0 0.0 psubusw %mm2, %mm2 +# CHECK-NEXT: 45. 1 2.0 0.0 21.0 psubusb %xmm2, %xmm2 +# CHECK-NEXT: 46. 1 3.0 0.0 20.0 psubusw %xmm2, %xmm2 +# CHECK-NEXT: 47. 1 4.0 3.0 19.0 vpsubusb %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 48. 1 4.0 0.0 18.0 vpsubusw %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 49. 1 5.0 0.0 17.0 vpsubsb %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 50. 1 6.0 1.0 16.0 vpsubsw %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 51. 1 4.0 4.0 18.0 andnps %xmm0, %xmm0 +# CHECK-NEXT: 52. 1 5.0 5.0 16.0 andnpd %xmm1, %xmm1 +# CHECK-NEXT: 53. 1 7.0 5.0 14.0 vandnps %xmm2, %xmm2, %xmm2 +# CHECK-NEXT: 54. 1 6.0 0.0 15.0 vandnpd %xmm1, %xmm1, %xmm1 +# CHECK-NEXT: 55. 1 22.0 0.0 0.0 pandn %mm2, %mm2 +# CHECK-NEXT: 56. 1 7.0 0.0 14.0 pandn %xmm2, %xmm2 +# CHECK-NEXT: 57. 1 3.0 0.0 18.0 vpandn %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 58. 1 8.0 0.0 13.0 vandnps %xmm2, %xmm2, %xmm5 +# CHECK-NEXT: 59. 1 7.0 1.0 14.0 vandnpd %xmm1, %xmm1, %xmm5 +# CHECK-NEXT: 60. 1 3.0 0.0 17.0 vpandn %xmm3, %xmm3, %xmm5 +# CHECK-NEXT: 61. 1 2.0 0.0 19.0 xorps %xmm0, %xmm0 +# CHECK-NEXT: 62. 1 5.0 0.0 16.0 xorpd %xmm1, %xmm1 +# CHECK-NEXT: 63. 1 7.0 0.0 14.0 vxorps %xmm2, %xmm2, %xmm2 +# CHECK-NEXT: 64. 1 4.0 0.0 16.0 vxorpd %xmm1, %xmm1, %xmm1 +# CHECK-NEXT: 65. 1 20.0 0.0 0.0 pxor %mm2, %mm2 +# CHECK-NEXT: 66. 1 6.0 0.0 15.0 pxor %xmm2, %xmm2 +# CHECK-NEXT: 67. 1 2.0 0.0 19.0 vpxor %xmm3, %xmm3, %xmm3 +# CHECK-NEXT: 68. 1 0.0 0.0 20.0 vxorps %xmm4, %xmm4, %xmm5 +# CHECK-NEXT: 69. 1 3.0 0.0 17.0 vxorpd %xmm1, %xmm1, %xmm3 +# CHECK-NEXT: 70. 1 3.0 0.0 17.0 vpxor %xmm3, %xmm3, %xmm5 diff --git a/llvm/test/tools/llvm-mca/X86/bextr-read-after-ld.s b/llvm/test/tools/llvm-mca/X86/bextr-read-after-ld.s index 4e4e23231b9..c356fe7976b 100644 --- a/llvm/test/tools/llvm-mca/X86/bextr-read-after-ld.s +++ b/llvm/test/tools/llvm-mca/X86/bextr-read-after-ld.s @@ -2,6 +2,7 @@ # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -iterations=1 -timeline -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=HASWELL # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=broadwell -iterations=1 -timeline -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=BDWELL # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=skylake -iterations=1 -timeline -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=SKYLAKE +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -timeline -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=BDVER2 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -timeline -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=BTVER2 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1 -timeline -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=ZNVER1 @@ -11,6 +12,9 @@ bextrl %esi, (%rdi), %eax # ALL: Iterations: 1 # ALL-NEXT: Instructions: 2 +# BDVER2-NEXT: Total Cycles: 10 +# BDVER2-NEXT: Total uOps: 4 + # BDWELL-NEXT: Total Cycles: 10 # BDWELL-NEXT: Total uOps: 4 @@ -26,6 +30,11 @@ bextrl %esi, (%rdi), %eax # ZNVER1-NEXT: Total Cycles: 8 # ZNVER1-NEXT: Total uOps: 3 +# BDVER2: Dispatch Width: 4 +# BDVER2-NEXT: uOps Per Cycle: 0.40 +# BDVER2-NEXT: IPC: 0.20 +# BDVER2-NEXT: Block RThroughput: 1.0 + # BDWELL: Dispatch Width: 4 # BDWELL-NEXT: uOps Per Cycle: 0.40 # BDWELL-NEXT: IPC: 0.20 @@ -61,6 +70,9 @@ bextrl %esi, (%rdi), %eax # ALL: [1] [2] [3] [4] [5] [6] Instructions: +# BDVER2-NEXT: 1 1 0.33 addl %edi, %esi +# BDVER2-NEXT: 3 7 1.00 * bextrl %esi, (%rdi), %eax + # BDWELL-NEXT: 1 1 0.25 addl %edi, %esi # BDWELL-NEXT: 3 7 0.50 * bextrl %esi, (%rdi), %eax @@ -78,12 +90,16 @@ bextrl %esi, (%rdi), %eax # ALL: Timeline view: +# BDVER2-NEXT: Index 0123456789 # BDWELL-NEXT: Index 0123456789 # BTVER2-NEXT: Index 0123456 # HASWELL-NEXT: Index 0123456789 # SKYLAKE-NEXT: Index 0123456789 # ZNVER1-NEXT: Index 01234567 +# BDVER2: [0,0] DeER . . addl %edi, %esi +# BDVER2-NEXT: [0,1] DeeeeeeeER bextrl %esi, (%rdi), %eax + # BDWELL: [0,0] DeER . . addl %edi, %esi # BDWELL-NEXT: [0,1] DeeeeeeeER bextrl %esi, (%rdi), %eax diff --git a/llvm/test/tools/llvm-mca/X86/cpus.s b/llvm/test/tools/llvm-mca/X86/cpus.s index 47e1e83c543..e666307d1a0 100644 --- a/llvm/test/tools/llvm-mca/X86/cpus.s +++ b/llvm/test/tools/llvm-mca/X86/cpus.s @@ -1,4 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -resource-pressure=false -instruction-info=false < %s | FileCheck --check-prefix=ALL --check-prefix=BDVER2 %s # RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=btver2 -resource-pressure=false -instruction-info=false < %s | FileCheck --check-prefix=ALL --check-prefix=BTVER2 %s # RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=znver1 -resource-pressure=false -instruction-info=false < %s | FileCheck --check-prefix=ALL --check-prefix=ZNVER1 %s # RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=sandybridge -resource-pressure=false -instruction-info=false < %s | FileCheck --check-prefix=ALL --check-prefix=SANDYBRIDGE %s @@ -17,6 +18,11 @@ add %edi, %eax # ALL-NEXT: Total Cycles: 103 # ALL-NEXT: Total uOps: 100 +# BDVER2: Dispatch Width: 4 +# BDVER2-NEXT: uOps Per Cycle: 0.97 +# BDVER2-NEXT: IPC: 0.97 +# BDVER2-NEXT: Block RThroughput: 0.3 + # BROADWELL: Dispatch Width: 4 # BROADWELL-NEXT: uOps Per Cycle: 0.97 # BROADWELL-NEXT: IPC: 0.97 diff --git a/llvm/test/tools/llvm-mca/X86/read-after-ld-1.s b/llvm/test/tools/llvm-mca/X86/read-after-ld-1.s index 1478eba77de..6c68ad13116 100644 --- a/llvm/test/tools/llvm-mca/X86/read-after-ld-1.s +++ b/llvm/test/tools/llvm-mca/X86/read-after-ld-1.s @@ -3,6 +3,7 @@ # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=HASWELL # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=broadwell -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=BDWELL # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=skylake -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=SKYLAKE +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=BDVER2 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=BTVER2 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=ZNVER1 @@ -12,6 +13,9 @@ vaddps (%rax), %xmm1, %xmm1 # ALL: Iterations: 1 # ALL-NEXT: Instructions: 2 +# BDVER2-NEXT: Total Cycles: 20 +# BDVER2-NEXT: Total uOps: 3 + # BDWELL-NEXT: Total Cycles: 17 # BDWELL-NEXT: Total uOps: 3 @@ -30,6 +34,11 @@ vaddps (%rax), %xmm1, %xmm1 # ZNVER1-NEXT: Total Cycles: 20 # ZNVER1-NEXT: Total uOps: 2 +# BDVER2: Dispatch Width: 4 +# BDVER2-NEXT: uOps Per Cycle: 0.15 +# BDVER2-NEXT: IPC: 0.10 +# BDVER2-NEXT: Block RThroughput: 14.0 + # BDWELL: Dispatch Width: 4 # BDWELL-NEXT: uOps Per Cycle: 0.18 # BDWELL-NEXT: IPC: 0.12 @@ -62,6 +71,9 @@ vaddps (%rax), %xmm1, %xmm1 # ALL: Timeline view: +# BDVER2-NEXT: 0123456789 +# BDVER2-NEXT: Index 0123456789 + # BDWELL-NEXT: 0123456 # BDWELL-NEXT: Index 0123456789 @@ -80,6 +92,9 @@ vaddps (%rax), %xmm1, %xmm1 # ZNVER1-NEXT: 0123456789 # ZNVER1-NEXT: Index 0123456789 +# BDVER2: [0,0] DeeeeeeeeeeeeeeER . vdivps %xmm0, %xmm1, %xmm1 +# BDVER2-NEXT: [0,1] D========eeeeeeeeeER vaddps (%rax), %xmm1, %xmm1 + # BDWELL: [0,0] DeeeeeeeeeeeER .. vdivps %xmm0, %xmm1, %xmm1 # BDWELL-NEXT: [0,1] D======eeeeeeeeER vaddps (%rax), %xmm1, %xmm1 @@ -107,6 +122,7 @@ vaddps (%rax), %xmm1, %xmm1 # ALL: [0] [1] [2] [3] # ALL-NEXT: 0. 1 1.0 1.0 0.0 vdivps %xmm0, %xmm1, %xmm1 +# BDVER2-NEXT: 1. 1 9.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1 # BDWELL-NEXT: 1. 1 7.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1 # BTVER2-NEXT: 1. 1 15.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1 # HASWELL-NEXT: 1. 1 8.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1 diff --git a/llvm/test/tools/llvm-mca/X86/register-file-statistics.s b/llvm/test/tools/llvm-mca/X86/register-file-statistics.s index e605ea94f4a..914eeaa82dd 100644 --- a/llvm/test/tools/llvm-mca/X86/register-file-statistics.s +++ b/llvm/test/tools/llvm-mca/X86/register-file-statistics.s @@ -1,4 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -all-stats=false -all-views=false -register-file-stats < %s | FileCheck --check-prefixes=ALL %s # RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -all-stats=false -all-views=false -register-file-stats < %s | FileCheck --check-prefixes=ALL,BTVER2 %s # RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1 -all-stats=false -all-views=false -register-file-stats < %s | FileCheck --check-prefixes=ALL,ZNVER1 %s # RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=sandybridge -iterations=1 -all-stats=false -all-views=false -register-file-stats < %s | FileCheck --check-prefixes=ALL %s diff --git a/llvm/test/tools/llvm-mca/X86/scheduler-queue-usage.s b/llvm/test/tools/llvm-mca/X86/scheduler-queue-usage.s index e22f4a51887..d99a76bf833 100644 --- a/llvm/test/tools/llvm-mca/X86/scheduler-queue-usage.s +++ b/llvm/test/tools/llvm-mca/X86/scheduler-queue-usage.s @@ -1,4 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,BDVER2 %s # RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,BTVER2 %s # RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,ZNVER1 %s # RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=sandybridge -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,SNB %s @@ -17,6 +18,12 @@ xor %eax, %ebx # ALL-NEXT: 0, 3 (75.0%) # ALL-NEXT: 1, 1 (25.0%) +# BDVER2: Scheduler's queue usage: +# BDVER2-NEXT: [1] Resource name. +# BDVER2-NEXT: [2] Average number of used buffer entries. +# BDVER2-NEXT: [3] Maximum number of used buffer entries. +# BDVER2-NEXT: [4] Total number of buffer entries. + # BDW: Scheduler's queue usage: # BDW-NEXT: [1] Resource name. # BDW-NEXT: [2] Average number of used buffer entries. @@ -74,6 +81,9 @@ xor %eax, %ebx # ZNVER1-NEXT: [3] Maximum number of used buffer entries. # ZNVER1-NEXT: [4] Total number of buffer entries. +# BDVER2: [1] [2] [3] [4] +# BDVER2-NEXT: SBPortAny 0 1 54 + # BDW: [1] [2] [3] [4] # BDW-NEXT: BWPortAny 0 1 60 diff --git a/llvm/test/tools/llvm-mca/X86/sqrt-rsqrt-rcp-memop.s b/llvm/test/tools/llvm-mca/X86/sqrt-rsqrt-rcp-memop.s index 66b87e72df2..e4531c990f0 100644 --- a/llvm/test/tools/llvm-mca/X86/sqrt-rsqrt-rcp-memop.s +++ b/llvm/test/tools/llvm-mca/X86/sqrt-rsqrt-rcp-memop.s @@ -1,4 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# ZZZ: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -all-views=false -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=BDVER2 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -all-views=false -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=BTVER2 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1 -all-views=false -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=ZNVER1 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -iterations=1 -all-views=false -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=HASWELL diff --git a/llvm/test/tools/llvm-mca/X86/variable-blend-read-after-ld-1.s b/llvm/test/tools/llvm-mca/X86/variable-blend-read-after-ld-1.s index 3a2f4d260f2..c2e28922e3a 100644 --- a/llvm/test/tools/llvm-mca/X86/variable-blend-read-after-ld-1.s +++ b/llvm/test/tools/llvm-mca/X86/variable-blend-read-after-ld-1.s @@ -9,6 +9,8 @@ # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=skylake -iterations=1 -timeline -instruction-info=false -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=SKYLAKE +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -timeline -instruction-info=false -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=BDVER2 + # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -timeline -instruction-info=false -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=BTVER2 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1 -timeline -instruction-info=false -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=ZNVER1 @@ -19,6 +21,9 @@ vblendvps %xmm1, (%rdi), %xmm2, %xmm3 # ALL: Iterations: 1 # ALL-NEXT: Instructions: 2 +# BDVER2-NEXT: Total Cycles: 11 +# BDVER2-NEXT: Total uOps: 4 + # BDWELL-NEXT: Total Cycles: 10 # BDWELL-NEXT: Total uOps: 4 @@ -40,6 +45,11 @@ vblendvps %xmm1, (%rdi), %xmm2, %xmm3 # ZNVER1-NEXT: Total Cycles: 11 # ZNVER1-NEXT: Total uOps: 2 +# BDVER2: Dispatch Width: 4 +# BDVER2-NEXT: uOps Per Cycle: 0.36 +# BDVER2-NEXT: IPC: 0.18 +# BDVER2-NEXT: Block RThroughput: 1.0 + # BDWELL: Dispatch Width: 4 # BDWELL-NEXT: uOps Per Cycle: 0.40 # BDWELL-NEXT: IPC: 0.20 @@ -75,6 +85,10 @@ vblendvps %xmm1, (%rdi), %xmm2, %xmm3 # ZNVER1-NEXT: IPC: 0.18 # ZNVER1-NEXT: Block RThroughput: 1.0 +# BDVER2: Timeline view: +# BDVER2-NEXT: 0 +# BDVER2-NEXT: Index 0123456789 + # BDWELL: Timeline view: # BDWELL-NEXT: Index 0123456789 @@ -102,6 +116,9 @@ vblendvps %xmm1, (%rdi), %xmm2, %xmm3 # ZNVER1-NEXT: 0 # ZNVER1-NEXT: Index 0123456789 +# BDVER2: [0,0] DeeeER . vaddps %xmm0, %xmm0, %xmm1 +# BDVER2-NEXT: [0,1] DeeeeeeeeER vblendvps %xmm1, (%rdi), %xmm2, %xmm3 + # BDWELL: [0,0] DeeeER . vaddps %xmm0, %xmm0, %xmm1 # BDWELL-NEXT: [0,1] DeeeeeeeER vblendvps %xmm1, (%rdi), %xmm2, %xmm3 @@ -132,6 +149,7 @@ vblendvps %xmm1, (%rdi), %xmm2, %xmm3 # ALL: [0] [1] [2] [3] # ALL-NEXT: 0. 1 1.0 1.0 0.0 vaddps %xmm0, %xmm0, %xmm1 +# BDVER2-NEXT: 1. 1 1.0 0.0 0.0 vblendvps %xmm1, (%rdi), %xmm2, %xmm3 # BDWELL-NEXT: 1. 1 1.0 0.0 0.0 vblendvps %xmm1, (%rdi), %xmm2, %xmm3 # BTVER2-NEXT: 1. 1 1.0 1.0 0.0 vblendvps %xmm1, (%rdi), %xmm2, %xmm3 # HASWELL-NEXT: 1. 1 1.0 0.0 0.0 vblendvps %xmm1, (%rdi), %xmm2, %xmm3 diff --git a/llvm/test/tools/llvm-mca/X86/variable-blend-read-after-ld-2.s b/llvm/test/tools/llvm-mca/X86/variable-blend-read-after-ld-2.s index fd581e0debf..0aa71425e94 100644 --- a/llvm/test/tools/llvm-mca/X86/variable-blend-read-after-ld-2.s +++ b/llvm/test/tools/llvm-mca/X86/variable-blend-read-after-ld-2.s @@ -9,6 +9,8 @@ # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=skylake -iterations=1 -timeline -instruction-info=false -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=SKYLAKE +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -timeline -instruction-info=false -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=BDVER2 + # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -timeline -instruction-info=false -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=BTVER2 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1 -timeline -instruction-info=false -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=ZNVER1 @@ -19,6 +21,9 @@ vblendvps %xmm1, (%rdi), %xmm2, %xmm3 # ALL: Iterations: 1 # ALL-NEXT: Instructions: 2 +# BDVER2-NEXT: Total Cycles: 11 +# BDVER2-NEXT: Total uOps: 4 + # BDWELL-NEXT: Total Cycles: 10 # BDWELL-NEXT: Total uOps: 4 @@ -40,6 +45,11 @@ vblendvps %xmm1, (%rdi), %xmm2, %xmm3 # ZNVER1-NEXT: Total Cycles: 11 # ZNVER1-NEXT: Total uOps: 2 +# BDVER2: Dispatch Width: 4 +# BDVER2-NEXT: uOps Per Cycle: 0.36 +# BDVER2-NEXT: IPC: 0.18 +# BDVER2-NEXT: Block RThroughput: 1.0 + # BDWELL: Dispatch Width: 4 # BDWELL-NEXT: uOps Per Cycle: 0.40 # BDWELL-NEXT: IPC: 0.20 @@ -75,6 +85,10 @@ vblendvps %xmm1, (%rdi), %xmm2, %xmm3 # ZNVER1-NEXT: IPC: 0.18 # ZNVER1-NEXT: Block RThroughput: 1.0 +# BDVER2: Timeline view: +# BDVER2-NEXT: 0 +# BDVER2-NEXT: Index 0123456789 + # BDWELL: Timeline view: # BDWELL-NEXT: Index 0123456789 @@ -102,6 +116,9 @@ vblendvps %xmm1, (%rdi), %xmm2, %xmm3 # ZNVER1-NEXT: 0 # ZNVER1-NEXT: Index 0123456789 +# BDVER2: [0,0] DeeeER . vaddps %xmm0, %xmm0, %xmm2 +# BDVER2-NEXT: [0,1] DeeeeeeeeER vblendvps %xmm1, (%rdi), %xmm2, %xmm3 + # BDWELL: [0,0] DeeeER . vaddps %xmm0, %xmm0, %xmm2 # BDWELL-NEXT: [0,1] DeeeeeeeER vblendvps %xmm1, (%rdi), %xmm2, %xmm3 @@ -132,6 +149,7 @@ vblendvps %xmm1, (%rdi), %xmm2, %xmm3 # ALL: [0] [1] [2] [3] # ALL-NEXT: 0. 1 1.0 1.0 0.0 vaddps %xmm0, %xmm0, %xmm2 +# BDVER2-NEXT: 1. 1 1.0 0.0 0.0 vblendvps %xmm1, (%rdi), %xmm2, %xmm3 # BDWELL-NEXT: 1. 1 1.0 0.0 0.0 vblendvps %xmm1, (%rdi), %xmm2, %xmm3 # BTVER2-NEXT: 1. 1 1.0 1.0 0.0 vblendvps %xmm1, (%rdi), %xmm2, %xmm3 # HASWELL-NEXT: 1. 1 1.0 0.0 0.0 vblendvps %xmm1, (%rdi), %xmm2, %xmm3 |
