diff options
Diffstat (limited to 'llvm/test/tools/llvm-mca')
3 files changed, 48 insertions, 8 deletions
diff --git a/llvm/test/tools/llvm-mca/AArch64/CortexA57/shifted-register.s b/llvm/test/tools/llvm-mca/AArch64/CortexA57/shifted-register.s index 4c0f580036e..b904e383485 100644 --- a/llvm/test/tools/llvm-mca/AArch64/CortexA57/shifted-register.s +++ b/llvm/test/tools/llvm-mca/AArch64/CortexA57/shifted-register.s @@ -1,7 +1,25 @@ -# RUN: not llvm-mca -march=aarch64 -mcpu=cortex-a57 -resource-pressure=false < %s 2> %t -# RUN: FileCheck --input-file %t %s +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -march=aarch64 -mcpu=cortex-a57 -resource-pressure=false < %s | FileCheck %s add x0, x1, x2, lsl #3 -# CHECK: error -# CHECK-SAME: unable to resolve scheduling class for write variant. +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 100 +# CHECK-NEXT: Total Cycles: 53 +# CHECK-NEXT: Total uOps: 100 + +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 1.89 +# CHECK-NEXT: IPC: 1.89 +# CHECK-NEXT: Block RThroughput: 0.5 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 0.50 add x0, x1, x2, lsl #3 diff --git a/llvm/test/tools/llvm-mca/AArch64/Cyclone/register-offset.s b/llvm/test/tools/llvm-mca/AArch64/Cyclone/register-offset.s index 1a6455cff07..16a6f3e1de7 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Cyclone/register-offset.s +++ b/llvm/test/tools/llvm-mca/AArch64/Cyclone/register-offset.s @@ -1,9 +1,29 @@ -# RUN: not llvm-mca -march=aarch64 -mcpu=cyclone -resource-pressure=false < %s 2> %t -# RUN: FileCheck --input-file %t %s +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -march=aarch64 -mcpu=cyclone -resource-pressure=false < %s | FileCheck %s ldr x7, [x1, #8] ldr x6, [x1, x2] ldr x4, [x1, x2, sxtx] -# CHECK: error -# CHECK-SAME: unable to resolve scheduling class for write variant. +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 300 +# CHECK-NEXT: Total Cycles: 156 +# CHECK-NEXT: Total uOps: 300 + +# CHECK: Dispatch Width: 6 +# CHECK-NEXT: uOps Per Cycle: 1.92 +# CHECK-NEXT: IPC: 1.92 +# CHECK-NEXT: Block RThroughput: 1.5 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 4 0.50 * ldr x7, [x1, #8] +# CHECK-NEXT: 1 4 0.50 * ldr x6, [x1, x2] +# CHECK-NEXT: 1 4 0.50 * ldr x4, [x1, x2, sxtx] diff --git a/llvm/test/tools/llvm-mca/ARM/unsupported-write-variant.s b/llvm/test/tools/llvm-mca/ARM/unsupported-write-variant.s index f4511f54ab5..6f95a017670 100644 --- a/llvm/test/tools/llvm-mca/ARM/unsupported-write-variant.s +++ b/llvm/test/tools/llvm-mca/ARM/unsupported-write-variant.s @@ -1,4 +1,6 @@ # RUN: not llvm-mca -march=arm -mcpu=swift -all-views=false 2>&1 < %s | FileCheck %s +# D54648 results in this test to become valid. +# XFAIL: * add r3, r1, r12, lsl #2 |
