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-rw-r--r--llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt2
-rw-r--r--llvm/test/MC/Disassembler/Hexagon/alu32_pred.txt4
2 files changed, 6 insertions, 0 deletions
diff --git a/llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt b/llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt
index 2f1d1b65067..d8952102ec7 100644
--- a/llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt
+++ b/llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt
@@ -10,6 +10,8 @@
# CHECK: r17 = combine(r31.l, r21.l)
0xb0 0xe2 0x0f 0x7c
# CHECK: r17:16 = combine(#21, #31)
+0x10 0xdf 0x15 0xf5
+# CHECK: r17:16 = combine(r21, r31)
0xf1 0xc3 0x75 0x73
# CHECK: r17 = mux(p3, r21, #31)
0xb1 0xc2 0xff 0x73
diff --git a/llvm/test/MC/Disassembler/Hexagon/alu32_pred.txt b/llvm/test/MC/Disassembler/Hexagon/alu32_pred.txt
index c85b86b5135..c17bd0fdeb9 100644
--- a/llvm/test/MC/Disassembler/Hexagon/alu32_pred.txt
+++ b/llvm/test/MC/Disassembler/Hexagon/alu32_pred.txt
@@ -6,6 +6,10 @@
# CHECK: if (p3) r17 = aslh(r21)
0x11 0xe3 0x35 0x70
# CHECK: if (p3) r17 = asrh(r21)
+0x70 0xdf 0x15 0xfd
+# CHECK: if (p3) r17:16 = combine(r21, r31)
+0xf0 0xdf 0x15 0xfd
+# CHECK: if (!p3) r17:16 = combine(r21, r31)
0x71 0xdf 0x15 0xf9
# CHECK: if (p3) r17 = and(r21, r31)
0x71 0xdf 0x35 0xf9
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