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-rw-r--r--llvm/test/CodeGen/RISCV/addc-adde-sube-subc.ll4
-rw-r--r--llvm/test/CodeGen/RISCV/alu32.ll38
-rw-r--r--llvm/test/CodeGen/RISCV/bare-select.ll4
-rw-r--r--llvm/test/CodeGen/RISCV/blockaddress.ll2
-rw-r--r--llvm/test/CodeGen/RISCV/branch.ll2
-rw-r--r--llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll30
-rw-r--r--llvm/test/CodeGen/RISCV/calls.ll12
-rw-r--r--llvm/test/CodeGen/RISCV/div.ll20
-rw-r--r--llvm/test/CodeGen/RISCV/i32-icmp.ll20
-rw-r--r--llvm/test/CodeGen/RISCV/imm.ll10
-rw-r--r--llvm/test/CodeGen/RISCV/indirectbr.ll4
-rw-r--r--llvm/test/CodeGen/RISCV/jumptable.ll2
-rw-r--r--llvm/test/CodeGen/RISCV/mem.ll24
-rw-r--r--llvm/test/CodeGen/RISCV/mul.ll12
-rw-r--r--llvm/test/CodeGen/RISCV/rem.ll4
-rw-r--r--llvm/test/CodeGen/RISCV/rotl-rotr.ll4
-rw-r--r--llvm/test/CodeGen/RISCV/select-cc.ll22
-rw-r--r--llvm/test/CodeGen/RISCV/sext-zext-trunc.ll60
-rw-r--r--llvm/test/CodeGen/RISCV/shifts.ll6
-rw-r--r--llvm/test/CodeGen/RISCV/wide-mem.ll4
20 files changed, 142 insertions, 142 deletions
diff --git a/llvm/test/CodeGen/RISCV/addc-adde-sube-subc.ll b/llvm/test/CodeGen/RISCV/addc-adde-sube-subc.ll
index 50de47d7c1f..54f5482b9e7 100644
--- a/llvm/test/CodeGen/RISCV/addc-adde-sube-subc.ll
+++ b/llvm/test/CodeGen/RISCV/addc-adde-sube-subc.ll
@@ -6,7 +6,7 @@
define i64 @addc_adde(i64 %a, i64 %b) {
; RV32I-LABEL: addc_adde:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: add a1, a1, a3
; RV32I-NEXT: add a2, a0, a2
; RV32I-NEXT: sltu a0, a2, a0
@@ -19,7 +19,7 @@ define i64 @addc_adde(i64 %a, i64 %b) {
define i64 @subc_sube(i64 %a, i64 %b) {
; RV32I-LABEL: subc_sube:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sub a1, a1, a3
; RV32I-NEXT: sltu a3, a0, a2
; RV32I-NEXT: sub a1, a1, a3
diff --git a/llvm/test/CodeGen/RISCV/alu32.ll b/llvm/test/CodeGen/RISCV/alu32.ll
index 9aa6058c2a0..e7c82181027 100644
--- a/llvm/test/CodeGen/RISCV/alu32.ll
+++ b/llvm/test/CodeGen/RISCV/alu32.ll
@@ -10,7 +10,7 @@
define i32 @addi(i32 %a) nounwind {
; RV32I-LABEL: addi:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: addi a0, a0, 1
; RV32I-NEXT: jalr zero, ra, 0
%1 = add i32 %a, 1
@@ -19,7 +19,7 @@ define i32 @addi(i32 %a) nounwind {
define i32 @slti(i32 %a) nounwind {
; RV32I-LABEL: slti:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: slti a0, a0, 2
; RV32I-NEXT: jalr zero, ra, 0
%1 = icmp slt i32 %a, 2
@@ -29,7 +29,7 @@ define i32 @slti(i32 %a) nounwind {
define i32 @sltiu(i32 %a) nounwind {
; RV32I-LABEL: sltiu:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sltiu a0, a0, 3
; RV32I-NEXT: jalr zero, ra, 0
%1 = icmp ult i32 %a, 3
@@ -39,7 +39,7 @@ define i32 @sltiu(i32 %a) nounwind {
define i32 @xori(i32 %a) nounwind {
; RV32I-LABEL: xori:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: xori a0, a0, 4
; RV32I-NEXT: jalr zero, ra, 0
%1 = xor i32 %a, 4
@@ -48,7 +48,7 @@ define i32 @xori(i32 %a) nounwind {
define i32 @ori(i32 %a) nounwind {
; RV32I-LABEL: ori:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: ori a0, a0, 5
; RV32I-NEXT: jalr zero, ra, 0
%1 = or i32 %a, 5
@@ -57,7 +57,7 @@ define i32 @ori(i32 %a) nounwind {
define i32 @andi(i32 %a) nounwind {
; RV32I-LABEL: andi:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 6
; RV32I-NEXT: jalr zero, ra, 0
%1 = and i32 %a, 6
@@ -66,7 +66,7 @@ define i32 @andi(i32 %a) nounwind {
define i32 @slli(i32 %a) nounwind {
; RV32I-LABEL: slli:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 7
; RV32I-NEXT: jalr zero, ra, 0
%1 = shl i32 %a, 7
@@ -75,7 +75,7 @@ define i32 @slli(i32 %a) nounwind {
define i32 @srli(i32 %a) nounwind {
; RV32I-LABEL: srli:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: srli a0, a0, 8
; RV32I-NEXT: jalr zero, ra, 0
%1 = lshr i32 %a, 8
@@ -84,7 +84,7 @@ define i32 @srli(i32 %a) nounwind {
define i32 @srai(i32 %a) nounwind {
; RV32I-LABEL: srai:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: srai a0, a0, 9
; RV32I-NEXT: jalr zero, ra, 0
%1 = ashr i32 %a, 9
@@ -95,7 +95,7 @@ define i32 @srai(i32 %a) nounwind {
define i32 @add(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: add:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: jalr zero, ra, 0
%1 = add i32 %a, %b
@@ -104,7 +104,7 @@ define i32 @add(i32 %a, i32 %b) nounwind {
define i32 @sub(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sub:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: jalr zero, ra, 0
%1 = sub i32 %a, %b
@@ -113,7 +113,7 @@ define i32 @sub(i32 %a, i32 %b) nounwind {
define i32 @sll(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sll:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sll a0, a0, a1
; RV32I-NEXT: jalr zero, ra, 0
%1 = shl i32 %a, %b
@@ -122,7 +122,7 @@ define i32 @sll(i32 %a, i32 %b) nounwind {
define i32 @slt(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: slt:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: slt a0, a0, a1
; RV32I-NEXT: jalr zero, ra, 0
%1 = icmp slt i32 %a, %b
@@ -132,7 +132,7 @@ define i32 @slt(i32 %a, i32 %b) nounwind {
define i32 @sltu(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sltu:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sltu a0, a0, a1
; RV32I-NEXT: jalr zero, ra, 0
%1 = icmp ult i32 %a, %b
@@ -142,7 +142,7 @@ define i32 @sltu(i32 %a, i32 %b) nounwind {
define i32 @xor(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: xor:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: jalr zero, ra, 0
%1 = xor i32 %a, %b
@@ -151,7 +151,7 @@ define i32 @xor(i32 %a, i32 %b) nounwind {
define i32 @srl(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: srl:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: srl a0, a0, a1
; RV32I-NEXT: jalr zero, ra, 0
%1 = lshr i32 %a, %b
@@ -160,7 +160,7 @@ define i32 @srl(i32 %a, i32 %b) nounwind {
define i32 @sra(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sra:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sra a0, a0, a1
; RV32I-NEXT: jalr zero, ra, 0
%1 = ashr i32 %a, %b
@@ -169,7 +169,7 @@ define i32 @sra(i32 %a, i32 %b) nounwind {
define i32 @or(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: or:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: jalr zero, ra, 0
%1 = or i32 %a, %b
@@ -178,7 +178,7 @@ define i32 @or(i32 %a, i32 %b) nounwind {
define i32 @and(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: and:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: jalr zero, ra, 0
%1 = and i32 %a, %b
diff --git a/llvm/test/CodeGen/RISCV/bare-select.ll b/llvm/test/CodeGen/RISCV/bare-select.ll
index ec98b6d18b2..a46afe27143 100644
--- a/llvm/test/CodeGen/RISCV/bare-select.ll
+++ b/llvm/test/CodeGen/RISCV/bare-select.ll
@@ -4,10 +4,10 @@
define i32 @bare_select(i1 %a, i32 %b, i32 %c) {
; RV32I-LABEL: bare_select:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: bne a0, zero, .LBB0_2
-; RV32I-NEXT: # BB#1:
+; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: addi a1, a2, 0
; RV32I-NEXT: .LBB0_2:
; RV32I-NEXT: addi a0, a1, 0
diff --git a/llvm/test/CodeGen/RISCV/blockaddress.ll b/llvm/test/CodeGen/RISCV/blockaddress.ll
index f51598ff5a7..9eb4e3d404d 100644
--- a/llvm/test/CodeGen/RISCV/blockaddress.ll
+++ b/llvm/test/CodeGen/RISCV/blockaddress.ll
@@ -6,7 +6,7 @@
define void @test_blockaddress() nounwind {
; RV32I-LABEL: test_blockaddress:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw ra, 0(s0)
; RV32I-NEXT: lui a0, %hi(addr)
; RV32I-NEXT: addi a0, a0, %lo(addr)
diff --git a/llvm/test/CodeGen/RISCV/branch.ll b/llvm/test/CodeGen/RISCV/branch.ll
index 194083b07c7..e2593d3309b 100644
--- a/llvm/test/CodeGen/RISCV/branch.ll
+++ b/llvm/test/CodeGen/RISCV/branch.ll
@@ -4,7 +4,7 @@
define void @foo(i32 %a, i32 *%b, i1 %c) {
; RV32I-LABEL: foo:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: beq a3, a0, .LBB0_12
; RV32I-NEXT: jal zero, .LBB0_1
diff --git a/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll b/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
index 6521f66cf6a..150dfed3573 100644
--- a/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
+++ b/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
@@ -14,7 +14,7 @@ declare i32 @llvm.ctpop.i32(i32)
define i16 @test_bswap_i16(i16 %a) nounwind {
; RV32I-LABEL: test_bswap_i16:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 4080
; RV32I-NEXT: addi a1, a1, 0
; RV32I-NEXT: slli a2, a0, 8
@@ -29,7 +29,7 @@ define i16 @test_bswap_i16(i16 %a) nounwind {
define i32 @test_bswap_i32(i32 %a) nounwind {
; RV32I-LABEL: test_bswap_i32:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -256
; RV32I-NEXT: srli a2, a0, 8
@@ -50,7 +50,7 @@ define i32 @test_bswap_i32(i32 %a) nounwind {
define i64 @test_bswap_i64(i64 %a) nounwind {
; RV32I-LABEL: test_bswap_i64:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: addi a3, a2, -256
; RV32I-NEXT: srli a2, a1, 8
@@ -81,7 +81,7 @@ define i64 @test_bswap_i64(i64 %a) nounwind {
define i8 @test_cttz_i8(i8 %a) nounwind {
; RV32I-LABEL: test_cttz_i8:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw ra, 12(s0)
; RV32I-NEXT: addi a1, a0, 0
; RV32I-NEXT: addi a0, zero, 8
@@ -123,7 +123,7 @@ define i8 @test_cttz_i8(i8 %a) nounwind {
define i16 @test_cttz_i16(i16 %a) nounwind {
; RV32I-LABEL: test_cttz_i16:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw ra, 12(s0)
; RV32I-NEXT: addi a1, a0, 0
; RV32I-NEXT: addi a0, zero, 16
@@ -167,7 +167,7 @@ define i16 @test_cttz_i16(i16 %a) nounwind {
define i32 @test_cttz_i32(i32 %a) nounwind {
; RV32I-LABEL: test_cttz_i32:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw ra, 12(s0)
; RV32I-NEXT: addi a1, a0, 0
; RV32I-NEXT: addi a0, zero, 32
@@ -208,7 +208,7 @@ define i32 @test_cttz_i32(i32 %a) nounwind {
define i32 @test_ctlz_i32(i32 %a) nounwind {
; RV32I-LABEL: test_ctlz_i32:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw ra, 12(s0)
; RV32I-NEXT: addi a1, a0, 0
; RV32I-NEXT: addi a0, zero, 32
@@ -257,7 +257,7 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
define i64 @test_cttz_i64(i64 %a) nounwind {
; RV32I-LABEL: test_cttz_i64:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw ra, 28(s0)
; RV32I-NEXT: sw s1, 24(s0)
; RV32I-NEXT: sw s2, 20(s0)
@@ -311,7 +311,7 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
; RV32I-NEXT: addi a1, s3, 0
; RV32I-NEXT: jalr ra, s6, 0
; RV32I-NEXT: bne s2, zero, .LBB7_2
-; RV32I-NEXT: # BB#1:
+; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: addi s1, a0, 32
; RV32I-NEXT: .LBB7_2:
@@ -332,7 +332,7 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
define i8 @test_cttz_i8_zero_undef(i8 %a) nounwind {
; RV32I-LABEL: test_cttz_i8_zero_undef:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw ra, 12(s0)
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: xori a0, a0, -1
@@ -367,7 +367,7 @@ define i8 @test_cttz_i8_zero_undef(i8 %a) nounwind {
define i16 @test_cttz_i16_zero_undef(i16 %a) nounwind {
; RV32I-LABEL: test_cttz_i16_zero_undef:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw ra, 12(s0)
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: xori a0, a0, -1
@@ -402,7 +402,7 @@ define i16 @test_cttz_i16_zero_undef(i16 %a) nounwind {
define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind {
; RV32I-LABEL: test_cttz_i32_zero_undef:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw ra, 12(s0)
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: xori a0, a0, -1
@@ -437,7 +437,7 @@ define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind {
define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
; RV32I-LABEL: test_cttz_i64_zero_undef:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw ra, 28(s0)
; RV32I-NEXT: sw s1, 24(s0)
; RV32I-NEXT: sw s2, 20(s0)
@@ -491,7 +491,7 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
; RV32I-NEXT: addi a1, s3, 0
; RV32I-NEXT: jalr ra, s6, 0
; RV32I-NEXT: bne s2, zero, .LBB11_2
-; RV32I-NEXT: # BB#1:
+; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: addi s1, a0, 32
; RV32I-NEXT: .LBB11_2:
@@ -512,7 +512,7 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
define i32 @test_ctpop_i32(i32 %a) nounwind {
; RV32I-LABEL: test_ctpop_i32:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw ra, 12(s0)
; RV32I-NEXT: lui a1, 349525
; RV32I-NEXT: addi a1, a1, 1365
diff --git a/llvm/test/CodeGen/RISCV/calls.ll b/llvm/test/CodeGen/RISCV/calls.ll
index 8abe5e92a8e..77f61290705 100644
--- a/llvm/test/CodeGen/RISCV/calls.ll
+++ b/llvm/test/CodeGen/RISCV/calls.ll
@@ -6,7 +6,7 @@ declare i32 @external_function(i32)
define i32 @test_call_external(i32 %a) nounwind {
; RV32I-LABEL: test_call_external:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw ra, 12(s0)
; RV32I-NEXT: lui a1, %hi(external_function)
; RV32I-NEXT: addi a1, a1, %lo(external_function)
@@ -19,7 +19,7 @@ define i32 @test_call_external(i32 %a) nounwind {
define i32 @defined_function(i32 %a) nounwind {
; RV32I-LABEL: defined_function:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: addi a0, a0, 1
; RV32I-NEXT: jalr zero, ra, 0
%1 = add i32 %a, 1
@@ -28,7 +28,7 @@ define i32 @defined_function(i32 %a) nounwind {
define i32 @test_call_defined(i32 %a) nounwind {
; RV32I-LABEL: test_call_defined:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw ra, 12(s0)
; RV32I-NEXT: lui a1, %hi(defined_function)
; RV32I-NEXT: addi a1, a1, %lo(defined_function)
@@ -41,7 +41,7 @@ define i32 @test_call_defined(i32 %a) nounwind {
define i32 @test_call_indirect(i32 (i32)* %a, i32 %b) nounwind {
; RV32I-LABEL: test_call_indirect:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw ra, 12(s0)
; RV32I-NEXT: addi a2, a0, 0
; RV32I-NEXT: addi a0, a1, 0
@@ -57,7 +57,7 @@ define i32 @test_call_indirect(i32 (i32)* %a, i32 %b) nounwind {
define fastcc i32 @fastcc_function(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: fastcc_function:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: jalr zero, ra, 0
%1 = add i32 %a, %b
@@ -66,7 +66,7 @@ define fastcc i32 @fastcc_function(i32 %a, i32 %b) nounwind {
define i32 @test_call_fastcc(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: test_call_fastcc:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw ra, 12(s0)
; RV32I-NEXT: sw s1, 8(s0)
; RV32I-NEXT: addi s1, a0, 0
diff --git a/llvm/test/CodeGen/RISCV/div.ll b/llvm/test/CodeGen/RISCV/div.ll
index 4c0f5de0358..a53c51c94d8 100644
--- a/llvm/test/CodeGen/RISCV/div.ll
+++ b/llvm/test/CodeGen/RISCV/div.ll
@@ -4,7 +4,7 @@
define i32 @udiv(i32 %a, i32 %b) {
; RV32I-LABEL: udiv:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw ra, 12(s0)
; RV32I-NEXT: lui a2, %hi(__udivsi3)
; RV32I-NEXT: addi a2, a2, %lo(__udivsi3)
@@ -17,7 +17,7 @@ define i32 @udiv(i32 %a, i32 %b) {
define i32 @udiv_constant(i32 %a) {
; RV32I-LABEL: udiv_constant:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw ra, 12(s0)
; RV32I-NEXT: lui a1, %hi(__udivsi3)
; RV32I-NEXT: addi a2, a1, %lo(__udivsi3)
@@ -31,7 +31,7 @@ define i32 @udiv_constant(i32 %a) {
define i32 @udiv_pow2(i32 %a) {
; RV32I-LABEL: udiv_pow2:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: srli a0, a0, 3
; RV32I-NEXT: jalr zero, ra, 0
%1 = udiv i32 %a, 8
@@ -40,7 +40,7 @@ define i32 @udiv_pow2(i32 %a) {
define i64 @udiv64(i64 %a, i64 %b) {
; RV32I-LABEL: udiv64:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw ra, 12(s0)
; RV32I-NEXT: lui a4, %hi(__udivdi3)
; RV32I-NEXT: addi a4, a4, %lo(__udivdi3)
@@ -53,7 +53,7 @@ define i64 @udiv64(i64 %a, i64 %b) {
define i64 @udiv64_constant(i64 %a) {
; RV32I-LABEL: udiv64_constant:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw ra, 12(s0)
; RV32I-NEXT: lui a2, %hi(__udivdi3)
; RV32I-NEXT: addi a4, a2, %lo(__udivdi3)
@@ -68,7 +68,7 @@ define i64 @udiv64_constant(i64 %a) {
define i32 @sdiv(i32 %a, i32 %b) {
; RV32I-LABEL: sdiv:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw ra, 12(s0)
; RV32I-NEXT: lui a2, %hi(__divsi3)
; RV32I-NEXT: addi a2, a2, %lo(__divsi3)
@@ -81,7 +81,7 @@ define i32 @sdiv(i32 %a, i32 %b) {
define i32 @sdiv_constant(i32 %a) {
; RV32I-LABEL: sdiv_constant:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw ra, 12(s0)
; RV32I-NEXT: lui a1, %hi(__divsi3)
; RV32I-NEXT: addi a2, a1, %lo(__divsi3)
@@ -95,7 +95,7 @@ define i32 @sdiv_constant(i32 %a) {
define i32 @sdiv_pow2(i32 %a) {
; RV32I-LABEL: sdiv_pow2:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: srai a1, a0, 31
; RV32I-NEXT: srli a1, a1, 29
; RV32I-NEXT: add a0, a0, a1
@@ -107,7 +107,7 @@ define i32 @sdiv_pow2(i32 %a) {
define i64 @sdiv64(i64 %a, i64 %b) {
; RV32I-LABEL: sdiv64:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw ra, 12(s0)
; RV32I-NEXT: lui a4, %hi(__divdi3)
; RV32I-NEXT: addi a4, a4, %lo(__divdi3)
@@ -120,7 +120,7 @@ define i64 @sdiv64(i64 %a, i64 %b) {
define i64 @sdiv64_constant(i64 %a) {
; RV32I-LABEL: sdiv64_constant:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw ra, 12(s0)
; RV32I-NEXT: lui a2, %hi(__divdi3)
; RV32I-NEXT: addi a4, a2, %lo(__divdi3)
diff --git a/llvm/test/CodeGen/RISCV/i32-icmp.ll b/llvm/test/CodeGen/RISCV/i32-icmp.ll
index 4d86ced2584..bc06ec805e9 100644
--- a/llvm/test/CodeGen/RISCV/i32-icmp.ll
+++ b/llvm/test/CodeGen/RISCV/i32-icmp.ll
@@ -7,7 +7,7 @@
define i32 @icmp_eq(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_eq:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: sltiu a0, a0, 1
; RV32I-NEXT: jalr zero, ra, 0
@@ -18,7 +18,7 @@ define i32 @icmp_eq(i32 %a, i32 %b) nounwind {
define i32 @icmp_ne(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_ne:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: sltu a0, zero, a0
; RV32I-NEXT: jalr zero, ra, 0
@@ -29,7 +29,7 @@ define i32 @icmp_ne(i32 %a, i32 %b) nounwind {
define i32 @icmp_ugt(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_ugt:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sltu a0, a1, a0
; RV32I-NEXT: jalr zero, ra, 0
%1 = icmp ugt i32 %a, %b
@@ -39,7 +39,7 @@ define i32 @icmp_ugt(i32 %a, i32 %b) nounwind {
define i32 @icmp_uge(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_uge:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sltu a0, a0, a1
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: jalr zero, ra, 0
@@ -50,7 +50,7 @@ define i32 @icmp_uge(i32 %a, i32 %b) nounwind {
define i32 @icmp_ult(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_ult:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sltu a0, a0, a1
; RV32I-NEXT: jalr zero, ra, 0
%1 = icmp ult i32 %a, %b
@@ -60,7 +60,7 @@ define i32 @icmp_ult(i32 %a, i32 %b) nounwind {
define i32 @icmp_ule(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_ule:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sltu a0, a1, a0
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: jalr zero, ra, 0
@@ -71,7 +71,7 @@ define i32 @icmp_ule(i32 %a, i32 %b) nounwind {
define i32 @icmp_sgt(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_sgt:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: slt a0, a1, a0
; RV32I-NEXT: jalr zero, ra, 0
%1 = icmp sgt i32 %a, %b
@@ -81,7 +81,7 @@ define i32 @icmp_sgt(i32 %a, i32 %b) nounwind {
define i32 @icmp_sge(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_sge:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: slt a0, a0, a1
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: jalr zero, ra, 0
@@ -92,7 +92,7 @@ define i32 @icmp_sge(i32 %a, i32 %b) nounwind {
define i32 @icmp_slt(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_slt:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: slt a0, a0, a1
; RV32I-NEXT: jalr zero, ra, 0
%1 = icmp slt i32 %a, %b
@@ -102,7 +102,7 @@ define i32 @icmp_slt(i32 %a, i32 %b) nounwind {
define i32 @icmp_sle(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_sle:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: slt a0, a1, a0
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: jalr zero, ra, 0
diff --git a/llvm/test/CodeGen/RISCV/imm.ll b/llvm/test/CodeGen/RISCV/imm.ll
index c52638da02e..ddefa22835a 100644
--- a/llvm/test/CodeGen/RISCV/imm.ll
+++ b/llvm/test/CodeGen/RISCV/imm.ll
@@ -6,7 +6,7 @@
define i32 @zero() nounwind {
; RV32I-LABEL: zero:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: addi a0, zero, 0
; RV32I-NEXT: jalr zero, ra, 0
ret i32 0
@@ -14,7 +14,7 @@ define i32 @zero() nounwind {
define i32 @pos_small() nounwind {
; RV32I-LABEL: pos_small:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: addi a0, zero, 2047
; RV32I-NEXT: jalr zero, ra, 0
ret i32 2047
@@ -22,7 +22,7 @@ define i32 @pos_small() nounwind {
define i32 @neg_small() nounwind {
; RV32I-LABEL: neg_small:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: addi a0, zero, -2048
; RV32I-NEXT: jalr zero, ra, 0
ret i32 -2048
@@ -30,7 +30,7 @@ define i32 @neg_small() nounwind {
define i32 @pos_i32() nounwind {
; RV32I-LABEL: pos_i32:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: lui a0, 423811
; RV32I-NEXT: addi a0, a0, -1297
; RV32I-NEXT: jalr zero, ra, 0
@@ -39,7 +39,7 @@ define i32 @pos_i32() nounwind {
define i32 @neg_i32() nounwind {
; RV32I-LABEL: neg_i32:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: lui a0, 912092
; RV32I-NEXT: addi a0, a0, -273
; RV32I-NEXT: jalr zero, ra, 0
diff --git a/llvm/test/CodeGen/RISCV/indirectbr.ll b/llvm/test/CodeGen/RISCV/indirectbr.ll
index 0a51e3d0b2e..40641da6d6f 100644
--- a/llvm/test/CodeGen/RISCV/indirectbr.ll
+++ b/llvm/test/CodeGen/RISCV/indirectbr.ll
@@ -4,7 +4,7 @@
define i32 @indirectbr(i8* %target) nounwind {
; RV32I-LABEL: indirectbr:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw ra, 0(s0)
; RV32I-NEXT: jalr zero, a0, 0
; RV32I-NEXT: .LBB0_1: # %ret
@@ -20,7 +20,7 @@ ret:
define i32 @indirectbr_with_offset(i8* %a) nounwind {
; RV32I-LABEL: indirectbr_with_offset:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw ra, 0(s0)
; RV32I-NEXT: jalr zero, a0, 1380
; RV32I-NEXT: .LBB1_1: # %ret
diff --git a/llvm/test/CodeGen/RISCV/jumptable.ll b/llvm/test/CodeGen/RISCV/jumptable.ll
index 98144c7c1e6..68f4f1cb721 100644
--- a/llvm/test/CodeGen/RISCV/jumptable.ll
+++ b/llvm/test/CodeGen/RISCV/jumptable.ll
@@ -4,7 +4,7 @@
define void @jt(i32 %in, i32* %out) {
; RV32I-LABEL: jt:
-; RV32I: # BB#0: # %entry
+; RV32I: # %bb.0: # %entry
; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: blt a2, a0, .LBB0_3
; RV32I-NEXT: jal zero, .LBB0_1
diff --git a/llvm/test/CodeGen/RISCV/mem.ll b/llvm/test/CodeGen/RISCV/mem.ll
index b06382f8742..6446034e542 100644
--- a/llvm/test/CodeGen/RISCV/mem.ll
+++ b/llvm/test/CodeGen/RISCV/mem.ll
@@ -6,7 +6,7 @@
define i32 @lb(i8 *%a) nounwind {
; RV32I-LABEL: lb:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: lb a1, 0(a0)
; RV32I-NEXT: lb a0, 1(a0)
; RV32I-NEXT: jalr zero, ra, 0
@@ -20,7 +20,7 @@ define i32 @lb(i8 *%a) nounwind {
define i32 @lh(i16 *%a) nounwind {
; RV32I-LABEL: lh:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: lh a1, 0(a0)
; RV32I-NEXT: lh a0, 4(a0)
; RV32I-NEXT: jalr zero, ra, 0
@@ -34,7 +34,7 @@ define i32 @lh(i16 *%a) nounwind {
define i32 @lw(i32 *%a) nounwind {
; RV32I-LABEL: lw:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: lw a1, 0(a0)
; RV32I-NEXT: lw a0, 12(a0)
; RV32I-NEXT: jalr zero, ra, 0
@@ -46,7 +46,7 @@ define i32 @lw(i32 *%a) nounwind {
define i32 @lbu(i8 *%a) nounwind {
; RV32I-LABEL: lbu:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: lbu a1, 0(a0)
; RV32I-NEXT: lbu a0, 4(a0)
; RV32I-NEXT: add a0, a0, a1
@@ -62,7 +62,7 @@ define i32 @lbu(i8 *%a) nounwind {
define i32 @lhu(i16 *%a) nounwind {
; RV32I-LABEL: lhu:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lhu a0, 10(a0)
; RV32I-NEXT: add a0, a0, a1
@@ -80,7 +80,7 @@ define i32 @lhu(i16 *%a) nounwind {
define void @sb(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: sb:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sb a1, 6(a0)
; RV32I-NEXT: sb a1, 0(a0)
; RV32I-NEXT: jalr zero, ra, 0
@@ -92,7 +92,7 @@ define void @sb(i8 *%a, i8 %b) nounwind {
define void @sh(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: sh:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sh a1, 14(a0)
; RV32I-NEXT: sh a1, 0(a0)
; RV32I-NEXT: jalr zero, ra, 0
@@ -104,7 +104,7 @@ define void @sh(i16 *%a, i16 %b) nounwind {
define void @sw(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: sw:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw a1, 32(a0)
; RV32I-NEXT: sw a1, 0(a0)
; RV32I-NEXT: jalr zero, ra, 0
@@ -117,7 +117,7 @@ define void @sw(i32 *%a, i32 %b) nounwind {
; Check load and store to an i1 location
define i32 @load_sext_zext_anyext_i1(i1 *%a) nounwind {
; RV32I-LABEL: load_sext_zext_anyext_i1:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: lb a1, 0(a0)
; RV32I-NEXT: lbu a1, 1(a0)
; RV32I-NEXT: lbu a0, 2(a0)
@@ -139,7 +139,7 @@ define i32 @load_sext_zext_anyext_i1(i1 *%a) nounwind {
define i16 @load_sext_zext_anyext_i1_i16(i1 *%a) nounwind {
; RV32I-LABEL: load_sext_zext_anyext_i1_i16:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: lb a1, 0(a0)
; RV32I-NEXT: lbu a1, 1(a0)
; RV32I-NEXT: lbu a0, 2(a0)
@@ -165,7 +165,7 @@ define i16 @load_sext_zext_anyext_i1_i16(i1 *%a) nounwind {
define i32 @lw_sw_global(i32 %a) nounwind {
; TODO: the addi should be folded in to the lw/sw operations
; RV32I-LABEL: lw_sw_global:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, %hi(G)
; RV32I-NEXT: addi a2, a1, %lo(G)
; RV32I-NEXT: lw a1, 0(a2)
@@ -188,7 +188,7 @@ define i32 @lw_sw_global(i32 %a) nounwind {
define i32 @lw_sw_constant(i32 %a) nounwind {
; TODO: the addi should be folded in to the lw/sw
; RV32I-LABEL: lw_sw_constant:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 912092
; RV32I-NEXT: addi a2, a1, -273
; RV32I-NEXT: lw a1, 0(a2)
diff --git a/llvm/test/CodeGen/RISCV/mul.ll b/llvm/test/CodeGen/RISCV/mul.ll
index 41653256deb..2eb5db79d1b 100644
--- a/llvm/test/CodeGen/RISCV/mul.ll
+++ b/llvm/test/CodeGen/RISCV/mul.ll
@@ -4,7 +4,7 @@
define i32 @square(i32 %a) {
; RV32I-LABEL: square:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw ra, 12(s0)
; RV32I-NEXT: lui a1, %hi(__mulsi3)
; RV32I-NEXT: addi a2, a1, %lo(__mulsi3)
@@ -18,7 +18,7 @@ define i32 @square(i32 %a) {
define i32 @mul(i32 %a, i32 %b) {
; RV32I-LABEL: mul:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw ra, 12(s0)
; RV32I-NEXT: lui a2, %hi(__mulsi3)
; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
@@ -31,7 +31,7 @@ define i32 @mul(i32 %a, i32 %b) {
define i32 @mul_constant(i32 %a) {
; RV32I-LABEL: mul_constant:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw ra, 12(s0)
; RV32I-NEXT: lui a1, %hi(__mulsi3)
; RV32I-NEXT: addi a2, a1, %lo(__mulsi3)
@@ -45,7 +45,7 @@ define i32 @mul_constant(i32 %a) {
define i32 @mul_pow2(i32 %a) {
; RV32I-LABEL: mul_pow2:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 3
; RV32I-NEXT: jalr zero, ra, 0
%1 = mul i32 %a, 8
@@ -54,7 +54,7 @@ define i32 @mul_pow2(i32 %a) {
define i64 @mul64(i64 %a, i64 %b) {
; RV32I-LABEL: mul64:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw ra, 12(s0)
; RV32I-NEXT: lui a4, %hi(__muldi3)
; RV32I-NEXT: addi a4, a4, %lo(__muldi3)
@@ -67,7 +67,7 @@ define i64 @mul64(i64 %a, i64 %b) {
define i64 @mul64_constant(i64 %a) {
; RV32I-LABEL: mul64_constant:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw ra, 12(s0)
; RV32I-NEXT: lui a2, %hi(__muldi3)
; RV32I-NEXT: addi a4, a2, %lo(__muldi3)
diff --git a/llvm/test/CodeGen/RISCV/rem.ll b/llvm/test/CodeGen/RISCV/rem.ll
index 80f79817b74..c9e2a90521d 100644
--- a/llvm/test/CodeGen/RISCV/rem.ll
+++ b/llvm/test/CodeGen/RISCV/rem.ll
@@ -4,7 +4,7 @@
define i32 @urem(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: urem:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw ra, 12(s0)
; RV32I-NEXT: lui a2, %hi(__umodsi3)
; RV32I-NEXT: addi a2, a2, %lo(__umodsi3)
@@ -17,7 +17,7 @@ define i32 @urem(i32 %a, i32 %b) nounwind {
define i32 @srem(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: srem:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw ra, 12(s0)
; RV32I-NEXT: lui a2, %hi(__modsi3)
; RV32I-NEXT: addi a2, a2, %lo(__modsi3)
diff --git a/llvm/test/CodeGen/RISCV/rotl-rotr.ll b/llvm/test/CodeGen/RISCV/rotl-rotr.ll
index bf0689feafa..b2331051fcd 100644
--- a/llvm/test/CodeGen/RISCV/rotl-rotr.ll
+++ b/llvm/test/CodeGen/RISCV/rotl-rotr.ll
@@ -7,7 +7,7 @@
define i32 @rotl(i32 %x, i32 %y) {
; RV32I-LABEL: rotl:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 32
; RV32I-NEXT: sub a2, a2, a1
; RV32I-NEXT: sll a1, a0, a1
@@ -23,7 +23,7 @@ define i32 @rotl(i32 %x, i32 %y) {
define i32 @rotr(i32 %x, i32 %y) {
; RV32I-LABEL: rotr:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 32
; RV32I-NEXT: sub a2, a2, a1
; RV32I-NEXT: srl a1, a0, a1
diff --git a/llvm/test/CodeGen/RISCV/select-cc.ll b/llvm/test/CodeGen/RISCV/select-cc.ll
index c1a570c5c98..ddc5983525e 100644
--- a/llvm/test/CodeGen/RISCV/select-cc.ll
+++ b/llvm/test/CodeGen/RISCV/select-cc.ll
@@ -4,55 +4,55 @@
define i32 @foo(i32 %a, i32 *%b) {
; RV32I-LABEL: foo:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: lw a2, 0(a1)
; RV32I-NEXT: beq a0, a2, .LBB0_2
-; RV32I-NEXT: # BB#1:
+; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: addi a0, a2, 0
; RV32I-NEXT: .LBB0_2:
; RV32I-NEXT: lw a2, 0(a1)
; RV32I-NEXT: bne a0, a2, .LBB0_4
-; RV32I-NEXT: # BB#3:
+; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: addi a0, a2, 0
; RV32I-NEXT: .LBB0_4:
; RV32I-NEXT: lw a2, 0(a1)
; RV32I-NEXT: bltu a2, a0, .LBB0_6
-; RV32I-NEXT: # BB#5:
+; RV32I-NEXT: # %bb.5:
; RV32I-NEXT: addi a0, a2, 0
; RV32I-NEXT: .LBB0_6:
; RV32I-NEXT: lw a2, 0(a1)
; RV32I-NEXT: bgeu a0, a2, .LBB0_8
-; RV32I-NEXT: # BB#7:
+; RV32I-NEXT: # %bb.7:
; RV32I-NEXT: addi a0, a2, 0
; RV32I-NEXT: .LBB0_8:
; RV32I-NEXT: lw a2, 0(a1)
; RV32I-NEXT: bltu a0, a2, .LBB0_10
-; RV32I-NEXT: # BB#9:
+; RV32I-NEXT: # %bb.9:
; RV32I-NEXT: addi a0, a2, 0
; RV32I-NEXT: .LBB0_10:
; RV32I-NEXT: lw a2, 0(a1)
; RV32I-NEXT: bgeu a2, a0, .LBB0_12
-; RV32I-NEXT: # BB#11:
+; RV32I-NEXT: # %bb.11:
; RV32I-NEXT: addi a0, a2, 0
; RV32I-NEXT: .LBB0_12:
; RV32I-NEXT: lw a2, 0(a1)
; RV32I-NEXT: blt a2, a0, .LBB0_14
-; RV32I-NEXT: # BB#13:
+; RV32I-NEXT: # %bb.13:
; RV32I-NEXT: addi a0, a2, 0
; RV32I-NEXT: .LBB0_14:
; RV32I-NEXT: lw a2, 0(a1)
; RV32I-NEXT: bge a0, a2, .LBB0_16
-; RV32I-NEXT: # BB#15:
+; RV32I-NEXT: # %bb.15:
; RV32I-NEXT: addi a0, a2, 0
; RV32I-NEXT: .LBB0_16:
; RV32I-NEXT: lw a2, 0(a1)
; RV32I-NEXT: blt a0, a2, .LBB0_18
-; RV32I-NEXT: # BB#17:
+; RV32I-NEXT: # %bb.17:
; RV32I-NEXT: addi a0, a2, 0
; RV32I-NEXT: .LBB0_18:
; RV32I-NEXT: lw a1, 0(a1)
; RV32I-NEXT: bge a1, a0, .LBB0_20
-; RV32I-NEXT: # BB#19:
+; RV32I-NEXT: # %bb.19:
; RV32I-NEXT: addi a0, a1, 0
; RV32I-NEXT: .LBB0_20:
; RV32I-NEXT: jalr zero, ra, 0
diff --git a/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll b/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
index 7c5f1205b76..80bd2d2b204 100644
--- a/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
+++ b/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
@@ -4,7 +4,7 @@
define i8 @sext_i1_to_i8(i1 %a) {
; RV32I-LABEL: sext_i1_to_i8:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: sub a0, zero, a0
; RV32I-NEXT: jalr zero, ra, 0
@@ -14,7 +14,7 @@ define i8 @sext_i1_to_i8(i1 %a) {
define i16 @sext_i1_to_i16(i1 %a) {
; RV32I-LABEL: sext_i1_to_i16:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: sub a0, zero, a0
; RV32I-NEXT: jalr zero, ra, 0
@@ -24,7 +24,7 @@ define i16 @sext_i1_to_i16(i1 %a) {
define i32 @sext_i1_to_i32(i1 %a) {
; RV32I-LABEL: sext_i1_to_i32:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: sub a0, zero, a0
; RV32I-NEXT: jalr zero, ra, 0
@@ -34,7 +34,7 @@ define i32 @sext_i1_to_i32(i1 %a) {
define i64 @sext_i1_to_i64(i1 %a) {
; RV32I-LABEL: sext_i1_to_i64:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: sub a0, zero, a0
; RV32I-NEXT: addi a1, a0, 0
@@ -45,7 +45,7 @@ define i64 @sext_i1_to_i64(i1 %a) {
define i16 @sext_i8_to_i16(i8 %a) {
; RV32I-LABEL: sext_i8_to_i16:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: jalr zero, ra, 0
@@ -55,7 +55,7 @@ define i16 @sext_i8_to_i16(i8 %a) {
define i32 @sext_i8_to_i32(i8 %a) {
; RV32I-LABEL: sext_i8_to_i32:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: jalr zero, ra, 0
@@ -65,7 +65,7 @@ define i32 @sext_i8_to_i32(i8 %a) {
define i64 @sext_i8_to_i64(i8 %a) {
; RV32I-LABEL: sext_i8_to_i64:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a0, 24
; RV32I-NEXT: srai a0, a1, 24
; RV32I-NEXT: srai a1, a1, 31
@@ -76,7 +76,7 @@ define i64 @sext_i8_to_i64(i8 %a) {
define i32 @sext_i16_to_i32(i16 %a) {
; RV32I-LABEL: sext_i16_to_i32:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: jalr zero, ra, 0
@@ -86,7 +86,7 @@ define i32 @sext_i16_to_i32(i16 %a) {
define i64 @sext_i16_to_i64(i16 %a) {
; RV32I-LABEL: sext_i16_to_i64:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a0, 16
; RV32I-NEXT: srai a0, a1, 16
; RV32I-NEXT: srai a1, a1, 31
@@ -97,7 +97,7 @@ define i64 @sext_i16_to_i64(i16 %a) {
define i64 @sext_i32_to_i64(i32 %a) {
; RV32I-LABEL: sext_i32_to_i64:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: srai a1, a0, 31
; RV32I-NEXT: jalr zero, ra, 0
%1 = sext i32 %a to i64
@@ -106,7 +106,7 @@ define i64 @sext_i32_to_i64(i32 %a) {
define i8 @zext_i1_to_i8(i1 %a) {
; RV32I-LABEL: zext_i1_to_i8:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: jalr zero, ra, 0
%1 = zext i1 %a to i8
@@ -115,7 +115,7 @@ define i8 @zext_i1_to_i8(i1 %a) {
define i16 @zext_i1_to_i16(i1 %a) {
; RV32I-LABEL: zext_i1_to_i16:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: jalr zero, ra, 0
%1 = zext i1 %a to i16
@@ -124,7 +124,7 @@ define i16 @zext_i1_to_i16(i1 %a) {
define i32 @zext_i1_to_i32(i1 %a) {
; RV32I-LABEL: zext_i1_to_i32:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: jalr zero, ra, 0
%1 = zext i1 %a to i32
@@ -133,7 +133,7 @@ define i32 @zext_i1_to_i32(i1 %a) {
define i64 @zext_i1_to_i64(i1 %a) {
; RV32I-LABEL: zext_i1_to_i64:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: addi a1, zero, 0
; RV32I-NEXT: jalr zero, ra, 0
@@ -143,7 +143,7 @@ define i64 @zext_i1_to_i64(i1 %a) {
define i16 @zext_i8_to_i16(i8 %a) {
; RV32I-LABEL: zext_i8_to_i16:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: jalr zero, ra, 0
%1 = zext i8 %a to i16
@@ -152,7 +152,7 @@ define i16 @zext_i8_to_i16(i8 %a) {
define i32 @zext_i8_to_i32(i8 %a) {
; RV32I-LABEL: zext_i8_to_i32:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: jalr zero, ra, 0
%1 = zext i8 %a to i32
@@ -161,7 +161,7 @@ define i32 @zext_i8_to_i32(i8 %a) {
define i64 @zext_i8_to_i64(i8 %a) {
; RV32I-LABEL: zext_i8_to_i64:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: addi a1, zero, 0
; RV32I-NEXT: jalr zero, ra, 0
@@ -171,7 +171,7 @@ define i64 @zext_i8_to_i64(i8 %a) {
define i32 @zext_i16_to_i32(i16 %a) {
; RV32I-LABEL: zext_i16_to_i32:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a0, a0, a1
@@ -182,7 +182,7 @@ define i32 @zext_i16_to_i32(i16 %a) {
define i64 @zext_i16_to_i64(i16 %a) {
; RV32I-LABEL: zext_i16_to_i64:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a0, a0, a1
@@ -194,7 +194,7 @@ define i64 @zext_i16_to_i64(i16 %a) {
define i64 @zext_i32_to_i64(i32 %a) {
; RV32I-LABEL: zext_i32_to_i64:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 0
; RV32I-NEXT: jalr zero, ra, 0
%1 = zext i32 %a to i64
@@ -206,7 +206,7 @@ define i64 @zext_i32_to_i64(i32 %a) {
define i1 @trunc_i8_to_i1(i8 %a) {
; RV32I-LABEL: trunc_i8_to_i1:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: jalr zero, ra, 0
%1 = trunc i8 %a to i1
ret i1 %1
@@ -214,7 +214,7 @@ define i1 @trunc_i8_to_i1(i8 %a) {
define i1 @trunc_i16_to_i1(i16 %a) {
; RV32I-LABEL: trunc_i16_to_i1:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: jalr zero, ra, 0
%1 = trunc i16 %a to i1
ret i1 %1
@@ -222,7 +222,7 @@ define i1 @trunc_i16_to_i1(i16 %a) {
define i1 @trunc_i32_to_i1(i32 %a) {
; RV32I-LABEL: trunc_i32_to_i1:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: jalr zero, ra, 0
%1 = trunc i32 %a to i1
ret i1 %1
@@ -230,7 +230,7 @@ define i1 @trunc_i32_to_i1(i32 %a) {
define i1 @trunc_i64_to_i1(i64 %a) {
; RV32I-LABEL: trunc_i64_to_i1:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: jalr zero, ra, 0
%1 = trunc i64 %a to i1
ret i1 %1
@@ -238,7 +238,7 @@ define i1 @trunc_i64_to_i1(i64 %a) {
define i8 @trunc_i16_to_i8(i16 %a) {
; RV32I-LABEL: trunc_i16_to_i8:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: jalr zero, ra, 0
%1 = trunc i16 %a to i8
ret i8 %1
@@ -246,7 +246,7 @@ define i8 @trunc_i16_to_i8(i16 %a) {
define i8 @trunc_i32_to_i8(i32 %a) {
; RV32I-LABEL: trunc_i32_to_i8:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: jalr zero, ra, 0
%1 = trunc i32 %a to i8
ret i8 %1
@@ -254,7 +254,7 @@ define i8 @trunc_i32_to_i8(i32 %a) {
define i8 @trunc_i64_to_i8(i64 %a) {
; RV32I-LABEL: trunc_i64_to_i8:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: jalr zero, ra, 0
%1 = trunc i64 %a to i8
ret i8 %1
@@ -262,7 +262,7 @@ define i8 @trunc_i64_to_i8(i64 %a) {
define i16 @trunc_i32_to_i16(i32 %a) {
; RV32I-LABEL: trunc_i32_to_i16:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: jalr zero, ra, 0
%1 = trunc i32 %a to i16
ret i16 %1
@@ -270,7 +270,7 @@ define i16 @trunc_i32_to_i16(i32 %a) {
define i16 @trunc_i64_to_i16(i64 %a) {
; RV32I-LABEL: trunc_i64_to_i16:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: jalr zero, ra, 0
%1 = trunc i64 %a to i16
ret i16 %1
@@ -278,7 +278,7 @@ define i16 @trunc_i64_to_i16(i64 %a) {
define i32 @trunc_i64_to_i32(i64 %a) {
; RV32I-LABEL: trunc_i64_to_i32:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: jalr zero, ra, 0
%1 = trunc i64 %a to i32
ret i32 %1
diff --git a/llvm/test/CodeGen/RISCV/shifts.ll b/llvm/test/CodeGen/RISCV/shifts.ll
index d773a6ad62a..c4033c574ef 100644
--- a/llvm/test/CodeGen/RISCV/shifts.ll
+++ b/llvm/test/CodeGen/RISCV/shifts.ll
@@ -7,7 +7,7 @@
define i64 @lshr64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: lshr64:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw ra, 12(s0)
; RV32I-NEXT: lui a3, %hi(__lshrdi3)
; RV32I-NEXT: addi a3, a3, %lo(__lshrdi3)
@@ -20,7 +20,7 @@ define i64 @lshr64(i64 %a, i64 %b) nounwind {
define i64 @ashr64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: ashr64:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw ra, 12(s0)
; RV32I-NEXT: lui a3, %hi(__ashrdi3)
; RV32I-NEXT: addi a3, a3, %lo(__ashrdi3)
@@ -33,7 +33,7 @@ define i64 @ashr64(i64 %a, i64 %b) nounwind {
define i64 @shl64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: shl64:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: sw ra, 12(s0)
; RV32I-NEXT: lui a3, %hi(__ashldi3)
; RV32I-NEXT: addi a3, a3, %lo(__ashldi3)
diff --git a/llvm/test/CodeGen/RISCV/wide-mem.ll b/llvm/test/CodeGen/RISCV/wide-mem.ll
index 18ab52aaf13..cbb89f631a5 100644
--- a/llvm/test/CodeGen/RISCV/wide-mem.ll
+++ b/llvm/test/CodeGen/RISCV/wide-mem.ll
@@ -6,7 +6,7 @@
define i64 @load_i64(i64 *%a) nounwind {
; RV32I-LABEL: load_i64:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: lw a2, 0(a0)
; RV32I-NEXT: lw a1, 4(a0)
; RV32I-NEXT: addi a0, a2, 0
@@ -21,7 +21,7 @@ define i64 @load_i64(i64 *%a) nounwind {
; generate two addi
define i64 @load_i64_global() nounwind {
; RV32I-LABEL: load_i64_global:
-; RV32I: # BB#0:
+; RV32I: # %bb.0:
; RV32I-NEXT: lui a0, %hi(val64)
; RV32I-NEXT: addi a0, a0, %lo(val64)
; RV32I-NEXT: lw a0, 0(a0)
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