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-rw-r--r--llvm/test/CodeGen/RISCV/float-arith.ll162
1 files changed, 162 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/RISCV/float-arith.ll b/llvm/test/CodeGen/RISCV/float-arith.ll
index 25e09471fad..a668b7e4942 100644
--- a/llvm/test/CodeGen/RISCV/float-arith.ll
+++ b/llvm/test/CodeGen/RISCV/float-arith.ll
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IF %s
+; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64IF %s
; These tests are each targeted at a particular RISC-V FPU instruction. Most
; other files in this folder exercise LLVM IR instructions that don't directly
@@ -14,6 +16,14 @@ define float @fadd_s(float %a, float %b) nounwind {
; RV32IF-NEXT: fadd.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fadd_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: fadd.s ft0, ft1, ft0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = fadd float %a, %b
ret float %1
}
@@ -26,6 +36,14 @@ define float @fsub_s(float %a, float %b) nounwind {
; RV32IF-NEXT: fsub.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fsub_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: fsub.s ft0, ft1, ft0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = fsub float %a, %b
ret float %1
}
@@ -38,6 +56,14 @@ define float @fmul_s(float %a, float %b) nounwind {
; RV32IF-NEXT: fmul.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fmul_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: fmul.s ft0, ft1, ft0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = fmul float %a, %b
ret float %1
}
@@ -50,6 +76,14 @@ define float @fdiv_s(float %a, float %b) nounwind {
; RV32IF-NEXT: fdiv.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fdiv_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: fdiv.s ft0, ft1, ft0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = fdiv float %a, %b
ret float %1
}
@@ -63,6 +97,13 @@ define float @fsqrt_s(float %a) nounwind {
; RV32IF-NEXT: fsqrt.s ft0, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fsqrt_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: fsqrt.s ft0, ft0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = call float @llvm.sqrt.f32(float %a)
ret float %1
}
@@ -77,6 +118,14 @@ define float @fsgnj_s(float %a, float %b) nounwind {
; RV32IF-NEXT: fsgnj.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fsgnj_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: fsgnj.s ft0, ft1, ft0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = call float @llvm.copysign.f32(float %a, float %b)
ret float %1
}
@@ -91,6 +140,14 @@ define i32 @fneg_s(float %a, float %b) nounwind {
; RV32IF-NEXT: fneg.s ft1, ft0
; RV32IF-NEXT: feq.s a0, ft0, ft1
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fneg_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: fadd.s ft0, ft0, ft0
+; RV64IF-NEXT: fneg.s ft1, ft0
+; RV64IF-NEXT: feq.s a0, ft0, ft1
+; RV64IF-NEXT: ret
%1 = fadd float %a, %a
%2 = fneg float %1
%3 = fcmp oeq float %1, %2
@@ -109,6 +166,15 @@ define float @fsgnjn_s(float %a, float %b) nounwind {
; RV32IF-NEXT: fsgnjn.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fsgnjn_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: fadd.s ft0, ft1, ft0
+; RV64IF-NEXT: fsgnjn.s ft0, ft1, ft0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = fadd float %a, %b
%2 = fneg float %1
%3 = call float @llvm.copysign.f32(float %a, float %2)
@@ -129,6 +195,16 @@ define float @fabs_s(float %a, float %b) nounwind {
; RV32IF-NEXT: fadd.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fabs_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: fadd.s ft0, ft1, ft0
+; RV64IF-NEXT: fabs.s ft1, ft0
+; RV64IF-NEXT: fadd.s ft0, ft1, ft0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = fadd float %a, %b
%2 = call float @llvm.fabs.f32(float %1)
%3 = fadd float %2, %1
@@ -145,6 +221,14 @@ define float @fmin_s(float %a, float %b) nounwind {
; RV32IF-NEXT: fmin.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fmin_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: fmin.s ft0, ft1, ft0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = call float @llvm.minnum.f32(float %a, float %b)
ret float %1
}
@@ -159,6 +243,14 @@ define float @fmax_s(float %a, float %b) nounwind {
; RV32IF-NEXT: fmax.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fmax_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: fmax.s ft0, ft1, ft0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = call float @llvm.maxnum.f32(float %a, float %b)
ret float %1
}
@@ -170,6 +262,13 @@ define i32 @feq_s(float %a, float %b) nounwind {
; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: feq.s a0, ft1, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: feq_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: feq.s a0, ft1, ft0
+; RV64IF-NEXT: ret
%1 = fcmp oeq float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -182,6 +281,13 @@ define i32 @flt_s(float %a, float %b) nounwind {
; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: flt_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: flt.s a0, ft1, ft0
+; RV64IF-NEXT: ret
%1 = fcmp olt float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -194,6 +300,13 @@ define i32 @fle_s(float %a, float %b) nounwind {
; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: fle.s a0, ft1, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fle_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a1
+; RV64IF-NEXT: fmv.w.x ft1, a0
+; RV64IF-NEXT: fle.s a0, ft1, ft0
+; RV64IF-NEXT: ret
%1 = fcmp ole float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -210,6 +323,15 @@ define float @fmadd_s(float %a, float %b, float %c) nounwind {
; RV32IF-NEXT: fmadd.s ft0, ft2, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fmadd_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a2
+; RV64IF-NEXT: fmv.w.x ft1, a1
+; RV64IF-NEXT: fmv.w.x ft2, a0
+; RV64IF-NEXT: fmadd.s ft0, ft2, ft1, ft0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%1 = call float @llvm.fma.f32(float %a, float %b, float %c)
ret float %1
}
@@ -227,6 +349,19 @@ define float @fmsub_s(float %a, float %b, float %c) nounwind {
; RV32IF-NEXT: fmsub.s ft0, ft2, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fmsub_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a2
+; RV64IF-NEXT: lui a2, %hi(.LCPI15_0)
+; RV64IF-NEXT: addi a2, a2, %lo(.LCPI15_0)
+; RV64IF-NEXT: flw ft1, 0(a2)
+; RV64IF-NEXT: fadd.s ft0, ft0, ft1
+; RV64IF-NEXT: fmv.w.x ft1, a1
+; RV64IF-NEXT: fmv.w.x ft2, a0
+; RV64IF-NEXT: fmsub.s ft0, ft2, ft1, ft0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%c_ = fadd float 0.0, %c ; avoid negation using xor
%negc = fsub float -0.0, %c_
%1 = call float @llvm.fma.f32(float %a, float %b, float %negc)
@@ -247,6 +382,20 @@ define float @fnmadd_s(float %a, float %b, float %c) nounwind {
; RV32IF-NEXT: fnmadd.s ft0, ft1, ft2, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fnmadd_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a2
+; RV64IF-NEXT: lui a2, %hi(.LCPI16_0)
+; RV64IF-NEXT: addi a2, a2, %lo(.LCPI16_0)
+; RV64IF-NEXT: flw ft1, 0(a2)
+; RV64IF-NEXT: fadd.s ft0, ft0, ft1
+; RV64IF-NEXT: fmv.w.x ft2, a0
+; RV64IF-NEXT: fadd.s ft1, ft2, ft1
+; RV64IF-NEXT: fmv.w.x ft2, a1
+; RV64IF-NEXT: fnmadd.s ft0, ft1, ft2, ft0
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%a_ = fadd float 0.0, %a
%c_ = fadd float 0.0, %c
%nega = fsub float -0.0, %a_
@@ -268,6 +417,19 @@ define float @fnmsub_s(float %a, float %b, float %c) nounwind {
; RV32IF-NEXT: fnmsub.s ft0, ft0, ft2, ft1
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
+;
+; RV64IF-LABEL: fnmsub_s:
+; RV64IF: # %bb.0:
+; RV64IF-NEXT: fmv.w.x ft0, a0
+; RV64IF-NEXT: lui a0, %hi(.LCPI17_0)
+; RV64IF-NEXT: addi a0, a0, %lo(.LCPI17_0)
+; RV64IF-NEXT: flw ft1, 0(a0)
+; RV64IF-NEXT: fadd.s ft0, ft0, ft1
+; RV64IF-NEXT: fmv.w.x ft1, a2
+; RV64IF-NEXT: fmv.w.x ft2, a1
+; RV64IF-NEXT: fnmsub.s ft0, ft0, ft2, ft1
+; RV64IF-NEXT: fmv.x.w a0, ft0
+; RV64IF-NEXT: ret
%a_ = fadd float 0.0, %a
%nega = fsub float -0.0, %a_
%1 = call float @llvm.fma.f32(float %nega, float %b, float %c)
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