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-rw-r--r--llvm/test/CodeGen/R600/fdiv.ll26
1 files changed, 12 insertions, 14 deletions
diff --git a/llvm/test/CodeGen/R600/fdiv.ll b/llvm/test/CodeGen/R600/fdiv.ll
index f6eb6a66948..c581ec9b9cc 100644
--- a/llvm/test/CodeGen/R600/fdiv.ll
+++ b/llvm/test/CodeGen/R600/fdiv.ll
@@ -1,19 +1,17 @@
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-;CHECK: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}}
-;CHECK: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}}
-;CHECK: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}}
-;CHECK: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}}
+;CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}
+;CHECK-DAG: MUL_IEEE * T{{[0-9]+\.[XYZW]}}
+;CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}
+;CHECK-DAG: MUL_IEEE * T{{[0-9]+\.[XYZW]}}
+;CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}
+;CHECK-DAG: MUL_IEEE * T{{[0-9]+\.[XYZW]}}
+;CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}
+;CHECK-DAG: MUL_IEEE * T{{[0-9]+\.[XYZW]}}
-define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
- %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
- %a = load <4 x float> addrspace(1) * %in
- %b = load <4 x float> addrspace(1) * %b_ptr
- %result = fdiv <4 x float> %a, %b
- store <4 x float> %result, <4 x float> addrspace(1)* %out
+define void @test(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b) {
+entry:
+ %0 = fdiv <4 x float> %a, %b
+ store <4 x float> %0, <4 x float> addrspace(1)* %out
ret void
}
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