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path: root/llvm/test/CodeGen/R600/fdiv.ll
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* R600 -> AMDGPU renameTom Stellard2015-06-131-68/+0
* [opaque pointer type] Add textual IR support for explicit type parameter to l...David Blaikie2015-02-271-2/+2
* [opaque pointer type] Add textual IR support for explicit type parameter to g...David Blaikie2015-02-271-1/+1
* R600/SI: Enable all tests that pass on VI without changesMarek Olsak2015-01-271-0/+1
* R600/SI: Add a stub GCNTargetMachineTom Stellard2015-01-061-1/+1
* R600/SI: Change all instruction assembly names to lowercase.Tom Stellard2014-11-051-14/+14
* R600: Call EmitFunctionHeader() in the AsmPrinter to populate the ELF symbol ...Tom Stellard2014-10-011-3/+3
* R600/SI: Implement less wrong f32 fdivMatt Arsenault2014-07-151-30/+47
* R600/SI: Use -verify-machineinstrs for most testsTom Stellard2013-10-101-1/+1
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-09-041-6/+6
* R600: Expand vector float operations for both SI and R600Tom Stellard2013-08-161-16/+30
* R600: Add 64-bit float load/store supportTom Stellard2013-08-011-12/+31
* Revert "R600: Non vector only instruction can be scheduled on trans unit"Tom Stellard2013-07-311-4/+4
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-07-311-4/+4
* R600: Use KCache for kernel argumentsTom Stellard2013-07-231-14/+12
* R600: Support schedule and packetization of trans-only instVincent Lejeune2013-06-291-4/+4
* R600: Use bottom up scheduling algorithmVincent Lejeune2013-05-171-2/+2
* R600: Prettier asmPrint of AluVincent Lejeune2013-05-021-7/+7
* R600: Reorganize lit tests and document how they should be organizedTom Stellard2013-04-191-0/+19
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