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-rw-r--r--llvm/test/CodeGen/PowerPC/testComparesi32leu.ll26
1 files changed, 26 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/PowerPC/testComparesi32leu.ll b/llvm/test/CodeGen/PowerPC/testComparesi32leu.ll
new file mode 100644
index 00000000000..29c051b9d9f
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/testComparesi32leu.ll
@@ -0,0 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+
+define signext i32 @test(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: rlwinm r3, r3, 0, 31, 31
+; CHECK-NEXT: rlwinm r4, r4, 0, 31, 31
+; CHECK-NEXT: clrldi r3, r3, 32
+; CHECK-NEXT: clrldi r4, r4, 32
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: blr
+entry:
+ %0 = and i8 %a, 1
+ %1 = and i8 %b, 1
+ %cmp = icmp ule i8 %0, %1
+ %conv3 = zext i1 %cmp to i32
+ ret i32 %conv3
+}
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