diff options
19 files changed, 1502 insertions, 27 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index d76ef72a28d..dca0094a667 100644 --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -75,6 +75,8 @@ STATISTIC(NumZextSetcc, "Number of (zext(setcc)) nodes expanded into GPR sequence."); STATISTIC(SignExtensionsAdded, "Number of sign extensions for compare inputs added."); +STATISTIC(ZeroExtensionsAdded, + "Number of zero extensions for compare inputs added."); STATISTIC(NumLogicOpsOnComparison, "Number of logical ops on i1 values calculated in GPR."); STATISTIC(OmittedForNonExtendUses, @@ -301,6 +303,7 @@ private: bool tryLogicOpOfCompares(SDNode *N); SDValue computeLogicOpInGPR(SDValue LogicOp); SDValue signExtendInputIfNeeded(SDValue Input); + SDValue zeroExtendInputIfNeeded(SDValue Input); SDValue addExtOrTrunc(SDValue NatWidthRes, ExtOrTruncConversion Conv); SDValue getCompoundZeroComparisonInGPR(SDValue LHS, SDLoc dl, ZeroCompare CmpTy); @@ -2763,6 +2766,41 @@ SDValue PPCDAGToDAGISel::signExtendInputIfNeeded(SDValue Input) { MVT::i64, Input), 0); } +/// If the value isn't guaranteed to be zero-extended to 64-bits, extend it. +/// Otherwise just reinterpret it as a 64-bit value. +/// Useful when emitting comparison code for 32-bit values without using +/// the compare instruction (which only considers the lower 32-bits). +SDValue PPCDAGToDAGISel::zeroExtendInputIfNeeded(SDValue Input) { + assert(Input.getValueType() == MVT::i32 && + "Can only zero-extend 32-bit values here."); + unsigned Opc = Input.getOpcode(); + + // The only condition under which we can omit the actual extend instruction: + // - The value has already been zero-extended + // - The value is a positive constant + // - The value comes from a load that isn't a sign-extending load + // An ISD::TRUNCATE will be lowered to an EXTRACT_SUBREG so we have + // to conservatively actually clear the high bits. + if (Opc == ISD::AssertZext || Opc == ISD::ZERO_EXTEND) + return addExtOrTrunc(Input, ExtOrTruncConversion::Ext); + + ConstantSDNode *InputConst = dyn_cast<ConstantSDNode>(Input); + if (InputConst && InputConst->getSExtValue() >= 0) + return addExtOrTrunc(Input, ExtOrTruncConversion::Ext); + + LoadSDNode *InputLoad = dyn_cast<LoadSDNode>(Input); + // The input is a load that doesn't sign-extend (it will be zero-extended). + if (InputLoad && InputLoad->getExtensionType() != ISD::SEXTLOAD) + return addExtOrTrunc(Input, ExtOrTruncConversion::Ext); + + // None of the above, need to zero-extend. + SDLoc dl(Input); + ZeroExtensionsAdded++; + return SDValue(CurDAG->getMachineNode(PPC::RLDICL_32_64, dl, MVT::i64, Input, + getI64Imm(0, dl), getI64Imm(32, dl)), + 0); +} + // Handle a 32-bit value in a 64-bit register and vice-versa. These are of // course not actual zero/sign extensions that will generate machine code, // they're just a way to reinterpret a 32 bit value in a register as a @@ -2980,6 +3018,24 @@ SDValue PPCDAGToDAGISel::get32BitZExtCompare(SDValue LHS, SDValue RHS, SUBFNode, getI64Imm(1, dl), getI64Imm(63, dl)), 0); } + case ISD::SETUGE: + // (zext (setcc %a, %b, setuge)) -> (xor (lshr (sub %b, %a), 63), 1) + // (zext (setcc %a, %b, setule)) -> (xor (lshr (sub %a, %b), 63), 1) + std::swap(LHS, RHS); + LLVM_FALLTHROUGH; + case ISD::SETULE: { + // The upper 32-bits of the register can't be undefined for this sequence. + LHS = zeroExtendInputIfNeeded(LHS); + RHS = zeroExtendInputIfNeeded(RHS); + SDValue Subtract = + SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, LHS, RHS), 0); + SDValue SrdiNode = + SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, + Subtract, getI64Imm(1, dl), + getI64Imm(63, dl)), 0); + return SDValue(CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64, SrdiNode, + getI32Imm(1, dl)), 0); + } } } @@ -3103,6 +3159,23 @@ SDValue PPCDAGToDAGISel::get32BitSExtCompare(SDValue LHS, SDValue RHS, return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, SUBFNode, getI64Imm(63, dl)), 0); } + case ISD::SETUGE: + // (sext (setcc %a, %b, setuge)) -> (add (lshr (sub %a, %b), 63), -1) + // (sext (setcc %a, %b, setule)) -> (add (lshr (sub %b, %a), 63), -1) + std::swap(LHS, RHS); + LLVM_FALLTHROUGH; + case ISD::SETULE: { + // The upper 32-bits of the register can't be undefined for this sequence. + LHS = zeroExtendInputIfNeeded(LHS); + RHS = zeroExtendInputIfNeeded(RHS); + SDValue Subtract = + SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, LHS, RHS), 0); + SDValue Shift = + SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Subtract, + getI32Imm(1, dl), getI32Imm(63,dl)), 0); + return SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, Shift, + getI32Imm(-1, dl)), 0); + } } } diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td index 8fc9574dca4..e22c466b203 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -4260,7 +4260,7 @@ def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; def : InstAlias<"clrldi $rA, $rS, $n", - (RLDICL_32 gprc:$rA, gprc:$rS, 0, u6imm:$n)>; + (RLDICL_32_64 g8rc:$rA, gprc:$rS, 0, u6imm:$n)>; def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; def : InstAlias<"lnia $RT", (ADDPCIS g8rc:$RT, 0)>; diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-call.ll b/llvm/test/CodeGen/PowerPC/fast-isel-call.ll index 4526db021a2..c89aa2b3655 100644 --- a/llvm/test/CodeGen/PowerPC/fast-isel-call.ll +++ b/llvm/test/CodeGen/PowerPC/fast-isel-call.ll @@ -29,17 +29,17 @@ define void @foo(i8 %a, i16 %b) nounwind { %1 = call i32 @t1(i8 signext %a) ; ELF64: extsb %2 = call i32 @t2(i8 zeroext %a) -; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56 +; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 56 %3 = call i32 @t3(i16 signext %b) ; ELF64: extsh %4 = call i32 @t4(i16 zeroext %b) -; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 +; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 48 ;; A few test to check materialization %5 = call i32 @t2(i8 zeroext 255) -; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56 +; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 56 %6 = call i32 @t4(i16 zeroext 65535) -; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 +; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 48 ret void } @@ -66,12 +66,12 @@ entry: ; ELF64: li 6, 28 ; ELF64: li 7, 40 ; ELF64: li 8, 186 -; ELF64: rldicl 3, 3, 0, 56 -; ELF64: rldicl 4, 4, 0, 56 -; ELF64: rldicl 5, 5, 0, 56 -; ELF64: rldicl 6, 6, 0, 56 -; ELF64: rldicl 7, 7, 0, 56 -; ELF64: rldicl 8, 8, 0, 56 +; ELF64: clrldi 3, 3, 56 +; ELF64: clrldi 4, 4, 56 +; ELF64: clrldi 5, 5, 56 +; ELF64: clrldi 6, 6, 56 +; ELF64: clrldi 7, 7, 56 +; ELF64: clrldi 8, 8, 56 ret i32 0 } diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-conversion.ll b/llvm/test/CodeGen/PowerPC/fast-isel-conversion.ll index a9324592aea..249f27563e2 100644 --- a/llvm/test/CodeGen/PowerPC/fast-isel-conversion.ll +++ b/llvm/test/CodeGen/PowerPC/fast-isel-conversion.ll @@ -245,11 +245,11 @@ entry: ; PPC970: uitofp_single_i16 %b.addr = alloca float, align 4 %conv = uitofp i16 %a to float -; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 +; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 48 ; ELF64: std ; ELF64: lfd ; ELF64: fcfidus -; ELF64LE: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 +; ELF64LE: clrldi {{[0-9]+}}, {{[0-9]+}}, 48 ; ELF64LE: std ; ELF64LE: lfd ; ELF64LE: fcfidus @@ -269,11 +269,11 @@ entry: ; PPC970: uitofp_single_i8 %b.addr = alloca float, align 4 %conv = uitofp i8 %a to float -; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56 +; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 56 ; ELF64: std ; ELF64: lfd ; ELF64: fcfidus -; ELF64LE: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56 +; ELF64LE: clrldi {{[0-9]+}}, {{[0-9]+}}, 56 ; ELF64LE: std ; ELF64LE: lfd ; ELF64LE: fcfidus @@ -334,11 +334,11 @@ entry: ; PPC970: uitofp_double_i16 %b.addr = alloca double, align 8 %conv = uitofp i16 %a to double -; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 +; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 48 ; ELF64: std ; ELF64: lfd ; ELF64: fcfidu -; ELF64LE: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 +; ELF64LE: clrldi {{[0-9]+}}, {{[0-9]+}}, 48 ; ELF64LE: std ; ELF64LE: lfd ; ELF64LE: fcfidu @@ -357,11 +357,11 @@ entry: ; PPC970: uitofp_double_i8 %b.addr = alloca double, align 8 %conv = uitofp i8 %a to double -; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56 +; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 56 ; ELF64: std ; ELF64: lfd ; ELF64: fcfidu -; ELF64LE: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56 +; ELF64LE: clrldi {{[0-9]+}}, {{[0-9]+}}, 56 ; ELF64LE: std ; ELF64LE: lfd ; ELF64LE: fcfidu diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-ext.ll b/llvm/test/CodeGen/PowerPC/fast-isel-ext.ll index ce8ac440b79..510f1488838 100644 --- a/llvm/test/CodeGen/PowerPC/fast-isel-ext.ll +++ b/llvm/test/CodeGen/PowerPC/fast-isel-ext.ll @@ -19,21 +19,21 @@ define i32 @zext_16_32(i16 %a) nounwind { define i64 @zext_8_64(i8 %a) nounwind { ; ELF64: zext_8_64 %r = zext i8 %a to i64 -; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56 +; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 56 ret i64 %r } define i64 @zext_16_64(i16 %a) nounwind { ; ELF64: zext_16_64 %r = zext i16 %a to i64 -; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 +; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 48 ret i64 %r } define i64 @zext_32_64(i32 %a) nounwind { ; ELF64: zext_32_64 %r = zext i32 %a to i64 -; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 32 +; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 32 ret i64 %r } diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-ret.ll b/llvm/test/CodeGen/PowerPC/fast-isel-ret.ll index 0adb5a93510..4c499e44e4f 100644 --- a/llvm/test/CodeGen/PowerPC/fast-isel-ret.ll +++ b/llvm/test/CodeGen/PowerPC/fast-isel-ret.ll @@ -47,7 +47,7 @@ entry: define zeroext i8 @ret3(i8 signext %a) nounwind { entry: ; ELF64-LABEL: ret3 -; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56 +; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 56 ; ELF64: blr ret i8 %a } @@ -63,7 +63,7 @@ entry: define zeroext i16 @ret5(i16 signext %a) nounwind { entry: ; ELF64-LABEL: ret5 -; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 +; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 48 ; ELF64: blr ret i16 %a } @@ -71,7 +71,7 @@ entry: define i16 @ret6(i16 %a) nounwind { entry: ; ELF64-LABEL: ret6 -; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48 +; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 48 ; ELF64: blr ret i16 %a } @@ -87,7 +87,7 @@ entry: define zeroext i32 @ret8(i32 signext %a) nounwind { entry: ; ELF64-LABEL: ret8 -; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 32 +; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 32 ; ELF64: blr ret i32 %a } @@ -95,7 +95,7 @@ entry: define i32 @ret9(i32 %a) nounwind { entry: ; ELF64-LABEL: ret9 -; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 32 +; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 32 ; ELF64: blr ret i32 %a } @@ -104,6 +104,7 @@ define i64 @ret10(i64 %a) nounwind { entry: ; ELF64-LABEL: ret10 ; ELF64-NOT: exts +; ELF64-NOT: clrldi ; ELF64-NOT: rldicl ; ELF64: blr ret i64 %a diff --git a/llvm/test/CodeGen/PowerPC/testComparesi32leu.ll b/llvm/test/CodeGen/PowerPC/testComparesi32leu.ll new file mode 100644 index 00000000000..29c051b9d9f --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/testComparesi32leu.ll @@ -0,0 +1,26 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +define signext i32 @test(i8 zeroext %a, i8 zeroext %b) { +; CHECK-LABEL: test: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: rlwinm r3, r3, 0, 31, 31 +; CHECK-NEXT: rlwinm r4, r4, 0, 31, 31 +; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r4, r4, 32 +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %0 = and i8 %a, 1 + %1 = and i8 %b, 1 + %cmp = icmp ule i8 %0, %1 + %conv3 = zext i1 %cmp to i32 + ret i32 %conv3 +} diff --git a/llvm/test/CodeGen/PowerPC/testComparesigeuc.ll b/llvm/test/CodeGen/PowerPC/testComparesigeuc.ll new file mode 100644 index 00000000000..7f72d0c7634 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/testComparesigeuc.ll @@ -0,0 +1,112 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i8 0, align 1 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeuc(i8 zeroext %a, i8 zeroext %b) { +entry: + %cmp = icmp uge i8 %a, %b + %conv2 = zext i1 %cmp to i32 + ret i32 %conv2 +; CHECK-LABEL: test_igeuc: +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63 +; CHECK-NEXT: xori r3, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeuc_sext(i8 zeroext %a, i8 zeroext %b) { +entry: + %cmp = icmp uge i8 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_igeuc_sext +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK-NEXT: blr + +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeuc_z(i8 zeroext %a) { +entry: + %cmp = icmp uge i8 %a, 0 + %conv2 = zext i1 %cmp to i32 + ret i32 %conv2 +; CHECK-LABEL: @test_igeuc_z +; CHECK: li r3, 1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeuc_sext_z(i8 zeroext %a) { +entry: + %cmp = icmp uge i8 %a, 0 + %conv2 = sext i1 %cmp to i32 + ret i32 %conv2 +; CHECK-LABEL: @test_igeuc_sext_z +; CHECK: li r3, -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind +define void @test_igeuc_store(i8 zeroext %a, i8 zeroext %b) { +entry: + %cmp = icmp uge i8 %a, %b + %conv3 = zext i1 %cmp to i8 + store i8 %conv3, i8* @glob + ret void +; CHECK_LABEL: test_igeuc_store: +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63 +; CHECK: xori {{r[0-9]+}}, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_igeuc_sext_store(i8 zeroext %a, i8 zeroext %b) { +entry: + %cmp = icmp uge i8 %a, %b + %conv3 = sext i1 %cmp to i8 + store i8 %conv3, i8* @glob + ret void +; CHECK-TBD-LABEL: @test_igeuc_sext_store +; CHECK-TBD: subf [[REG1:r[0-9]+]], r3, r4 +; CHECK-TBD: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-TBD: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK-TBD: stb [[REG3]] +; CHECK-TBD: blr +} + +; Function Attrs : norecurse nounwind +define void @test_igeuc_z_store(i8 zeroext %a) { +entry: + %cmp = icmp uge i8 %a, 0 + %conv3 = zext i1 %cmp to i8 + store i8 %conv3, i8* @glob + ret void +; CHECK-LABEL: @test_igeuc_z_store +; CHECK: li [[REG1:r[0-9]+]], 1 +; CHECK: stb [[REG1]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_igeuc_sext_z_store(i8 zeroext %a) { +entry: + %cmp = icmp uge i8 %a, 0 + %conv3 = sext i1 %cmp to i8 + store i8 %conv3, i8* @glob + ret void +; CHECK-LABEL: @test_igeuc_sext_z_store +; CHECK: li [[REG1:r[0-9]+]], 255 +; CHECK: stb [[REG1]] +; CHECK: blr +} diff --git a/llvm/test/CodeGen/PowerPC/testComparesigeui.ll b/llvm/test/CodeGen/PowerPC/testComparesigeui.ll new file mode 100644 index 00000000000..fd11816d6c0 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/testComparesigeui.ll @@ -0,0 +1,112 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i32 0, align 4 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeui(i32 zeroext %a, i32 zeroext %b) { +entry: + %cmp = icmp uge i32 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +; CHECK-LABEL: test_igeui: +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63 +; CHECK-NEXT: xori r3, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeui_sext(i32 zeroext %a, i32 zeroext %b) { +entry: + %cmp = icmp uge i32 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_igeui_sext +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeui_z(i32 zeroext %a) { +entry: + %cmp = icmp uge i32 %a, 0 + %sub = zext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_igeui_z +; CHECK: li r3, 1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeui_sext_z(i32 zeroext %a) { +entry: + %cmp = icmp uge i32 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_igeui_sext_z +; CHECK: li r3, -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind +define void @test_igeui_store(i32 zeroext %a, i32 zeroext %b) { +entry: + %cmp = icmp uge i32 %a, %b + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @glob + ret void +; CHECK_LABEL: test_igeuc_store: +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63 +; CHECK: xori {{r[0-9]+}}, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_igeui_sext_store(i32 zeroext %a, i32 zeroext %b) { +entry: + %cmp = icmp uge i32 %a, %b + %sub = sext i1 %cmp to i32 + store i32 %sub, i32* @glob + ret void +; CHECK-LABEL: @test_igeui_sext_store +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK: stw [[REG3]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_igeui_z_store(i32 zeroext %a) { +entry: + %cmp = icmp uge i32 %a, 0 + %conv1 = zext i1 %cmp to i32 + store i32 %conv1, i32* @glob + ret void +; CHECK-LABEL: @test_igeui_z_store +; CHECK: li [[REG1:r[0-9]+]], 1 +; CHECK: stw [[REG1]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_igeui_sext_z_store(i32 zeroext %a) { +entry: + %cmp = icmp uge i32 %a, 0 + %conv1 = sext i1 %cmp to i32 + store i32 %conv1, i32* @glob + ret void +; CHECK-LABEL: @test_igeui_sext_z_store +; CHECK: li [[REG1:r[0-9]+]], -1 +; CHECK: stw [[REG1]] +; CHECK: blr +} + diff --git a/llvm/test/CodeGen/PowerPC/testComparesigeus.ll b/llvm/test/CodeGen/PowerPC/testComparesigeus.ll new file mode 100644 index 00000000000..2da7d60294f --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/testComparesigeus.ll @@ -0,0 +1,113 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i16 0, align 2 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeus(i16 zeroext %a, i16 zeroext %b) { +entry: + %cmp = icmp uge i16 %a, %b + %conv2 = zext i1 %cmp to i32 + ret i32 %conv2 +; CHECK-LABEL: test_igeus: +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63 +; CHECK-NEXT: xori r3, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeus_sext(i16 zeroext %a, i16 zeroext %b) { +entry: + %cmp = icmp uge i16 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_igeus_sext +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeus_z(i16 zeroext %a) { +entry: + %cmp = icmp uge i16 %a, 0 + %conv2 = zext i1 %cmp to i32 + ret i32 %conv2 +; CHECK-LABEL: @test_igeus_z +; CHECK: li r3, 1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeus_sext_z(i16 zeroext %a) { +entry: + %cmp = icmp uge i16 %a, 0 + %conv2 = zext i1 %cmp to i32 + ret i32 %conv2 +; CHECK-LABEL: @test_igeus_sext_z +; CHECK: li r3, 1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind +define void @test_igeus_store(i16 zeroext %a, i16 zeroext %b) { +entry: + %cmp = icmp uge i16 %a, %b + %conv3 = zext i1 %cmp to i16 + store i16 %conv3, i16* @glob + ret void +; CHECK_LABEL: test_igeus_store: +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63 +; CHECK: xori {{r[0-9]+}}, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_igeus_sext_store(i16 zeroext %a, i16 zeroext %b) { +entry: + %cmp = icmp uge i16 %a, %b + %conv3 = sext i1 %cmp to i16 + store i16 %conv3, i16* @glob + ret void +; CHECK-LABEL: @test_igeus_sext_store +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK: sth [[REG3]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_igeus_z_store(i16 zeroext %a) { +entry: + %cmp = icmp uge i16 %a, 0 + %conv3 = zext i1 %cmp to i16 + store i16 %conv3, i16* @glob + ret void +; CHECK-LABEL: @test_igeus_z_store +; CHECK: li [[REG1:r[0-9]+]], 1 +; CHECK: sth [[REG1]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_igeus_sext_z_store(i16 zeroext %a) { +entry: + %cmp = icmp uge i16 %a, 0 + %conv3 = sext i1 %cmp to i16 + store i16 %conv3, i16* @glob + ret void +; CHECK-LABEL: @test_igeus_sext_z_store +; CHECK: lis [[REG1:r[0-9]+]], 0 +; CHECK: ori [[REG2:r[0-9]+]], [[REG1]], 65535 +; CHECK: sth [[REG2]] +; CHECK: blr +} + diff --git a/llvm/test/CodeGen/PowerPC/testComparesileuc.ll b/llvm/test/CodeGen/PowerPC/testComparesileuc.ll new file mode 100644 index 00000000000..4d5b128585a --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/testComparesileuc.ll @@ -0,0 +1,117 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i8 0, align 1 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileuc(i8 zeroext %a, i8 zeroext %b) { +entry: + %cmp = icmp ule i8 %a, %b + %conv2 = zext i1 %cmp to i32 + ret i32 %conv2 +; CHECK-LABEL: test_ileuc: +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: xori r3, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileuc_sext(i8 zeroext %a, i8 zeroext %b) { +entry: + %cmp = icmp ule i8 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_ileuc_sext +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileuc_z(i8 zeroext %a) { +entry: + %cmp = icmp eq i8 %a, 0 + %conv1 = zext i1 %cmp to i32 + ret i32 %conv1 +; CHECK-LABEL: test_ileuc_z: +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK: srwi r3, [[REG1]], 5 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileuc_sext_z(i8 zeroext %a) { +entry: + %cmp = icmp ule i8 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_ileuc_sext_z +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5 +; CHECK-NEXT: neg r3, [[REG2]] +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileuc_store(i8 zeroext %a, i8 zeroext %b) { +entry: + %cmp = icmp ule i8 %a, %b + %conv3 = zext i1 %cmp to i8 + store i8 %conv3, i8* @glob + ret void +; CHECK-LABEL: test_ileuc_store: +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK: xori {{r[0-9]+}}, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileuc_sext_store(i8 zeroext %a, i8 zeroext %b) { +entry: + %cmp = icmp ule i8 %a, %b + %conv3 = sext i1 %cmp to i8 + store i8 %conv3, i8* @glob + ret void +; CHECK-LABEL: @test_ileuc_sext_store +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK: stb [[REG3]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileuc_z_store(i8 zeroext %a) { +entry: + %cmp = icmp eq i8 %a, 0 + %conv2 = zext i1 %cmp to i8 + store i8 %conv2, i8* @glob + ret void +; CHECK-LABEL: test_ileuc_z_store: +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK: srwi {{r[0-9]+}}, [[REG1]], 5 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileuc_sext_z_store(i8 zeroext %a) { +entry: + %cmp = icmp eq i8 %a, 0 + %conv2 = sext i1 %cmp to i8 + store i8 %conv2, i8* @glob + ret void +; CHECK-LABEL: @test_ileuc_sext_z_store +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5 +; CHECK: neg [[REG3:r[0-9]+]], [[REG2]] +; CHECK: stb [[REG3]] +; CHECK: blr +} + diff --git a/llvm/test/CodeGen/PowerPC/testComparesileui.ll b/llvm/test/CodeGen/PowerPC/testComparesileui.ll new file mode 100644 index 00000000000..3ae7536d6c2 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/testComparesileui.ll @@ -0,0 +1,117 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i32 0, align 4 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileui(i32 zeroext %a, i32 zeroext %b) { +entry: + %cmp = icmp ule i32 %a, %b + %sub = zext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: test_ileui: +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: xori r3, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileui_sext(i32 zeroext %a, i32 zeroext %b) { +entry: + %cmp = icmp ule i32 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_ileui_sext +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileui_z(i32 zeroext %a) { +entry: + %cmp = icmp eq i32 %a, 0 + %sub = zext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: test_ileui_z: +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK: srwi r3, [[REG1]], 5 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileui_sext_z(i32 zeroext %a) { +entry: + %cmp = icmp eq i32 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_ileui_sext_z +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5 +; CHECK-NEXT: neg r3, [[REG2]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileui_store(i32 zeroext %a, i32 zeroext %b) { +entry: + %cmp = icmp ule i32 %a, %b + %sub = zext i1 %cmp to i32 + store i32 %sub, i32* @glob + ret void +; CHECK-LABEL: test_ileui_store: +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK: xori {{r[0-9]+}}, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileui_sext_store(i32 zeroext %a, i32 zeroext %b) { +entry: + %cmp = icmp ule i32 %a, %b + %sub = sext i1 %cmp to i32 + store i32 %sub, i32* @glob + ret void +; CHECK-LABEL: @test_ileui_sext_store +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK: stw [[REG3]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileui_z_store(i32 zeroext %a) { +entry: + %cmp = icmp eq i32 %a, 0 + %sub = zext i1 %cmp to i32 + store i32 %sub, i32* @glob + ret void +; CHECK-LABEL: test_ileui_z_store: +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK: srwi {{r[0-9]+}}, [[REG1]], 5 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileui_sext_z_store(i32 zeroext %a) { +entry: + %cmp = icmp eq i32 %a, 0 + %sub = sext i1 %cmp to i32 + store i32 %sub, i32* @glob + ret void +; CHECK-LABEL: @test_ileui_sext_z_store +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5 +; CHECK: neg [[REG3:r[0-9]+]], [[REG2]] +; CHECK: stw [[REG3]] +; CHECK: blr +} + diff --git a/llvm/test/CodeGen/PowerPC/testComparesileus.ll b/llvm/test/CodeGen/PowerPC/testComparesileus.ll new file mode 100644 index 00000000000..cd696f496bf --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/testComparesileus.ll @@ -0,0 +1,117 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i16 0, align 2 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileus(i16 zeroext %a, i16 zeroext %b) { +entry: + %cmp = icmp ule i16 %a, %b + %conv2 = zext i1 %cmp to i32 + ret i32 %conv2 +; CHECK-LABEL: test_ileus: +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: xori r3, [[REG2]], 1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileus_sext(i16 zeroext %a, i16 zeroext %b) { +entry: + %cmp = icmp ule i16 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_ileus_sext +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileus_z(i16 zeroext %a) { +entry: + %cmp = icmp ule i16 %a, 0 + %conv1 = zext i1 %cmp to i32 + ret i32 %conv1 +; CHECK-LABEL: test_ileus_z: +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK: srwi r3, [[REG1]], 5 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileus_sext_z(i16 zeroext %a) { +entry: + %cmp = icmp ule i16 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_ileus_sext_z +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5 +; CHECK-NEXT: neg r3, [[REG2]] +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileus_store(i16 zeroext %a, i16 zeroext %b) { +entry: + %cmp = icmp ule i16 %a, %b + %conv3 = zext i1 %cmp to i16 + store i16 %conv3, i16* @glob + ret void +; CHECK-LABEL: test_ileus_store: +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK: xori {{r[0-9]+}}, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileus_sext_store(i16 zeroext %a, i16 zeroext %b) { +entry: + %cmp = icmp ule i16 %a, %b + %conv3 = sext i1 %cmp to i16 + store i16 %conv3, i16* @glob + ret void +; CHECK-LABEL: @test_ileus_sext_store +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK: sth [[REG3]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileus_z_store(i16 zeroext %a) { +entry: + %cmp = icmp ule i16 %a, 0 + %conv2 = zext i1 %cmp to i16 + store i16 %conv2, i16* @glob + ret void +; CHECK-LABEL: test_ileus_z_store: +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK: srwi {{r[0-9]+}}, [[REG1]], 5 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileus_sext_z_store(i16 zeroext %a) { +entry: + %cmp = icmp ule i16 %a, 0 + %conv2 = sext i1 %cmp to i16 + store i16 %conv2, i16* @glob + ret void +; CHECK-LABEL: @test_ileus_sext_z_store +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5 +; CHECK: neg [[REG3:r[0-9]+]], [[REG2]] +; CHECK: sth [[REG3]] +; CHECK: blr +} + diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgeuc.ll b/llvm/test/CodeGen/PowerPC/testComparesllgeuc.ll new file mode 100644 index 00000000000..c7fc779c4aa --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/testComparesllgeuc.ll @@ -0,0 +1,112 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i8 0, align 1 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeuc(i8 zeroext %a, i8 zeroext %b) { +entry: + %cmp = icmp uge i8 %a, %b + %conv3 = zext i1 %cmp to i64 + ret i64 %conv3 +; CHECK-LABEL: test_llgeuc: +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63 +; CHECK: xori r3, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeuc_sext(i8 zeroext %a, i8 zeroext %b) { +entry: + %cmp = icmp uge i8 %a, %b + %conv3 = sext i1 %cmp to i64 + ret i64 %conv3 +; CHECK-LABEL: @test_llgeuc_sext +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeuc_z(i8 zeroext %a) { +entry: + %cmp = icmp uge i8 %a, 0 + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: @test_llgeuc_z +; CHECK: li r3, 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeuc_sext_z(i8 zeroext %a) { +entry: + %cmp = icmp uge i8 %a, 0 + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: @test_llgeuc_sext_z +; CHECK: li r3, -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeuc_store(i8 zeroext %a, i8 zeroext %b) { +entry: + %cmp = icmp uge i8 %a, %b + %conv3 = zext i1 %cmp to i8 + store i8 %conv3, i8* @glob + ret void +; CHECK_LABEL: test_llgeuc_store: +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63 +; CHECK: xori {{r[0-9]+}}, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeuc_sext_store(i8 zeroext %a, i8 zeroext %b) { +entry: + %cmp = icmp uge i8 %a, %b + %conv3 = sext i1 %cmp to i8 + store i8 %conv3, i8* @glob + ret void +; CHECK-LABEL: @test_llgeuc_sext_store +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK: stb [[REG3]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeuc_z_store(i8 zeroext %a) { +entry: + %cmp = icmp uge i8 %a, 0 + %conv1 = zext i1 %cmp to i8 + store i8 %conv1, i8* @glob + ret void +; CHECK-LABEL: @test_llgeuc_z_store +; CHECK: li [[REG1:r[0-9]+]], 1 +; CHECK: stb [[REG1]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeuc_sext_z_store(i8 zeroext %a) { +entry: + %cmp = icmp uge i8 %a, 0 + %conv1 = sext i1 %cmp to i8 + store i8 %conv1, i8* @glob + ret void +; CHECK-LABEL: @test_llgeuc_sext_z_store +; CHECK: li [[REG1:r[0-9]+]], 255 +; CHECK: stb [[REG1]] +; CHECK: blr +} + diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgeui.ll b/llvm/test/CodeGen/PowerPC/testComparesllgeui.ll new file mode 100644 index 00000000000..fb31ccbba29 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/testComparesllgeui.ll @@ -0,0 +1,112 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i32 0, align 4 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeui(i32 zeroext %a, i32 zeroext %b) { +entry: + %cmp = icmp uge i32 %a, %b + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: test_llgeui: +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63 +; CHECK-NEXT: xori r3, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeui_sext(i32 zeroext %a, i32 zeroext %b) { +entry: + %cmp = icmp uge i32 %a, %b + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: @test_llgeui_sext +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeui_z(i32 zeroext %a) { +entry: + %cmp = icmp uge i32 %a, 0 + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: @test_llgeui_z +; CHECK: li r3, 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeui_sext_z(i32 zeroext %a) { +entry: + %cmp = icmp uge i32 %a, 0 + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: @test_llgeui_sext_z +; CHECK: li r3, -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeui_store(i32 zeroext %a, i32 zeroext %b) { +entry: + %cmp = icmp uge i32 %a, %b + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @glob + ret void +; CHECK_LABEL: test_igeuc_store: +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63 +; CHECK: xori {{r[0-9]+}}, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeui_sext_store(i32 zeroext %a, i32 zeroext %b) { +entry: + %cmp = icmp uge i32 %a, %b + %sub = sext i1 %cmp to i32 + store i32 %sub, i32* @glob + ret void +; CHECK-LABEL: @test_llgeui_sext_store +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK: stw [[REG3]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeui_z_store(i32 zeroext %a) { +entry: + %cmp = icmp uge i32 %a, 0 + %sub = zext i1 %cmp to i32 + store i32 %sub, i32* @glob + ret void +; CHECK-LABEL: @test_llgeui_z_store +; CHECK: li [[REG1:r[0-9]+]], 1 +; CHECK: stw [[REG1]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeui_sext_z_store(i32 zeroext %a) { +entry: + %cmp = icmp uge i32 %a, 0 + %sub = sext i1 %cmp to i32 + store i32 %sub, i32* @glob + ret void +; CHECK-LABEL: @test_llgeui_sext_z_store +; CHECK: li [[REG1:r[0-9]+]], -1 +; CHECK: stw [[REG1]] +; CHECK: blr +} + diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgeus.ll b/llvm/test/CodeGen/PowerPC/testComparesllgeus.ll new file mode 100644 index 00000000000..85575059565 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/testComparesllgeus.ll @@ -0,0 +1,113 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i16 0, align 2 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeus(i16 zeroext %a, i16 zeroext %b) { +entry: + %cmp = icmp uge i16 %a, %b + %conv3 = zext i1 %cmp to i64 + ret i64 %conv3 +; CHECK-LABEL: test_llgeus: +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63 +; CHECK: xori r3, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeus_sext(i16 zeroext %a, i16 zeroext %b) { +entry: + %cmp = icmp uge i16 %a, %b + %conv3 = sext i1 %cmp to i64 + ret i64 %conv3 +; CHECK-LABEL: @test_llgeus_sext +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeus_z(i16 zeroext %a) { +entry: + %cmp = icmp uge i16 %a, 0 + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: @test_llgeus_z +; CHECK: li r3, 1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeus_sext_z(i16 zeroext %a) { +entry: + %cmp = icmp uge i16 %a, 0 + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: @test_llgeus_sext_z +; CHECK: li r3, -1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeus_store(i16 zeroext %a, i16 zeroext %b) { +entry: + %cmp = icmp uge i16 %a, %b + %conv3 = zext i1 %cmp to i16 + store i16 %conv3, i16* @glob + ret void +; CHECK_LABEL: test_llgeus_store: +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63 +; CHECK: xori {{r[0-9]+}}, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeus_sext_store(i16 zeroext %a, i16 zeroext %b) { +entry: + %cmp = icmp uge i16 %a, %b + %conv3 = sext i1 %cmp to i16 + store i16 %conv3, i16* @glob + ret void +; CHECK-LABEL: @test_llgeus_sext_store +; CHECK: sub [[REG1:r[0-9]+]], r3, r4 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK: sth [[REG3]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeus_z_store(i16 zeroext %a) { +entry: + %cmp = icmp uge i16 %a, 0 + %conv1 = zext i1 %cmp to i16 + store i16 %conv1, i16* @glob + ret void +; CHECK-LABEL: @test_llgeus_z_store +; CHECK: li [[REG1:r[0-9]+]], 1 +; CHECK: sth [[REG1]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeus_sext_z_store(i16 zeroext %a) { +entry: + %cmp = icmp uge i16 %a, 0 + %conv1 = sext i1 %cmp to i16 + store i16 %conv1, i16* @glob + ret void +; CHECK-LABEL: @test_llgeus_sext_z_store +; CHECK: lis [[REG1:r[0-9]+]], 0 +; CHECK: ori [[REG2:r[0-9]+]], [[REG1]], 65535 +; CHECK: sth [[REG2]] +; CHECK: blr +} + diff --git a/llvm/test/CodeGen/PowerPC/testComparesllleuc.ll b/llvm/test/CodeGen/PowerPC/testComparesllleuc.ll new file mode 100644 index 00000000000..29b394614e6 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/testComparesllleuc.ll @@ -0,0 +1,116 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i8 0, align 1 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleuc(i8 zeroext %a, i8 zeroext %b) { +entry: + %cmp = icmp ule i8 %a, %b + %conv3 = zext i1 %cmp to i64 + ret i64 %conv3 +; CHECK-LABEL: test_llleuc: +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: xori r3, [[REG2]], 1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleuc_sext(i8 zeroext %a, i8 zeroext %b) { +entry: + %cmp = icmp ule i8 %a, %b + %conv3 = sext i1 %cmp to i64 + ret i64 %conv3 +; CHECK-LABEL: @test_llleuc_sext +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleuc_z(i8 zeroext %a) { +entry: + %cmp = icmp ule i8 %a, 0 + %conv2 = zext i1 %cmp to i64 + ret i64 %conv2 +; CHECK-LABEL: test_llleuc_z: +; CHECK: cntlzw r3, r3 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleuc_sext_z(i8 zeroext %a) { +entry: + %cmp = icmp ule i8 %a, 0 + %conv2 = sext i1 %cmp to i64 + ret i64 %conv2 +; CHECK-LABEL: @test_llleuc_sext_z +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5 +; CHECK-NEXT: neg r3, [[REG2]] +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleuc_store(i8 zeroext %a, i8 zeroext %b) { +entry: + %cmp = icmp ule i8 %a, %b + %conv3 = zext i1 %cmp to i8 + store i8 %conv3, i8* @glob + ret void +; CHECK-LABEL: test_llleuc_store: +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK: xori {{r[0-9]+}}, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleuc_sext_store(i8 zeroext %a, i8 zeroext %b) { +entry: + %cmp = icmp ule i8 %a, %b + %conv3 = sext i1 %cmp to i8 + store i8 %conv3, i8* @glob + ret void +; CHECK-LABEL: @test_llleuc_sext_store +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK: stb [[REG3]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleuc_z_store(i8 zeroext %a) { +entry: + %cmp = icmp ule i8 %a, 0 + %conv2 = zext i1 %cmp to i8 + store i8 %conv2, i8* @glob + ret void +; CHECK-LABEL: test_llleuc_z_store: +; CHECK: cntlzw r3, r3 +; CHECK: srwi {{r[0-9]}}, r3, 5 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleuc_sext_z_store(i8 zeroext %a) { +entry: + %cmp = icmp ule i8 %a, 0 + %conv2 = sext i1 %cmp to i8 + store i8 %conv2, i8* @glob + ret void +; CHECK-LABEL: @test_llleuc_sext_z_store +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5 +; CHECK: neg [[REG3:r[0-9]+]], [[REG2]] +; CHECK: stb [[REG3]] +; CHECK: blr +} diff --git a/llvm/test/CodeGen/PowerPC/testComparesllleui.ll b/llvm/test/CodeGen/PowerPC/testComparesllleui.ll new file mode 100644 index 00000000000..ecdee9e6dd0 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/testComparesllleui.ll @@ -0,0 +1,117 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i32 0, align 4 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleui(i32 zeroext %a, i32 zeroext %b) { +entry: + %cmp = icmp ule i32 %a, %b + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: test_llleui: +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: xori r3, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleui_sext(i32 zeroext %a, i32 zeroext %b) { +entry: + %cmp = icmp ule i32 %a, %b + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: @test_llleui_sext +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleui_z(i32 zeroext %a) { +entry: + %cmp = icmp ule i32 %a, 0 + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: test_llleui_z: +; CHECK: cntlzw r3, r3 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleui_sext_z(i32 zeroext %a) { +entry: + %cmp = icmp ule i32 %a, 0 + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: @test_llleui_sext_z +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5 +; CHECK-NEXT: neg r3, [[REG2]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleui_store(i32 zeroext %a, i32 zeroext %b) { +entry: + %cmp = icmp ule i32 %a, %b + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @glob + ret void +; CHECK-LABEL: test_llleui_store: +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK: xori {{r[0-9]+}}, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleui_sext_store(i32 zeroext %a, i32 zeroext %b) { +entry: + %cmp = icmp ule i32 %a, %b + %sub = sext i1 %cmp to i32 + store i32 %sub, i32* @glob + ret void +; CHECK-LABEL: @test_llleui_sext_store +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK: stw [[REG3]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleui_z_store(i32 zeroext %a) { +entry: + %cmp = icmp ule i32 %a, 0 + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @glob + ret void +; CHECK-LABEL: test_llleui_z_store: +; CHECK: cntlzw r3, r3 +; CHECK: srwi r3, r3, 5 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleui_sext_z_store(i32 zeroext %a) { +entry: + %cmp = icmp ule i32 %a, 0 + %sub = sext i1 %cmp to i32 + store i32 %sub, i32* @glob + ret void +; CHECK-LABEL: @test_llleui_sext_z_store +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5 +; CHECK: neg [[REG3:r[0-9]+]], [[REG2]] +; CHECK: stw [[REG3]] +; CHECK: blr +} + diff --git a/llvm/test/CodeGen/PowerPC/testComparesllleus.ll b/llvm/test/CodeGen/PowerPC/testComparesllleus.ll new file mode 100644 index 00000000000..f43cfcdddf6 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/testComparesllleus.ll @@ -0,0 +1,117 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i16 0, align 2 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleus(i16 zeroext %a, i16 zeroext %b) { +entry: + %cmp = icmp ule i16 %a, %b + %conv3 = zext i1 %cmp to i64 + ret i64 %conv3 +; CHECK-LABEL: test_llleus: +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: xori r3, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleus_sext(i16 zeroext %a, i16 zeroext %b) { +entry: + %cmp = icmp ule i16 %a, %b + %conv3 = sext i1 %cmp to i64 + ret i64 %conv3 +; CHECK-LABEL: @test_llleus_sext +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleus_z(i16 zeroext %a) { +entry: + %cmp = icmp ule i16 %a, 0 + %conv2 = zext i1 %cmp to i64 + ret i64 %conv2 +; CHECK-LABEL: test_llleus_z: +; CHECK: cntlzw r3, r3 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleus_sext_z(i16 zeroext %a) { +entry: + %cmp = icmp ule i16 %a, 0 + %conv2 = sext i1 %cmp to i64 + ret i64 %conv2 +; CHECK-LABEL: @test_llleus_sext_z +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5 +; CHECK-NEXT: neg r3, [[REG2]] +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleus_store(i16 zeroext %a, i16 zeroext %b) { +entry: + %cmp = icmp ule i16 %a, %b + %conv3 = zext i1 %cmp to i16 + store i16 %conv3, i16* @glob + ret void +; CHECK-LABEL: test_llleus_store: +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK: xori {{r[0-9]+}}, [[REG2]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleus_sext_store(i16 zeroext %a, i16 zeroext %b) { +entry: + %cmp = icmp ule i16 %a, %b + %conv3 = sext i1 %cmp to i16 + store i16 %conv3, i16* @glob + ret void +; CHECK-LABEL: @test_llleus_sext_store +; CHECK: sub [[REG1:r[0-9]+]], r4, r3 +; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63 +; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1 +; CHECK: sth [[REG3]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleus_z_store(i16 zeroext %a) { +entry: + %cmp = icmp ule i16 %a, 0 + %conv2 = zext i1 %cmp to i16 + store i16 %conv2, i16* @glob + ret void +; CHECK-LABEL: test_llleus_z_store: +; CHECK: cntlzw r3, r3 +; CHECK: srwi r3, r3, 5 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleus_sext_z_store(i16 zeroext %a) { +entry: + %cmp = icmp ule i16 %a, 0 + %conv2 = sext i1 %cmp to i16 + store i16 %conv2, i16* @glob + ret void +; CHECK-LABEL: @test_llleus_sext_z_store +; CHECK: cntlzw [[REG1:r[0-9]+]], r3 +; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5 +; CHECK: neg [[REG3:r[0-9]+]], [[REG2]] +; CHECK: sth [[REG3]] +; CHECK: blr +} + |
