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-rw-r--r--llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll872
1 files changed, 584 insertions, 288 deletions
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll b/llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll
index 2b3a9b689c0..c0ac43f662f 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll
@@ -1,342 +1,638 @@
-; RUN: llc < %s -march=mips -mcpu=mips2 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,M2,M2-M3
-; RUN: llc < %s -march=mips -mcpu=mips32 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R1
-; RUN: llc < %s -march=mips -mcpu=mips32r2 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
-; RUN: llc < %s -march=mips -mcpu=mips32r3 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
-; RUN: llc < %s -march=mips -mcpu=mips32r5 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
-; RUN: llc < %s -march=mips -mcpu=mips32r6 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,SEL-32,32R6
-; RUN: llc < %s -march=mips64 -mcpu=mips3 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,M3,M2-M3
-; RUN: llc < %s -march=mips64 -mcpu=mips4 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,CMOV,CMOV-64
-; RUN: llc < %s -march=mips64 -mcpu=mips64 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,CMOV,CMOV-64
-; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,CMOV,CMOV-64
-; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,CMOV,CMOV-64
-; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,CMOV,CMOV-64
-; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,SEL-64,64R6
-; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,MM32R3
-; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,MM32R6,SEL-32
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips2 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefixes=M2
+; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefixes=CMOV32R1
+; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r2 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefixes=CMOV32R2
+; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefixes=CMOV32R2
+; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r5 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefixes=CMOV32R2
+; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefixes=32R6
+; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips3 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefixes=M3
+; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips4 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefixes=CMOV64
+; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefixes=CMOV64
+; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r2 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefixes=CMOV64
+; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r3 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefixes=CMOV64
+; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r5 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefixes=CMOV64
+; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r6 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefixes=64R6
+; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -mattr=+micromips -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefixes=MM32R3
+; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefixes=MM32R6
define float @tst_select_i1_float(i1 signext %s, float %x, float %y) {
+; M2-LABEL: tst_select_i1_float:
+; M2: # %bb.0: # %entry
+; M2-NEXT: andi $1, $4, 1
+; M2-NEXT: bnez $1, $BB0_2
+; M2-NEXT: nop
+; M2-NEXT: # %bb.1: # %entry
+; M2-NEXT: jr $ra
+; M2-NEXT: mtc1 $6, $f0
+; M2-NEXT: $BB0_2:
+; M2-NEXT: jr $ra
+; M2-NEXT: mtc1 $5, $f0
+;
+; CMOV32R1-LABEL: tst_select_i1_float:
+; CMOV32R1: # %bb.0: # %entry
+; CMOV32R1-NEXT: mtc1 $6, $f0
+; CMOV32R1-NEXT: andi $1, $4, 1
+; CMOV32R1-NEXT: mtc1 $5, $f1
+; CMOV32R1-NEXT: jr $ra
+; CMOV32R1-NEXT: movn.s $f0, $f1, $1
+;
+; CMOV32R2-LABEL: tst_select_i1_float:
+; CMOV32R2: # %bb.0: # %entry
+; CMOV32R2-NEXT: mtc1 $6, $f0
+; CMOV32R2-NEXT: andi $1, $4, 1
+; CMOV32R2-NEXT: mtc1 $5, $f1
+; CMOV32R2-NEXT: jr $ra
+; CMOV32R2-NEXT: movn.s $f0, $f1, $1
+;
+; 32R6-LABEL: tst_select_i1_float:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: mtc1 $5, $f1
+; 32R6-NEXT: mtc1 $6, $f2
+; 32R6-NEXT: mtc1 $4, $f0
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: sel.s $f0, $f2, $f1
+;
+; M3-LABEL: tst_select_i1_float:
+; M3: # %bb.0: # %entry
+; M3-NEXT: andi $1, $4, 1
+; M3-NEXT: bnez $1, .LBB0_2
+; M3-NEXT: nop
+; M3-NEXT: # %bb.1: # %entry
+; M3-NEXT: mov.s $f13, $f14
+; M3-NEXT: .LBB0_2: # %entry
+; M3-NEXT: jr $ra
+; M3-NEXT: mov.s $f0, $f13
+;
+; CMOV64-LABEL: tst_select_i1_float:
+; CMOV64: # %bb.0: # %entry
+; CMOV64-NEXT: andi $1, $4, 1
+; CMOV64-NEXT: movn.s $f14, $f13, $1
+; CMOV64-NEXT: jr $ra
+; CMOV64-NEXT: mov.s $f0, $f14
+;
+; 64R6-LABEL: tst_select_i1_float:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: mtc1 $4, $f0
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: sel.s $f0, $f14, $f13
+;
+; MM32R3-LABEL: tst_select_i1_float:
+; MM32R3: # %bb.0: # %entry
+; MM32R3-NEXT: mtc1 $6, $f0
+; MM32R3-NEXT: andi16 $2, $4, 1
+; MM32R3-NEXT: mtc1 $5, $f1
+; MM32R3-NEXT: jr $ra
+; MM32R3-NEXT: movn.s $f0, $f1, $2
+;
+; MM32R6-LABEL: tst_select_i1_float:
+; MM32R6: # %bb.0: # %entry
+; MM32R6-NEXT: mtc1 $5, $f1
+; MM32R6-NEXT: mtc1 $6, $f2
+; MM32R6-NEXT: mtc1 $4, $f0
+; MM32R6-NEXT: sel.s $f0, $f2, $f1
+; MM32R6-NEXT: jrc $ra
entry:
- ; ALL-LABEL: tst_select_i1_float:
-
- ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
- ; M2: bnez $[[T0]], [[BB0:\$BB[0-9_]+]]
- ; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
- ; M2-M3: nop
- ; M2: jr $ra
- ; M2: mtc1 $6, $f0
- ; M3: mov.s $f13, $f14
- ; M2-M3: [[BB0]]:
- ; M2-M3: jr $ra
- ; M2: mtc1 $5, $f0
- ; M3: mov.s $f0, $f13
-
- ; CMOV-32: mtc1 $6, $f0
- ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1
- ; CMOV-32: mtc1 $5, $f1
- ; CMOV-32: movn.s $f0, $f1, $[[T0]]
-
- ; SEL-32: mtc1 $5, $[[F0:f[0-9]+]]
- ; SEL-32: mtc1 $6, $[[F1:f[0-9]+]]
- ; SEL-32: mtc1 $4, $f0
- ; SEL-32: sel.s $f0, $[[F1]], $[[F0]]
-
- ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1
- ; CMOV-64: movn.s $f14, $f13, $[[T0]]
- ; CMOV-64: mov.s $f0, $f14
-
- ; SEL-64: mtc1 $4, $f0
- ; SEL-64: sel.s $f0, $f14, $f13
-
- ; MM32R3: mtc1 $6, $[[F0:f[0-9]+]]
- ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1
- ; MM32R3: mtc1 $5, $[[F1:f[0-9]+]]
- ; MM32R3: movn.s $f0, $[[F1]], $[[T0]]
-
%r = select i1 %s, float %x, float %y
ret float %r
}
define float @tst_select_i1_float_reordered(float %x, float %y,
+; M2-LABEL: tst_select_i1_float_reordered:
+; M2: # %bb.0: # %entry
+; M2-NEXT: andi $1, $6, 1
+; M2-NEXT: bnez $1, $BB1_2
+; M2-NEXT: nop
+; M2-NEXT: # %bb.1: # %entry
+; M2-NEXT: mov.s $f12, $f14
+; M2-NEXT: $BB1_2: # %entry
+; M2-NEXT: jr $ra
+; M2-NEXT: mov.s $f0, $f12
+;
+; CMOV32R1-LABEL: tst_select_i1_float_reordered:
+; CMOV32R1: # %bb.0: # %entry
+; CMOV32R1-NEXT: andi $1, $6, 1
+; CMOV32R1-NEXT: movn.s $f14, $f12, $1
+; CMOV32R1-NEXT: jr $ra
+; CMOV32R1-NEXT: mov.s $f0, $f14
+;
+; CMOV32R2-LABEL: tst_select_i1_float_reordered:
+; CMOV32R2: # %bb.0: # %entry
+; CMOV32R2-NEXT: andi $1, $6, 1
+; CMOV32R2-NEXT: movn.s $f14, $f12, $1
+; CMOV32R2-NEXT: jr $ra
+; CMOV32R2-NEXT: mov.s $f0, $f14
+;
+; 32R6-LABEL: tst_select_i1_float_reordered:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: mtc1 $6, $f0
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: sel.s $f0, $f14, $f12
+;
+; M3-LABEL: tst_select_i1_float_reordered:
+; M3: # %bb.0: # %entry
+; M3-NEXT: andi $1, $6, 1
+; M3-NEXT: bnez $1, .LBB1_2
+; M3-NEXT: nop
+; M3-NEXT: # %bb.1: # %entry
+; M3-NEXT: mov.s $f12, $f13
+; M3-NEXT: .LBB1_2: # %entry
+; M3-NEXT: jr $ra
+; M3-NEXT: mov.s $f0, $f12
+;
+; CMOV64-LABEL: tst_select_i1_float_reordered:
+; CMOV64: # %bb.0: # %entry
+; CMOV64-NEXT: andi $1, $6, 1
+; CMOV64-NEXT: movn.s $f13, $f12, $1
+; CMOV64-NEXT: jr $ra
+; CMOV64-NEXT: mov.s $f0, $f13
+;
+; 64R6-LABEL: tst_select_i1_float_reordered:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: mtc1 $6, $f0
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: sel.s $f0, $f13, $f12
+;
+; MM32R3-LABEL: tst_select_i1_float_reordered:
+; MM32R3: # %bb.0: # %entry
+; MM32R3-NEXT: andi16 $2, $6, 1
+; MM32R3-NEXT: movn.s $f14, $f12, $2
+; MM32R3-NEXT: jr $ra
+; MM32R3-NEXT: mov.s $f0, $f14
+;
+; MM32R6-LABEL: tst_select_i1_float_reordered:
+; MM32R6: # %bb.0: # %entry
+; MM32R6-NEXT: mtc1 $6, $f0
+; MM32R6-NEXT: sel.s $f0, $f14, $f12
+; MM32R6-NEXT: jrc $ra
i1 signext %s) {
entry:
- ; ALL-LABEL: tst_select_i1_float_reordered:
-
- ; M2-M3: andi $[[T0:[0-9]+]], $6, 1
- ; M2: bnez $[[T0]], [[BB0:\$BB[0-9_]+]]
- ; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
- ; M2-M3: nop
- ; M2: mov.s $f12, $f14
- ; M3: mov.s $f12, $f13
- ; M2-M3: [[BB0]]:
- ; M2-M3: jr $ra
- ; M2-M3: mov.s $f0, $f12
-
- ; CMOV-32: andi $[[T0:[0-9]+]], $6, 1
- ; CMOV-32: movn.s $f14, $f12, $[[T0]]
- ; CMOV-32: mov.s $f0, $f14
-
- ; SEL-32: mtc1 $6, $f0
- ; SEL-32: sel.s $f0, $f14, $f12
-
- ; CMOV-64: andi $[[T0:[0-9]+]], $6, 1
- ; CMOV-64: movn.s $f13, $f12, $[[T0]]
- ; CMOV-64: mov.s $f0, $f13
-
- ; SEL-64: mtc1 $6, $f0
- ; SEL-64: sel.s $f0, $f13, $f12
-
- ; MM32R3: andi16 $[[T0:[0-9]+]], $6, 1
- ; MM32R3: movn.s $[[F0:f[0-9]+]], $f12, $[[T0]]
- ; MM32R3: mov.s $f0, $[[F0]]
-
%r = select i1 %s, float %x, float %y
ret float %r
}
define float @tst_select_fcmp_olt_float(float %x, float %y) {
+; M2-LABEL: tst_select_fcmp_olt_float:
+; M2: # %bb.0: # %entry
+; M2-NEXT: c.olt.s $f12, $f14
+; M2-NEXT: bc1t $BB2_2
+; M2-NEXT: nop
+; M2-NEXT: # %bb.1: # %entry
+; M2-NEXT: mov.s $f12, $f14
+; M2-NEXT: $BB2_2: # %entry
+; M2-NEXT: jr $ra
+; M2-NEXT: mov.s $f0, $f12
+;
+; CMOV32R1-LABEL: tst_select_fcmp_olt_float:
+; CMOV32R1: # %bb.0: # %entry
+; CMOV32R1-NEXT: c.olt.s $f12, $f14
+; CMOV32R1-NEXT: movt.s $f14, $f12, $fcc0
+; CMOV32R1-NEXT: jr $ra
+; CMOV32R1-NEXT: mov.s $f0, $f14
+;
+; CMOV32R2-LABEL: tst_select_fcmp_olt_float:
+; CMOV32R2: # %bb.0: # %entry
+; CMOV32R2-NEXT: c.olt.s $f12, $f14
+; CMOV32R2-NEXT: movt.s $f14, $f12, $fcc0
+; CMOV32R2-NEXT: jr $ra
+; CMOV32R2-NEXT: mov.s $f0, $f14
+;
+; 32R6-LABEL: tst_select_fcmp_olt_float:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: cmp.lt.s $f0, $f12, $f14
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: sel.s $f0, $f14, $f12
+;
+; M3-LABEL: tst_select_fcmp_olt_float:
+; M3: # %bb.0: # %entry
+; M3-NEXT: c.olt.s $f12, $f13
+; M3-NEXT: bc1t .LBB2_2
+; M3-NEXT: nop
+; M3-NEXT: # %bb.1: # %entry
+; M3-NEXT: mov.s $f12, $f13
+; M3-NEXT: .LBB2_2: # %entry
+; M3-NEXT: jr $ra
+; M3-NEXT: mov.s $f0, $f12
+;
+; CMOV64-LABEL: tst_select_fcmp_olt_float:
+; CMOV64: # %bb.0: # %entry
+; CMOV64-NEXT: c.olt.s $f12, $f13
+; CMOV64-NEXT: movt.s $f13, $f12, $fcc0
+; CMOV64-NEXT: jr $ra
+; CMOV64-NEXT: mov.s $f0, $f13
+;
+; 64R6-LABEL: tst_select_fcmp_olt_float:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: cmp.lt.s $f0, $f12, $f13
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: sel.s $f0, $f13, $f12
+;
+; MM32R3-LABEL: tst_select_fcmp_olt_float:
+; MM32R3: # %bb.0: # %entry
+; MM32R3-NEXT: c.olt.s $f12, $f14
+; MM32R3-NEXT: movt.s $f14, $f12, $fcc0
+; MM32R3-NEXT: jr $ra
+; MM32R3-NEXT: mov.s $f0, $f14
+;
+; MM32R6-LABEL: tst_select_fcmp_olt_float:
+; MM32R6: # %bb.0: # %entry
+; MM32R6-NEXT: cmp.lt.s $f0, $f12, $f14
+; MM32R6-NEXT: sel.s $f0, $f14, $f12
+; MM32R6-NEXT: jrc $ra
entry:
- ; ALL-LABEL: tst_select_fcmp_olt_float:
-
- ; M2: c.olt.s $f12, $f14
- ; M3: c.olt.s $f12, $f13
- ; M2: bc1t [[BB0:\$BB[0-9_]+]]
- ; M3: bc1t [[BB0:\.LBB[0-9_]+]]
- ; M2-M3: nop
- ; M2: mov.s $f12, $f14
- ; M3: mov.s $f12, $f13
- ; M2-M3: [[BB0]]:
- ; M2-M3: jr $ra
- ; M2-M3: mov.s $f0, $f12
-
- ; CMOV-32: c.olt.s $f12, $f14
- ; CMOV-32: movt.s $f14, $f12, $fcc0
- ; CMOV-32: mov.s $f0, $f14
-
- ; SEL-32: cmp.lt.s $f0, $f12, $f14
- ; SEL-32: sel.s $f0, $f14, $f12
-
- ; CMOV-64: c.olt.s $f12, $f13
- ; CMOV-64: movt.s $f13, $f12, $fcc0
- ; CMOV-64: mov.s $f0, $f13
-
- ; SEL-64: cmp.lt.s $f0, $f12, $f13
- ; SEL-64: sel.s $f0, $f13, $f12
-
- ; MM32R3: c.olt.s $f12, $f14
- ; MM32R3: movt.s $f14, $f12, $fcc0
- ; MM32R3: mov.s $f0, $f14
-
%s = fcmp olt float %x, %y
%r = select i1 %s, float %x, float %y
ret float %r
}
define float @tst_select_fcmp_ole_float(float %x, float %y) {
+; M2-LABEL: tst_select_fcmp_ole_float:
+; M2: # %bb.0: # %entry
+; M2-NEXT: c.ole.s $f12, $f14
+; M2-NEXT: bc1t $BB3_2
+; M2-NEXT: nop
+; M2-NEXT: # %bb.1: # %entry
+; M2-NEXT: mov.s $f12, $f14
+; M2-NEXT: $BB3_2: # %entry
+; M2-NEXT: jr $ra
+; M2-NEXT: mov.s $f0, $f12
+;
+; CMOV32R1-LABEL: tst_select_fcmp_ole_float:
+; CMOV32R1: # %bb.0: # %entry
+; CMOV32R1-NEXT: c.ole.s $f12, $f14
+; CMOV32R1-NEXT: movt.s $f14, $f12, $fcc0
+; CMOV32R1-NEXT: jr $ra
+; CMOV32R1-NEXT: mov.s $f0, $f14
+;
+; CMOV32R2-LABEL: tst_select_fcmp_ole_float:
+; CMOV32R2: # %bb.0: # %entry
+; CMOV32R2-NEXT: c.ole.s $f12, $f14
+; CMOV32R2-NEXT: movt.s $f14, $f12, $fcc0
+; CMOV32R2-NEXT: jr $ra
+; CMOV32R2-NEXT: mov.s $f0, $f14
+;
+; 32R6-LABEL: tst_select_fcmp_ole_float:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: cmp.le.s $f0, $f12, $f14
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: sel.s $f0, $f14, $f12
+;
+; M3-LABEL: tst_select_fcmp_ole_float:
+; M3: # %bb.0: # %entry
+; M3-NEXT: c.ole.s $f12, $f13
+; M3-NEXT: bc1t .LBB3_2
+; M3-NEXT: nop
+; M3-NEXT: # %bb.1: # %entry
+; M3-NEXT: mov.s $f12, $f13
+; M3-NEXT: .LBB3_2: # %entry
+; M3-NEXT: jr $ra
+; M3-NEXT: mov.s $f0, $f12
+;
+; CMOV64-LABEL: tst_select_fcmp_ole_float:
+; CMOV64: # %bb.0: # %entry
+; CMOV64-NEXT: c.ole.s $f12, $f13
+; CMOV64-NEXT: movt.s $f13, $f12, $fcc0
+; CMOV64-NEXT: jr $ra
+; CMOV64-NEXT: mov.s $f0, $f13
+;
+; 64R6-LABEL: tst_select_fcmp_ole_float:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: cmp.le.s $f0, $f12, $f13
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: sel.s $f0, $f13, $f12
+;
+; MM32R3-LABEL: tst_select_fcmp_ole_float:
+; MM32R3: # %bb.0: # %entry
+; MM32R3-NEXT: c.ole.s $f12, $f14
+; MM32R3-NEXT: movt.s $f14, $f12, $fcc0
+; MM32R3-NEXT: jr $ra
+; MM32R3-NEXT: mov.s $f0, $f14
+;
+; MM32R6-LABEL: tst_select_fcmp_ole_float:
+; MM32R6: # %bb.0: # %entry
+; MM32R6-NEXT: cmp.le.s $f0, $f12, $f14
+; MM32R6-NEXT: sel.s $f0, $f14, $f12
+; MM32R6-NEXT: jrc $ra
entry:
- ; ALL-LABEL: tst_select_fcmp_ole_float:
-
- ; M2: c.ole.s $f12, $f14
- ; M3: c.ole.s $f12, $f13
- ; M2: bc1t [[BB0:\$BB[0-9_]+]]
- ; M3: bc1t [[BB0:\.LBB[0-9_]+]]
- ; M2-M3: nop
- ; M2: mov.s $f12, $f14
- ; M3: mov.s $f12, $f13
- ; M2-M3: [[BB0]]:
- ; M2-M3: jr $ra
- ; M2-M3: mov.s $f0, $f12
-
- ; CMOV-32: c.ole.s $f12, $f14
- ; CMOV-32: movt.s $f14, $f12, $fcc0
- ; CMOV-32: mov.s $f0, $f14
-
- ; SEL-32: cmp.le.s $f0, $f12, $f14
- ; SEL-32: sel.s $f0, $f14, $f12
-
- ; CMOV-64: c.ole.s $f12, $f13
- ; CMOV-64: movt.s $f13, $f12, $fcc0
- ; CMOV-64: mov.s $f0, $f13
-
- ; SEL-64: cmp.le.s $f0, $f12, $f13
- ; SEL-64: sel.s $f0, $f13, $f12
-
- ; MM32R3: c.ole.s $f12, $f14
- ; MM32R3: movt.s $f14, $f12, $fcc0
- ; MM32R3: mov.s $f0, $f14
-
%s = fcmp ole float %x, %y
%r = select i1 %s, float %x, float %y
ret float %r
}
define float @tst_select_fcmp_ogt_float(float %x, float %y) {
+; M2-LABEL: tst_select_fcmp_ogt_float:
+; M2: # %bb.0: # %entry
+; M2-NEXT: c.ule.s $f12, $f14
+; M2-NEXT: bc1f $BB4_2
+; M2-NEXT: nop
+; M2-NEXT: # %bb.1: # %entry
+; M2-NEXT: mov.s $f12, $f14
+; M2-NEXT: $BB4_2: # %entry
+; M2-NEXT: jr $ra
+; M2-NEXT: mov.s $f0, $f12
+;
+; CMOV32R1-LABEL: tst_select_fcmp_ogt_float:
+; CMOV32R1: # %bb.0: # %entry
+; CMOV32R1-NEXT: c.ule.s $f12, $f14
+; CMOV32R1-NEXT: movf.s $f14, $f12, $fcc0
+; CMOV32R1-NEXT: jr $ra
+; CMOV32R1-NEXT: mov.s $f0, $f14
+;
+; CMOV32R2-LABEL: tst_select_fcmp_ogt_float:
+; CMOV32R2: # %bb.0: # %entry
+; CMOV32R2-NEXT: c.ule.s $f12, $f14
+; CMOV32R2-NEXT: movf.s $f14, $f12, $fcc0
+; CMOV32R2-NEXT: jr $ra
+; CMOV32R2-NEXT: mov.s $f0, $f14
+;
+; 32R6-LABEL: tst_select_fcmp_ogt_float:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: cmp.lt.s $f0, $f14, $f12
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: sel.s $f0, $f14, $f12
+;
+; M3-LABEL: tst_select_fcmp_ogt_float:
+; M3: # %bb.0: # %entry
+; M3-NEXT: c.ule.s $f12, $f13
+; M3-NEXT: bc1f .LBB4_2
+; M3-NEXT: nop
+; M3-NEXT: # %bb.1: # %entry
+; M3-NEXT: mov.s $f12, $f13
+; M3-NEXT: .LBB4_2: # %entry
+; M3-NEXT: jr $ra
+; M3-NEXT: mov.s $f0, $f12
+;
+; CMOV64-LABEL: tst_select_fcmp_ogt_float:
+; CMOV64: # %bb.0: # %entry
+; CMOV64-NEXT: c.ule.s $f12, $f13
+; CMOV64-NEXT: movf.s $f13, $f12, $fcc0
+; CMOV64-NEXT: jr $ra
+; CMOV64-NEXT: mov.s $f0, $f13
+;
+; 64R6-LABEL: tst_select_fcmp_ogt_float:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: cmp.lt.s $f0, $f13, $f12
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: sel.s $f0, $f13, $f12
+;
+; MM32R3-LABEL: tst_select_fcmp_ogt_float:
+; MM32R3: # %bb.0: # %entry
+; MM32R3-NEXT: c.ule.s $f12, $f14
+; MM32R3-NEXT: movf.s $f14, $f12, $fcc0
+; MM32R3-NEXT: jr $ra
+; MM32R3-NEXT: mov.s $f0, $f14
+;
+; MM32R6-LABEL: tst_select_fcmp_ogt_float:
+; MM32R6: # %bb.0: # %entry
+; MM32R6-NEXT: cmp.lt.s $f0, $f14, $f12
+; MM32R6-NEXT: sel.s $f0, $f14, $f12
+; MM32R6-NEXT: jrc $ra
entry:
- ; ALL-LABEL: tst_select_fcmp_ogt_float:
-
- ; M2: c.ule.s $f12, $f14
- ; M3: c.ule.s $f12, $f13
- ; M2: bc1f [[BB0:\$BB[0-9_]+]]
- ; M3: bc1f [[BB0:\.LBB[0-9_]+]]
- ; M2-M3: nop
- ; M2: mov.s $f12, $f14
- ; M3: mov.s $f12, $f13
- ; M2-M3: [[BB0]]:
- ; M2-M3: jr $ra
- ; M2-M3: mov.s $f0, $f12
-
- ; CMOV-32: c.ule.s $f12, $f14
- ; CMOV-32: movf.s $f14, $f12, $fcc0
- ; CMOV-32: mov.s $f0, $f14
-
- ; SEL-32: cmp.lt.s $f0, $f14, $f12
- ; SEL-32: sel.s $f0, $f14, $f12
-
- ; CMOV-64: c.ule.s $f12, $f13
- ; CMOV-64: movf.s $f13, $f12, $fcc0
- ; CMOV-64: mov.s $f0, $f13
-
- ; SEL-64: cmp.lt.s $f0, $f13, $f12
- ; SEL-64: sel.s $f0, $f13, $f12
-
- ; MM32R3: c.ule.s $f12, $f14
- ; MM32R3: movf.s $f14, $f12, $fcc0
- ; MM32R3: mov.s $f0, $f14
-
%s = fcmp ogt float %x, %y
%r = select i1 %s, float %x, float %y
ret float %r
}
define float @tst_select_fcmp_oge_float(float %x, float %y) {
+; M2-LABEL: tst_select_fcmp_oge_float:
+; M2: # %bb.0: # %entry
+; M2-NEXT: c.ult.s $f12, $f14
+; M2-NEXT: bc1f $BB5_2
+; M2-NEXT: nop
+; M2-NEXT: # %bb.1: # %entry
+; M2-NEXT: mov.s $f12, $f14
+; M2-NEXT: $BB5_2: # %entry
+; M2-NEXT: jr $ra
+; M2-NEXT: mov.s $f0, $f12
+;
+; CMOV32R1-LABEL: tst_select_fcmp_oge_float:
+; CMOV32R1: # %bb.0: # %entry
+; CMOV32R1-NEXT: c.ult.s $f12, $f14
+; CMOV32R1-NEXT: movf.s $f14, $f12, $fcc0
+; CMOV32R1-NEXT: jr $ra
+; CMOV32R1-NEXT: mov.s $f0, $f14
+;
+; CMOV32R2-LABEL: tst_select_fcmp_oge_float:
+; CMOV32R2: # %bb.0: # %entry
+; CMOV32R2-NEXT: c.ult.s $f12, $f14
+; CMOV32R2-NEXT: movf.s $f14, $f12, $fcc0
+; CMOV32R2-NEXT: jr $ra
+; CMOV32R2-NEXT: mov.s $f0, $f14
+;
+; 32R6-LABEL: tst_select_fcmp_oge_float:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: cmp.le.s $f0, $f14, $f12
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: sel.s $f0, $f14, $f12
+;
+; M3-LABEL: tst_select_fcmp_oge_float:
+; M3: # %bb.0: # %entry
+; M3-NEXT: c.ult.s $f12, $f13
+; M3-NEXT: bc1f .LBB5_2
+; M3-NEXT: nop
+; M3-NEXT: # %bb.1: # %entry
+; M3-NEXT: mov.s $f12, $f13
+; M3-NEXT: .LBB5_2: # %entry
+; M3-NEXT: jr $ra
+; M3-NEXT: mov.s $f0, $f12
+;
+; CMOV64-LABEL: tst_select_fcmp_oge_float:
+; CMOV64: # %bb.0: # %entry
+; CMOV64-NEXT: c.ult.s $f12, $f13
+; CMOV64-NEXT: movf.s $f13, $f12, $fcc0
+; CMOV64-NEXT: jr $ra
+; CMOV64-NEXT: mov.s $f0, $f13
+;
+; 64R6-LABEL: tst_select_fcmp_oge_float:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: cmp.le.s $f0, $f13, $f12
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: sel.s $f0, $f13, $f12
+;
+; MM32R3-LABEL: tst_select_fcmp_oge_float:
+; MM32R3: # %bb.0: # %entry
+; MM32R3-NEXT: c.ult.s $f12, $f14
+; MM32R3-NEXT: movf.s $f14, $f12, $fcc0
+; MM32R3-NEXT: jr $ra
+; MM32R3-NEXT: mov.s $f0, $f14
+;
+; MM32R6-LABEL: tst_select_fcmp_oge_float:
+; MM32R6: # %bb.0: # %entry
+; MM32R6-NEXT: cmp.le.s $f0, $f14, $f12
+; MM32R6-NEXT: sel.s $f0, $f14, $f12
+; MM32R6-NEXT: jrc $ra
entry:
- ; ALL-LABEL: tst_select_fcmp_oge_float:
-
- ; M2: c.ult.s $f12, $f14
- ; M3: c.ult.s $f12, $f13
- ; M2: bc1f [[BB0:\$BB[0-9_]+]]
- ; M3: bc1f [[BB0:\.LBB[0-9_]+]]
- ; M2-M3: nop
- ; M2: mov.s $f12, $f14
- ; M3: mov.s $f12, $f13
- ; M2-M3: [[BB0]]:
- ; M2-M3: jr $ra
- ; M2-M3: mov.s $f0, $f12
-
- ; CMOV-32: c.ult.s $f12, $f14
- ; CMOV-32: movf.s $f14, $f12, $fcc0
- ; CMOV-32: mov.s $f0, $f14
-
- ; SEL-32: cmp.le.s $f0, $f14, $f12
- ; SEL-32: sel.s $f0, $f14, $f12
-
- ; CMOV-64: c.ult.s $f12, $f13
- ; CMOV-64: movf.s $f13, $f12, $fcc0
- ; CMOV-64: mov.s $f0, $f13
-
- ; SEL-64: cmp.le.s $f0, $f13, $f12
- ; SEL-64: sel.s $f0, $f13, $f12
-
- ; MM32R3: c.ult.s $f12, $f14
- ; MM32R3: movf.s $f14, $f12, $fcc0
- ; MM32R3: mov.s $f0, $f14
-
%s = fcmp oge float %x, %y
%r = select i1 %s, float %x, float %y
ret float %r
}
define float @tst_select_fcmp_oeq_float(float %x, float %y) {
+; M2-LABEL: tst_select_fcmp_oeq_float:
+; M2: # %bb.0: # %entry
+; M2-NEXT: c.eq.s $f12, $f14
+; M2-NEXT: bc1t $BB6_2
+; M2-NEXT: nop
+; M2-NEXT: # %bb.1: # %entry
+; M2-NEXT: mov.s $f12, $f14
+; M2-NEXT: $BB6_2: # %entry
+; M2-NEXT: jr $ra
+; M2-NEXT: mov.s $f0, $f12
+;
+; CMOV32R1-LABEL: tst_select_fcmp_oeq_float:
+; CMOV32R1: # %bb.0: # %entry
+; CMOV32R1-NEXT: c.eq.s $f12, $f14
+; CMOV32R1-NEXT: movt.s $f14, $f12, $fcc0
+; CMOV32R1-NEXT: jr $ra
+; CMOV32R1-NEXT: mov.s $f0, $f14
+;
+; CMOV32R2-LABEL: tst_select_fcmp_oeq_float:
+; CMOV32R2: # %bb.0: # %entry
+; CMOV32R2-NEXT: c.eq.s $f12, $f14
+; CMOV32R2-NEXT: movt.s $f14, $f12, $fcc0
+; CMOV32R2-NEXT: jr $ra
+; CMOV32R2-NEXT: mov.s $f0, $f14
+;
+; 32R6-LABEL: tst_select_fcmp_oeq_float:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: cmp.eq.s $f0, $f12, $f14
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: sel.s $f0, $f14, $f12
+;
+; M3-LABEL: tst_select_fcmp_oeq_float:
+; M3: # %bb.0: # %entry
+; M3-NEXT: c.eq.s $f12, $f13
+; M3-NEXT: bc1t .LBB6_2
+; M3-NEXT: nop
+; M3-NEXT: # %bb.1: # %entry
+; M3-NEXT: mov.s $f12, $f13
+; M3-NEXT: .LBB6_2: # %entry
+; M3-NEXT: jr $ra
+; M3-NEXT: mov.s $f0, $f12
+;
+; CMOV64-LABEL: tst_select_fcmp_oeq_float:
+; CMOV64: # %bb.0: # %entry
+; CMOV64-NEXT: c.eq.s $f12, $f13
+; CMOV64-NEXT: movt.s $f13, $f12, $fcc0
+; CMOV64-NEXT: jr $ra
+; CMOV64-NEXT: mov.s $f0, $f13
+;
+; 64R6-LABEL: tst_select_fcmp_oeq_float:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: cmp.eq.s $f0, $f12, $f13
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: sel.s $f0, $f13, $f12
+;
+; MM32R3-LABEL: tst_select_fcmp_oeq_float:
+; MM32R3: # %bb.0: # %entry
+; MM32R3-NEXT: c.eq.s $f12, $f14
+; MM32R3-NEXT: movt.s $f14, $f12, $fcc0
+; MM32R3-NEXT: jr $ra
+; MM32R3-NEXT: mov.s $f0, $f14
+;
+; MM32R6-LABEL: tst_select_fcmp_oeq_float:
+; MM32R6: # %bb.0: # %entry
+; MM32R6-NEXT: cmp.eq.s $f0, $f12, $f14
+; MM32R6-NEXT: sel.s $f0, $f14, $f12
+; MM32R6-NEXT: jrc $ra
entry:
- ; ALL-LABEL: tst_select_fcmp_oeq_float:
-
- ; M2: c.eq.s $f12, $f14
- ; M3: c.eq.s $f12, $f13
- ; M2: bc1t [[BB0:\$BB[0-9_]+]]
- ; M3: bc1t [[BB0:\.LBB[0-9_]+]]
- ; M2-M3: nop
- ; M2: mov.s $f12, $f14
- ; M3: mov.s $f12, $f13
- ; M2-M3: [[BB0]]:
- ; M2-M3: jr $ra
- ; M2-M3: mov.s $f0, $f12
-
- ; CMOV-32: c.eq.s $f12, $f14
- ; CMOV-32: movt.s $f14, $f12, $fcc0
- ; CMOV-32: mov.s $f0, $f14
-
- ; SEL-32: cmp.eq.s $f0, $f12, $f14
- ; SEL-32: sel.s $f0, $f14, $f12
-
- ; CMOV-64: c.eq.s $f12, $f13
- ; CMOV-64: movt.s $f13, $f12, $fcc0
- ; CMOV-64: mov.s $f0, $f13
-
- ; SEL-64: cmp.eq.s $f0, $f12, $f13
- ; SEL-64: sel.s $f0, $f13, $f12
-
- ; MM32R3: c.eq.s $f12, $f14
- ; MM32R3: movt.s $f14, $f12, $fcc0
- ; MM32R3: mov.s $f0, $f14
-
%s = fcmp oeq float %x, %y
%r = select i1 %s, float %x, float %y
ret float %r
}
define float @tst_select_fcmp_one_float(float %x, float %y) {
+; M2-LABEL: tst_select_fcmp_one_float:
+; M2: # %bb.0: # %entry
+; M2-NEXT: c.ueq.s $f12, $f14
+; M2-NEXT: bc1f $BB7_2
+; M2-NEXT: nop
+; M2-NEXT: # %bb.1: # %entry
+; M2-NEXT: mov.s $f12, $f14
+; M2-NEXT: $BB7_2: # %entry
+; M2-NEXT: jr $ra
+; M2-NEXT: mov.s $f0, $f12
+;
+; CMOV32R1-LABEL: tst_select_fcmp_one_float:
+; CMOV32R1: # %bb.0: # %entry
+; CMOV32R1-NEXT: c.ueq.s $f12, $f14
+; CMOV32R1-NEXT: movf.s $f14, $f12, $fcc0
+; CMOV32R1-NEXT: jr $ra
+; CMOV32R1-NEXT: mov.s $f0, $f14
+;
+; CMOV32R2-LABEL: tst_select_fcmp_one_float:
+; CMOV32R2: # %bb.0: # %entry
+; CMOV32R2-NEXT: c.ueq.s $f12, $f14
+; CMOV32R2-NEXT: movf.s $f14, $f12, $fcc0
+; CMOV32R2-NEXT: jr $ra
+; CMOV32R2-NEXT: mov.s $f0, $f14
+;
+; 32R6-LABEL: tst_select_fcmp_one_float:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: cmp.ueq.s $f0, $f12, $f14
+; 32R6-NEXT: mfc1 $1, $f0
+; 32R6-NEXT: not $1, $1
+; 32R6-NEXT: mtc1 $1, $f0
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: sel.s $f0, $f14, $f12
+;
+; M3-LABEL: tst_select_fcmp_one_float:
+; M3: # %bb.0: # %entry
+; M3-NEXT: c.ueq.s $f12, $f13
+; M3-NEXT: bc1f .LBB7_2
+; M3-NEXT: nop
+; M3-NEXT: # %bb.1: # %entry
+; M3-NEXT: mov.s $f12, $f13
+; M3-NEXT: .LBB7_2: # %entry
+; M3-NEXT: jr $ra
+; M3-NEXT: mov.s $f0, $f12
+;
+; CMOV64-LABEL: tst_select_fcmp_one_float:
+; CMOV64: # %bb.0: # %entry
+; CMOV64-NEXT: c.ueq.s $f12, $f13
+; CMOV64-NEXT: movf.s $f13, $f12, $fcc0
+; CMOV64-NEXT: jr $ra
+; CMOV64-NEXT: mov.s $f0, $f13
+;
+; 64R6-LABEL: tst_select_fcmp_one_float:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: cmp.ueq.s $f0, $f12, $f13
+; 64R6-NEXT: mfc1 $1, $f0
+; 64R6-NEXT: not $1, $1
+; 64R6-NEXT: mtc1 $1, $f0
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: sel.s $f0, $f13, $f12
+;
+; MM32R3-LABEL: tst_select_fcmp_one_float:
+; MM32R3: # %bb.0: # %entry
+; MM32R3-NEXT: c.ueq.s $f12, $f14
+; MM32R3-NEXT: movf.s $f14, $f12, $fcc0
+; MM32R3-NEXT: jr $ra
+; MM32R3-NEXT: mov.s $f0, $f14
+;
+; MM32R6-LABEL: tst_select_fcmp_one_float:
+; MM32R6: # %bb.0: # %entry
+; MM32R6-NEXT: cmp.ueq.s $f0, $f12, $f14
+; MM32R6-NEXT: mfc1 $1, $f0
+; MM32R6-NEXT: not $1, $1
+; MM32R6-NEXT: mtc1 $1, $f0
+; MM32R6-NEXT: sel.s $f0, $f14, $f12
+; MM32R6-NEXT: jrc $ra
entry:
- ; ALL-LABEL: tst_select_fcmp_one_float:
-
- ; M2: c.ueq.s $f12, $f14
- ; M3: c.ueq.s $f12, $f13
- ; M2: bc1f [[BB0:\$BB[0-9_]+]]
- ; M3: bc1f [[BB0:\.LBB[0-9_]+]]
- ; M2-M3: nop
- ; M2: mov.s $f12, $f14
- ; M3: mov.s $f12, $f13
- ; M2-M3: [[BB0]]:
- ; M2-M3: jr $ra
- ; M2-M3: mov.s $f0, $f12
-
- ; CMOV-32: c.ueq.s $f12, $f14
- ; CMOV-32: movf.s $f14, $f12, $fcc0
- ; CMOV-32: mov.s $f0, $f14
-
- ; SEL-32: cmp.ueq.s $f0, $f12, $f14
- ; SEL-32: mfc1 $[[T0:[0-9]+]], $f0
- ; SEL-32: not $[[T0]], $[[T0]]
- ; SEL-32: mtc1 $[[T0:[0-9]+]], $f0
- ; SEL-32: sel.s $f0, $f14, $f12
-
- ; CMOV-64: c.ueq.s $f12, $f13
- ; CMOV-64: movf.s $f13, $f12, $fcc0
- ; CMOV-64: mov.s $f0, $f13
-
- ; SEL-64: cmp.ueq.s $f0, $f12, $f13
- ; SEL-64: mfc1 $[[T0:[0-9]+]], $f0
- ; SEL-64: not $[[T0]], $[[T0]]
- ; SEL-64: mtc1 $[[T0:[0-9]+]], $f0
- ; SEL-64: sel.s $f0, $f13, $f12
-
- ; MM32R3: c.ueq.s $f12, $f14
- ; MM32R3: movf.s $f14, $f12, $fcc0
- ; MM32R3: mov.s $f0, $f14
-
%s = fcmp one float %x, %y
%r = select i1 %s, float %x, float %y
ret float %r
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