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-rw-r--r--llvm/test/CodeGen/Mips/Fast-ISel/sel1.ll147
-rw-r--r--llvm/test/CodeGen/Mips/analyzebranch.ll304
-rw-r--r--llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll936
-rw-r--r--llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll872
-rw-r--r--llvm/test/CodeGen/Mips/o32_cc_byval.ll231
-rw-r--r--llvm/test/CodeGen/Mips/select.ll1765
6 files changed, 2787 insertions, 1468 deletions
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/sel1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/sel1.ll
index b3fc58f293a..8c258513072 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/sel1.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/sel1.ll
@@ -1,125 +1,134 @@
-; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O2 -relocation-model=pic \
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32r2 -O2 -relocation-model=pic \
; RUN: -fast-isel -fast-isel-abort=1 | FileCheck %s
+; FIXME: The first xor instruction is redundant.
define i1 @sel_i1(i1 %j, i1 %k, i1 %l) {
+; CHECK-LABEL: sel_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xor $1, $4, $zero
+; CHECK-NEXT: sltu $1, $zero, $1
+; CHECK-NEXT: andi $1, $1, 1
+; CHECK-NEXT: movn $6, $5, $1
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: move $2, $6
entry:
- ; CHECK-LABEL: sel_i1:
-
- ; FIXME: The following instruction is redundant.
- ; CHECK: xor $[[T0:[0-9]+]], $4, $zero
- ; CHECK-NEXT: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
- ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1
- ; CHECK-NEXT: movn $6, $5, $[[T2]]
- ; CHECK: move $2, $6
%cond = icmp ne i1 %j, 0
%res = select i1 %cond, i1 %k, i1 %l
ret i1 %res
}
+; FIXME: The seb $X, $zero and xor .., .., $x instructions are redundant.
define i8 @sel_i8(i8 %j, i8 %k, i8 %l) {
+; CHECK-LABEL: sel_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: seb $1, $4
+; CHECK-NEXT: seb $2, $zero
+; CHECK-NEXT: xor $1, $1, $2
+; CHECK-NEXT: sltu $1, $zero, $1
+; CHECK-NEXT: andi $1, $1, 1
+; CHECK-NEXT: movn $6, $5, $1
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: move $2, $6
entry:
- ; CHECK-LABEL: sel_i8:
-
- ; CHECK-DAG: seb $[[T0:[0-9]+]], $4
- ; FIXME: The following 2 instructions are redundant.
- ; CHECK-DAG: seb $[[T1:[0-9]+]], $zero
- ; CHECK: xor $[[T2:[0-9]+]], $[[T0]], $[[T1]]
- ; CHECK-NEXT: sltu $[[T3:[0-9]+]], $zero, $[[T2]]
- ; CHECK-NEXT: andi $[[T4:[0-9]+]], $[[T3]], 1
- ; CHECK-NEXT: movn $6, $5, $[[T4]]
- ; CHECK: move $2, $6
%cond = icmp ne i8 %j, 0
%res = select i1 %cond, i8 %k, i8 %l
ret i8 %res
}
+; FIXME: The seh $X, $zero and xor .., .., $x instructions are redundant.
define i16 @sel_i16(i16 %j, i16 %k, i16 %l) {
+; CHECK-LABEL: sel_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: seh $1, $4
+; CHECK-NEXT: seh $2, $zero
+; CHECK-NEXT: xor $1, $1, $2
+; CHECK-NEXT: sltu $1, $zero, $1
+; CHECK-NEXT: andi $1, $1, 1
+; CHECK-NEXT: movn $6, $5, $1
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: move $2, $6
entry:
- ; CHECK-LABEL: sel_i16:
-
- ; CHECK-DAG: seh $[[T0:[0-9]+]], $4
- ; FIXME: The following 2 instructions are redundant.
- ; CHECK-DAG: seh $[[T1:[0-9]+]], $zero
- ; CHECK: xor $[[T2:[0-9]+]], $[[T0]], $[[T1]]
- ; CHECK-NEXT: sltu $[[T3:[0-9]+]], $zero, $[[T2]]
- ; CHECK-NEXT: andi $[[T4:[0-9]+]], $[[T3]], 1
- ; CHECK-NEXT: movn $6, $5, $[[T4]]
- ; CHECK: move $2, $6
%cond = icmp ne i16 %j, 0
%res = select i1 %cond, i16 %k, i16 %l
ret i16 %res
}
+; FIXME: The first xor instruction is redundant.
define i32 @sel_i32(i32 %j, i32 %k, i32 %l) {
+; CHECK-LABEL: sel_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xor $1, $4, $zero
+; CHECK-NEXT: sltu $1, $zero, $1
+; CHECK-NEXT: andi $1, $1, 1
+; CHECK-NEXT: movn $6, $5, $1
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: move $2, $6
entry:
- ; CHECK-LABEL: sel_i32:
-
- ; FIXME: The following instruction is redundant.
- ; CHECK: xor $[[T0:[0-9]+]], $4, $zero
- ; CHECK-NEXT: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
- ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1
- ; CHECK-NEXT: movn $6, $5, $[[T2]]
- ; CHECK: move $2, $6
%cond = icmp ne i32 %j, 0
%res = select i1 %cond, i32 %k, i32 %l
ret i32 %res
}
define float @sel_float(i32 %j, float %k, float %l) {
+; CHECK-LABEL: sel_float:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mtc1 $6, $f0
+; CHECK-NEXT: mtc1 $5, $f1
+; CHECK-NEXT: xor $1, $4, $zero
+; CHECK-NEXT: sltu $1, $zero, $1
+; CHECK-NEXT: andi $1, $1, 1
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: movn.s $f0, $f1, $1
entry:
- ; CHECK-LABEL: sel_float:
-
- ; CHECK-DAG: mtc1 $6, $f0
- ; CHECK-DAG: mtc1 $5, $f1
- ; CHECK-DAG: xor $[[T0:[0-9]+]], $4, $zero
- ; CHECK: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
- ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1
- ; CHECK: movn.s $f0, $f1, $[[T2]]
%cond = icmp ne i32 %j, 0
%res = select i1 %cond, float %k, float %l
ret float %res
}
define float @sel_float2(float %k, float %l, i32 %j) {
+; CHECK-LABEL: sel_float2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xor $1, $6, $zero
+; CHECK-NEXT: sltu $1, $zero, $1
+; CHECK-NEXT: andi $1, $1, 1
+; CHECK-NEXT: movn.s $f14, $f12, $1
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: mov.s $f0, $f14
entry:
- ; CHECK-LABEL: sel_float2:
-
- ; CHECK-DAG: xor $[[T0:[0-9]+]], $6, $zero
- ; CHECK: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
- ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1
- ; CHECK: movn.s $f14, $f12, $[[T2]]
- ; CHECK: mov.s $f0, $f14
%cond = icmp ne i32 %j, 0
%res = select i1 %cond, float %k, float %l
ret float %res
}
define double @sel_double(i32 %j, double %k, double %l) {
+; CHECK-LABEL: sel_double:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mtc1 $6, $f2
+; CHECK-NEXT: mthc1 $7, $f2
+; CHECK-NEXT: ldc1 $f0, 16($sp)
+; CHECK-NEXT: xor $1, $4, $zero
+; CHECK-NEXT: sltu $1, $zero, $1
+; CHECK-NEXT: andi $1, $1, 1
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: movn.d $f0, $f2, $1
entry:
- ; CHECK-LABEL: sel_double:
-
- ; CHECK-DAG: mtc1 $6, $f2
- ; CHECK-DAG: mthc1 $7, $f2
- ; CHECK-DAG: ldc1 $f0, 16($sp)
- ; CHECK-DAG: xor $[[T0:[0-9]+]], $4, $zero
- ; CHECK: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
- ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1
- ; CHECK: movn.d $f0, $f2, $[[T2]]
%cond = icmp ne i32 %j, 0
%res = select i1 %cond, double %k, double %l
ret double %res
}
define double @sel_double2(double %k, double %l, i32 %j) {
+; CHECK-LABEL: sel_double2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lw $1, 16($sp)
+; CHECK-NEXT: xor $1, $1, $zero
+; CHECK-NEXT: sltu $1, $zero, $1
+; CHECK-NEXT: andi $1, $1, 1
+; CHECK-NEXT: movn.d $f14, $f12, $1
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: mov.d $f0, $f14
entry:
- ; CHECK-LABEL: sel_double2:
-
- ; CHECK-DAG: lw $[[SEL:[0-9]+]], 16($sp)
- ; CHECK-DAG: xor $[[T0:[0-9]+]], $[[SEL]], $zero
- ; CHECK: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
- ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1
- ; CHECK: movn.d $f14, $f12, $[[T2]]
- ; CHECK: mov.d $f0, $f14
%cond = icmp ne i32 %j, 0
%res = select i1 %cond, double %k, double %l
ret double %res
diff --git a/llvm/test/CodeGen/Mips/analyzebranch.ll b/llvm/test/CodeGen/Mips/analyzebranch.ll
index 62150875e75..23c312c613c 100644
--- a/llvm/test/CodeGen/Mips/analyzebranch.ll
+++ b/llvm/test/CodeGen/Mips/analyzebranch.ll
@@ -1,26 +1,149 @@
-; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s -check-prefixes=ALL,FCC
-; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=ALL,FCC
-; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefixes=ALL,GPR,32-GPR
-; RUN: llc -march=mips64 -mcpu=mips4 < %s | FileCheck %s -check-prefixes=ALL,FCC
-; RUN: llc -march=mips64 -mcpu=mips64 < %s | FileCheck %s -check-prefixes=ALL,FCC
-; RUN: llc -march=mips64 -mcpu=mips64r2 < %s | FileCheck %s -check-prefixes=ALL,FCC
-; RUN: llc -march=mips64 -mcpu=mips64r6 < %s | FileCheck %s -check-prefixes=ALL,GPR,64-GPR
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=mips-unknown-linux-gnu -mcpu=mips32 < %s | FileCheck %s -check-prefixes=MIPS32
+; RUN: llc -mtriple=mips-unknown-linux-gnu -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=MIPS32R2
+; RUN: llc -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 < %s | FileCheck %s -check-prefixes=MIPS32r6
+; RUN: llc -mtriple=mips64-unknown-linux-gnu -mcpu=mips4 < %s | FileCheck %s -check-prefixes=MIPS4
+; RUN: llc -mtriple=mips64-unknown-linux-gnu -mcpu=mips64 < %s | FileCheck %s -check-prefixes=MIPS64
+; RUN: llc -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r2 < %s | FileCheck %s -check-prefixes=MIPS64R2
+; RUN: llc -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r6 < %s | FileCheck %s -check-prefixes=MIPS64R6
define double @foo(double %a, double %b) nounwind readnone {
+; MIPS32-LABEL: foo:
+; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: mtc1 $zero, $f0
+; MIPS32-NEXT: mtc1 $zero, $f1
+; MIPS32-NEXT: c.ule.d $f12, $f0
+; MIPS32-NEXT: bc1f $BB0_2
+; MIPS32-NEXT: nop
+; MIPS32-NEXT: # %bb.1: # %if.else
+; MIPS32-NEXT: mtc1 $zero, $f12
+; MIPS32-NEXT: mtc1 $zero, $f13
+; MIPS32-NEXT: c.ule.d $f14, $f12
+; MIPS32-NEXT: bc1t $BB0_3
+; MIPS32-NEXT: nop
+; MIPS32-NEXT: $BB0_2: # %if.end6
+; MIPS32-NEXT: sub.d $f0, $f14, $f12
+; MIPS32-NEXT: add.d $f12, $f0, $f0
+; MIPS32-NEXT: $BB0_3: # %return
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: mov.d $f0, $f12
+;
+; MIPS32R2-LABEL: foo:
+; MIPS32R2: # %bb.0: # %entry
+; MIPS32R2-NEXT: mtc1 $zero, $f0
+; MIPS32R2-NEXT: mthc1 $zero, $f0
+; MIPS32R2-NEXT: c.ule.d $f12, $f0
+; MIPS32R2-NEXT: bc1f $BB0_2
+; MIPS32R2-NEXT: nop
+; MIPS32R2-NEXT: # %bb.1: # %if.else
+; MIPS32R2-NEXT: mtc1 $zero, $f12
+; MIPS32R2-NEXT: mthc1 $zero, $f12
+; MIPS32R2-NEXT: c.ule.d $f14, $f12
+; MIPS32R2-NEXT: bc1t $BB0_3
+; MIPS32R2-NEXT: nop
+; MIPS32R2-NEXT: $BB0_2: # %if.end6
+; MIPS32R2-NEXT: sub.d $f0, $f14, $f12
+; MIPS32R2-NEXT: add.d $f12, $f0, $f0
+; MIPS32R2-NEXT: $BB0_3: # %return
+; MIPS32R2-NEXT: jr $ra
+; MIPS32R2-NEXT: mov.d $f0, $f12
+;
+; MIPS32r6-LABEL: foo:
+; MIPS32r6: # %bb.0: # %entry
+; MIPS32r6-NEXT: mtc1 $zero, $f0
+; MIPS32r6-NEXT: mthc1 $zero, $f0
+; MIPS32r6-NEXT: cmp.lt.d $f0, $f0, $f12
+; MIPS32r6-NEXT: mfc1 $1, $f0
+; MIPS32r6-NEXT: andi $1, $1, 1
+; MIPS32r6-NEXT: bnezc $1, $BB0_2
+; MIPS32r6-NEXT: # %bb.1: # %if.else
+; MIPS32r6-NEXT: mtc1 $zero, $f12
+; MIPS32r6-NEXT: mthc1 $zero, $f12
+; MIPS32r6-NEXT: cmp.ule.d $f0, $f14, $f12
+; MIPS32r6-NEXT: mfc1 $1, $f0
+; MIPS32r6-NEXT: andi $1, $1, 1
+; MIPS32r6-NEXT: bnezc $1, $BB0_3
+; MIPS32r6-NEXT: $BB0_2: # %if.end6
+; MIPS32r6-NEXT: sub.d $f0, $f14, $f12
+; MIPS32r6-NEXT: add.d $f12, $f0, $f0
+; MIPS32r6-NEXT: $BB0_3: # %return
+; MIPS32r6-NEXT: jr $ra
+; MIPS32r6-NEXT: mov.d $f0, $f12
+;
+; MIPS4-LABEL: foo:
+; MIPS4: # %bb.0: # %entry
+; MIPS4-NEXT: dmtc1 $zero, $f0
+; MIPS4-NEXT: c.ule.d $f12, $f0
+; MIPS4-NEXT: bc1f .LBB0_2
+; MIPS4-NEXT: nop
+; MIPS4-NEXT: # %bb.1: # %if.else
+; MIPS4-NEXT: dmtc1 $zero, $f12
+; MIPS4-NEXT: c.ule.d $f13, $f12
+; MIPS4-NEXT: bc1t .LBB0_3
+; MIPS4-NEXT: nop
+; MIPS4-NEXT: .LBB0_2: # %if.end6
+; MIPS4-NEXT: sub.d $f0, $f13, $f12
+; MIPS4-NEXT: add.d $f12, $f0, $f0
+; MIPS4-NEXT: .LBB0_3: # %return
+; MIPS4-NEXT: jr $ra
+; MIPS4-NEXT: mov.d $f0, $f12
+;
+; MIPS64-LABEL: foo:
+; MIPS64: # %bb.0: # %entry
+; MIPS64-NEXT: dmtc1 $zero, $f0
+; MIPS64-NEXT: c.ule.d $f12, $f0
+; MIPS64-NEXT: bc1f .LBB0_2
+; MIPS64-NEXT: nop
+; MIPS64-NEXT: # %bb.1: # %if.else
+; MIPS64-NEXT: dmtc1 $zero, $f12
+; MIPS64-NEXT: c.ule.d $f13, $f12
+; MIPS64-NEXT: bc1t .LBB0_3
+; MIPS64-NEXT: nop
+; MIPS64-NEXT: .LBB0_2: # %if.end6
+; MIPS64-NEXT: sub.d $f0, $f13, $f12
+; MIPS64-NEXT: add.d $f12, $f0, $f0
+; MIPS64-NEXT: .LBB0_3: # %return
+; MIPS64-NEXT: jr $ra
+; MIPS64-NEXT: mov.d $f0, $f12
+;
+; MIPS64R2-LABEL: foo:
+; MIPS64R2: # %bb.0: # %entry
+; MIPS64R2-NEXT: dmtc1 $zero, $f0
+; MIPS64R2-NEXT: c.ule.d $f12, $f0
+; MIPS64R2-NEXT: bc1f .LBB0_2
+; MIPS64R2-NEXT: nop
+; MIPS64R2-NEXT: # %bb.1: # %if.else
+; MIPS64R2-NEXT: dmtc1 $zero, $f12
+; MIPS64R2-NEXT: c.ule.d $f13, $f12
+; MIPS64R2-NEXT: bc1t .LBB0_3
+; MIPS64R2-NEXT: nop
+; MIPS64R2-NEXT: .LBB0_2: # %if.end6
+; MIPS64R2-NEXT: sub.d $f0, $f13, $f12
+; MIPS64R2-NEXT: add.d $f12, $f0, $f0
+; MIPS64R2-NEXT: .LBB0_3: # %return
+; MIPS64R2-NEXT: jr $ra
+; MIPS64R2-NEXT: mov.d $f0, $f12
+;
+; MIPS64R6-LABEL: foo:
+; MIPS64R6: # %bb.0: # %entry
+; MIPS64R6-NEXT: dmtc1 $zero, $f0
+; MIPS64R6-NEXT: cmp.lt.d $f0, $f0, $f12
+; MIPS64R6-NEXT: mfc1 $1, $f0
+; MIPS64R6-NEXT: andi $1, $1, 1
+; MIPS64R6-NEXT: bnezc $1, .LBB0_2
+; MIPS64R6-NEXT: # %bb.1: # %if.else
+; MIPS64R6-NEXT: dmtc1 $zero, $f12
+; MIPS64R6-NEXT: cmp.ule.d $f0, $f13, $f12
+; MIPS64R6-NEXT: mfc1 $1, $f0
+; MIPS64R6-NEXT: andi $1, $1, 1
+; MIPS64R6-NEXT: bnezc $1, .LBB0_3
+; MIPS64R6-NEXT: .LBB0_2: # %if.end6
+; MIPS64R6-NEXT: sub.d $f0, $f13, $f12
+; MIPS64R6-NEXT: add.d $f12, $f0, $f0
+; MIPS64R6-NEXT: .LBB0_3: # %return
+; MIPS64R6-NEXT: jr $ra
+; MIPS64R6-NEXT: mov.d $f0, $f12
entry:
-; ALL-LABEL: foo:
-
-; FCC: bc1f {{\$|\.L}}BB
-; FCC: nop
-
-; 32-GPR: mtc1 $zero, $[[Z:f[0-9]]]
-; 32-GPR: mthc1 $zero, $[[Z:f[0-9]]]
-; 64-GPR: dmtc1 $zero, $[[Z:f[0-9]]]
-; GPR: cmp.lt.d $[[FGRCC:f[0-9]+]], $[[Z]], $f12
-; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC]]
-; GPR-NOT: not $[[GPRCC]], $[[GPRCC]]
-; GPR: bnezc $[[GPRCC]], {{\$|\.L}}BB
-
%cmp = fcmp ogt double %a, 0.000000e+00
br i1 %cmp, label %if.end6, label %if.else
@@ -40,19 +163,136 @@ return: ; preds = %if.else, %if.end6
}
define void @f1(float %f) nounwind {
+; MIPS32-LABEL: f1:
+; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: addiu $sp, $sp, -24
+; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
+; MIPS32-NEXT: mtc1 $zero, $f0
+; MIPS32-NEXT: c.eq.s $f12, $f0
+; MIPS32-NEXT: bc1f $BB1_2
+; MIPS32-NEXT: nop
+; MIPS32-NEXT: # %bb.1: # %if.end
+; MIPS32-NEXT: jal f2
+; MIPS32-NEXT: nop
+; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: addiu $sp, $sp, 24
+; MIPS32-NEXT: $BB1_2: # %if.then
+; MIPS32-NEXT: jal abort
+; MIPS32-NEXT: nop
+;
+; MIPS32R2-LABEL: f1:
+; MIPS32R2: # %bb.0: # %entry
+; MIPS32R2-NEXT: addiu $sp, $sp, -24
+; MIPS32R2-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
+; MIPS32R2-NEXT: mtc1 $zero, $f0
+; MIPS32R2-NEXT: c.eq.s $f12, $f0
+; MIPS32R2-NEXT: bc1f $BB1_2
+; MIPS32R2-NEXT: nop
+; MIPS32R2-NEXT: # %bb.1: # %if.end
+; MIPS32R2-NEXT: jal f2
+; MIPS32R2-NEXT: nop
+; MIPS32R2-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
+; MIPS32R2-NEXT: jr $ra
+; MIPS32R2-NEXT: addiu $sp, $sp, 24
+; MIPS32R2-NEXT: $BB1_2: # %if.then
+; MIPS32R2-NEXT: jal abort
+; MIPS32R2-NEXT: nop
+;
+; MIPS32r6-LABEL: f1:
+; MIPS32r6: # %bb.0: # %entry
+; MIPS32r6-NEXT: addiu $sp, $sp, -24
+; MIPS32r6-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
+; MIPS32r6-NEXT: mtc1 $zero, $f0
+; MIPS32r6-NEXT: cmp.eq.s $f0, $f12, $f0
+; MIPS32r6-NEXT: mfc1 $1, $f0
+; MIPS32r6-NEXT: andi $1, $1, 1
+; MIPS32r6-NEXT: beqzc $1, $BB1_2
+; MIPS32r6-NEXT: nop
+; MIPS32r6-NEXT: # %bb.1: # %if.end
+; MIPS32r6-NEXT: jal f2
+; MIPS32r6-NEXT: nop
+; MIPS32r6-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
+; MIPS32r6-NEXT: jr $ra
+; MIPS32r6-NEXT: addiu $sp, $sp, 24
+; MIPS32r6-NEXT: $BB1_2: # %if.then
+; MIPS32r6-NEXT: jal abort
+; MIPS32r6-NEXT: nop
+;
+; MIPS4-LABEL: f1:
+; MIPS4: # %bb.0: # %entry
+; MIPS4-NEXT: daddiu $sp, $sp, -16
+; MIPS4-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
+; MIPS4-NEXT: mtc1 $zero, $f0
+; MIPS4-NEXT: c.eq.s $f12, $f0
+; MIPS4-NEXT: bc1f .LBB1_2
+; MIPS4-NEXT: nop
+; MIPS4-NEXT: # %bb.1: # %if.end
+; MIPS4-NEXT: jal f2
+; MIPS4-NEXT: nop
+; MIPS4-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
+; MIPS4-NEXT: jr $ra
+; MIPS4-NEXT: daddiu $sp, $sp, 16
+; MIPS4-NEXT: .LBB1_2: # %if.then
+; MIPS4-NEXT: jal abort
+; MIPS4-NEXT: nop
+;
+; MIPS64-LABEL: f1:
+; MIPS64: # %bb.0: # %entry
+; MIPS64-NEXT: daddiu $sp, $sp, -16
+; MIPS64-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
+; MIPS64-NEXT: mtc1 $zero, $f0
+; MIPS64-NEXT: c.eq.s $f12, $f0
+; MIPS64-NEXT: bc1f .LBB1_2
+; MIPS64-NEXT: nop
+; MIPS64-NEXT: # %bb.1: # %if.end
+; MIPS64-NEXT: jal f2
+; MIPS64-NEXT: nop
+; MIPS64-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
+; MIPS64-NEXT: jr $ra
+; MIPS64-NEXT: daddiu $sp, $sp, 16
+; MIPS64-NEXT: .LBB1_2: # %if.then
+; MIPS64-NEXT: jal abort
+; MIPS64-NEXT: nop
+;
+; MIPS64R2-LABEL: f1:
+; MIPS64R2: # %bb.0: # %entry
+; MIPS64R2-NEXT: daddiu $sp, $sp, -16
+; MIPS64R2-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
+; MIPS64R2-NEXT: mtc1 $zero, $f0
+; MIPS64R2-NEXT: c.eq.s $f12, $f0
+; MIPS64R2-NEXT: bc1f .LBB1_2
+; MIPS64R2-NEXT: nop
+; MIPS64R2-NEXT: # %bb.1: # %if.end
+; MIPS64R2-NEXT: jal f2
+; MIPS64R2-NEXT: nop
+; MIPS64R2-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
+; MIPS64R2-NEXT: jr $ra
+; MIPS64R2-NEXT: daddiu $sp, $sp, 16
+; MIPS64R2-NEXT: .LBB1_2: # %if.then
+; MIPS64R2-NEXT: jal abort
+; MIPS64R2-NEXT: nop
+;
+; MIPS64R6-LABEL: f1:
+; MIPS64R6: # %bb.0: # %entry
+; MIPS64R6-NEXT: daddiu $sp, $sp, -16
+; MIPS64R6-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
+; MIPS64R6-NEXT: mtc1 $zero, $f0
+; MIPS64R6-NEXT: cmp.eq.s $f0, $f12, $f0
+; MIPS64R6-NEXT: mfc1 $1, $f0
+; MIPS64R6-NEXT: andi $1, $1, 1
+; MIPS64R6-NEXT: beqzc $1, .LBB1_2
+; MIPS64R6-NEXT: nop
+; MIPS64R6-NEXT: # %bb.1: # %if.end
+; MIPS64R6-NEXT: jal f2
+; MIPS64R6-NEXT: nop
+; MIPS64R6-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
+; MIPS64R6-NEXT: jr $ra
+; MIPS64R6-NEXT: daddiu $sp, $sp, 16
+; MIPS64R6-NEXT: .LBB1_2: # %if.then
+; MIPS64R6-NEXT: jal abort
+; MIPS64R6-NEXT: nop
entry:
-; ALL-LABEL: f1:
-
-; FCC: bc1f {{\$|\.L}}BB
-; FCC: nop
-
-; GPR: mtc1 $zero, $[[Z:f[0-9]]]
-; GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $[[Z]]
-; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC]]
-; GPR-NOT: not $[[GPRCC]], $[[GPRCC]]
-; 64-GPR beqzc $[[GPRCC]], $BB
-; 32-GPR beqz $[[GPRCC]], $BB
-
%cmp = fcmp une float %f, 0.000000e+00
br i1 %cmp, label %if.then, label %if.end
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll b/llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll
index a7174d25937..40d74157ab8 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll
@@ -1,363 +1,681 @@
-; RUN: llc < %s -march=mips -mcpu=mips2 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,M2,M2-M3
-; RUN: llc < %s -march=mips -mcpu=mips32 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R1
-; RUN: llc < %s -march=mips -mcpu=mips32r2 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
-; RUN: llc < %s -march=mips -mcpu=mips32r3 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
-; RUN: llc < %s -march=mips -mcpu=mips32r5 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
-; RUN: llc < %s -march=mips -mcpu=mips32r6 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,SEL-32,32R6
-; RUN: llc < %s -march=mips64 -mcpu=mips3 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,M3,M2-M3
-; RUN: llc < %s -march=mips64 -mcpu=mips4 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,CMOV,CMOV-64
-; RUN: llc < %s -march=mips64 -mcpu=mips64 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,CMOV,CMOV-64
-; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,CMOV,CMOV-64
-; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,CMOV,CMOV-64
-; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,CMOV,CMOV-64
-; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,SEL-64,64R6
-; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,MM32R3
-; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,MM32R6,SEL-32
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips2 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefix=M2
+; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefix=CMOV32R1
+; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r2 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefix=CMOV32R2
+; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefix=CMOV32R2
+; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r5 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefix=CMOV32R2
+; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefix=32R6
+; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips3 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefix=M3
+; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips4 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefix=CMOV64
+; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefix=CMOV64
+; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r2 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefix=CMOV64
+; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r3 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefix=CMOV64
+; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r5 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefix=CMOV64
+; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r6 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefix=64R6
+; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -mattr=+micromips -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefix=MM32R3
+; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefix=MM32R6
define double @tst_select_i1_double(i1 signext %s, double %x, double %y) {
+; M2-LABEL: tst_select_i1_double:
+; M2: # %bb.0: # %entry
+; M2-NEXT: andi $1, $4, 1
+; M2-NEXT: bnez $1, $BB0_2
+; M2-NEXT: nop
+; M2-NEXT: # %bb.1: # %entry
+; M2-NEXT: ldc1 $f0, 16($sp)
+; M2-NEXT: jr $ra
+; M2-NEXT: nop
+; M2-NEXT: $BB0_2:
+; M2-NEXT: mtc1 $7, $f0
+; M2-NEXT: jr $ra
+; M2-NEXT: mtc1 $6, $f1
+;
+; CMOV32R1-LABEL: tst_select_i1_double:
+; CMOV32R1: # %bb.0: # %entry
+; CMOV32R1-NEXT: mtc1 $7, $f2
+; CMOV32R1-NEXT: mtc1 $6, $f3
+; CMOV32R1-NEXT: andi $1, $4, 1
+; CMOV32R1-NEXT: ldc1 $f0, 16($sp)
+; CMOV32R1-NEXT: jr $ra
+; CMOV32R1-NEXT: movn.d $f0, $f2, $1
+;
+; CMOV32R2-LABEL: tst_select_i1_double:
+; CMOV32R2: # %bb.0: # %entry
+; CMOV32R2-NEXT: mtc1 $7, $f2
+; CMOV32R2-NEXT: mthc1 $6, $f2
+; CMOV32R2-NEXT: andi $1, $4, 1
+; CMOV32R2-NEXT: ldc1 $f0, 16($sp)
+; CMOV32R2-NEXT: jr $ra
+; CMOV32R2-NEXT: movn.d $f0, $f2, $1
+;
+; 32R6-LABEL: tst_select_i1_double:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: mtc1 $7, $f1
+; 32R6-NEXT: mthc1 $6, $f1
+; 32R6-NEXT: mtc1 $4, $f0
+; 32R6-NEXT: ldc1 $f2, 16($sp)
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: sel.d $f0, $f2, $f1
+;
+; M3-LABEL: tst_select_i1_double:
+; M3: # %bb.0: # %entry
+; M3-NEXT: andi $1, $4, 1
+; M3-NEXT: bnez $1, .LBB0_2
+; M3-NEXT: nop
+; M3-NEXT: # %bb.1: # %entry
+; M3-NEXT: mov.d $f13, $f14
+; M3-NEXT: .LBB0_2: # %entry
+; M3-NEXT: jr $ra
+; M3-NEXT: mov.d $f0, $f13
+;
+; CMOV64-LABEL: tst_select_i1_double:
+; CMOV64: # %bb.0: # %entry
+; CMOV64-NEXT: andi $1, $4, 1
+; CMOV64-NEXT: movn.d $f14, $f13, $1
+; CMOV64-NEXT: jr $ra
+; CMOV64-NEXT: mov.d $f0, $f14
+;
+; 64R6-LABEL: tst_select_i1_double:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: mtc1 $4, $f0
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: sel.d $f0, $f14, $f13
+;
+; MM32R3-LABEL: tst_select_i1_double:
+; MM32R3: # %bb.0: # %entry
+; MM32R3-NEXT: mtc1 $7, $f2
+; MM32R3-NEXT: mthc1 $6, $f2
+; MM32R3-NEXT: andi16 $2, $4, 1
+; MM32R3-NEXT: ldc1 $f0, 16($sp)
+; MM32R3-NEXT: jr $ra
+; MM32R3-NEXT: movn.d $f0, $f2, $2
+;
+; MM32R6-LABEL: tst_select_i1_double:
+; MM32R6: # %bb.0: # %entry
+; MM32R6-NEXT: mtc1 $7, $f1
+; MM32R6-NEXT: mthc1 $6, $f1
+; MM32R6-NEXT: mtc1 $4, $f0
+; MM32R6-NEXT: ldc1 $f2, 16($sp)
+; MM32R6-NEXT: sel.d $f0, $f2, $f1
+; MM32R6-NEXT: jrc $ra
entry:
- ; ALL-LABEL: tst_select_i1_double:
-
- ; M2: andi $[[T0:[0-9]+]], $4, 1
- ; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
- ; M2: nop
- ; M2: ldc1 $f0, 16($sp)
- ; M2: jr $ra
- ; M2: nop
- ; M2: $[[BB0]]:
- ; M2: mtc1 $7, $f0
- ; M2: jr $ra
- ; M2: mtc1 $6, $f1
-
- ; CMOV-32: mtc1 $7, $[[F0:f[0-9]+]]
- ; CMOV-32R1: mtc1 $6, $f{{[0-9]+}}
- ; CMOV-32R2-R5: mthc1 $6, $[[F0]]
- ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1
- ; CMOV-32: ldc1 $f0, 16($sp)
- ; CMOV-32: movn.d $f0, $[[F0]], $[[T0]]
-
- ; SEL-32: mtc1 $7, $[[F0:f[0-9]+]]
- ; SEL-32: mthc1 $6, $[[F0]]
- ; SEL-32: mtc1 $4, $f0
- ; SEL-32: ldc1 $[[F1:f[0-9]+]], 16($sp)
- ; SEL-32: sel.d $f0, $[[F1]], $[[F0]]
-
- ; M3: andi $[[T0:[0-9]+]], $4, 1
- ; M3: bnez $[[T0]], [[BB0:.LBB[0-9_]+]]
- ; M3: nop
- ; M3: mov.d $f13, $f14
- ; M3: [[BB0]]:
- ; M3: jr $ra
- ; M3: mov.d $f0, $f13
-
- ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1
- ; CMOV-64: movn.d $f14, $f13, $[[T0]]
- ; CMOV-64: mov.d $f0, $f14
-
- ; SEL-64: mtc1 $4, $f0
- ; SEL-64: sel.d $f0, $f14, $f13
-
- ; MM32R3: mtc1 $7, $[[F0:f[0-9]+]]
- ; MM32R3: mthc1 $6, $[[F0]]
- ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1
- ; MM32R3: ldc1 $f0, 16($sp)
- ; MM32R3: movn.d $f0, $[[F0]], $[[T0]]
-
%r = select i1 %s, double %x, double %y
ret double %r
}
define double @tst_select_i1_double_reordered(double %x, double %y,
+; M2-LABEL: tst_select_i1_double_reordered:
+; M2: # %bb.0: # %entry
+; M2-NEXT: lw $1, 16($sp)
+; M2-NEXT: andi $1, $1, 1
+; M2-NEXT: bnez $1, $BB1_2
+; M2-NEXT: nop
+; M2-NEXT: # %bb.1: # %entry
+; M2-NEXT: mov.d $f12, $f14
+; M2-NEXT: $BB1_2: # %entry
+; M2-NEXT: jr $ra
+; M2-NEXT: mov.d $f0, $f12
+;
+; CMOV32R1-LABEL: tst_select_i1_double_reordered:
+; CMOV32R1: # %bb.0: # %entry
+; CMOV32R1-NEXT: lw $1, 16($sp)
+; CMOV32R1-NEXT: andi $1, $1, 1
+; CMOV32R1-NEXT: movn.d $f14, $f12, $1
+; CMOV32R1-NEXT: jr $ra
+; CMOV32R1-NEXT: mov.d $f0, $f14
+;
+; CMOV32R2-LABEL: tst_select_i1_double_reordered:
+; CMOV32R2: # %bb.0: # %entry
+; CMOV32R2-NEXT: lw $1, 16($sp)
+; CMOV32R2-NEXT: andi $1, $1, 1
+; CMOV32R2-NEXT: movn.d $f14, $f12, $1
+; CMOV32R2-NEXT: jr $ra
+; CMOV32R2-NEXT: mov.d $f0, $f14
+;
+; 32R6-LABEL: tst_select_i1_double_reordered:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: lw $1, 16($sp)
+; 32R6-NEXT: mtc1 $1, $f0
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: sel.d $f0, $f14, $f12
+;
+; M3-LABEL: tst_select_i1_double_reordered:
+; M3: # %bb.0: # %entry
+; M3-NEXT: andi $1, $6, 1
+; M3-NEXT: bnez $1, .LBB1_2
+; M3-NEXT: nop
+; M3-NEXT: # %bb.1: # %entry
+; M3-NEXT: mov.d $f12, $f13
+; M3-NEXT: .LBB1_2: # %entry
+; M3-NEXT: jr $ra
+; M3-NEXT: mov.d $f0, $f12
+;
+; CMOV64-LABEL: tst_select_i1_double_reordered:
+; CMOV64: # %bb.0: # %entry
+; CMOV64-NEXT: andi $1, $6, 1
+; CMOV64-NEXT: movn.d $f13, $f12, $1
+; CMOV64-NEXT: jr $ra
+; CMOV64-NEXT: mov.d $f0, $f13
+;
+; 64R6-LABEL: tst_select_i1_double_reordered:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: mtc1 $6, $f0
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: sel.d $f0, $f13, $f12
+;
+; MM32R3-LABEL: tst_select_i1_double_reordered:
+; MM32R3: # %bb.0: # %entry
+; MM32R3-NEXT: lw $2, 16($sp)
+; MM32R3-NEXT: andi16 $2, $2, 1
+; MM32R3-NEXT: movn.d $f14, $f12, $2
+; MM32R3-NEXT: jr $ra
+; MM32R3-NEXT: mov.d $f0, $f14
+;
+; MM32R6-LABEL: tst_select_i1_double_reordered:
+; MM32R6: # %bb.0: # %entry
+; MM32R6-NEXT: lw $1, 16($sp)
+; MM32R6-NEXT: mtc1 $1, $f0
+; MM32R6-NEXT: sel.d $f0, $f14, $f12
+; MM32R6-NEXT: jrc $ra
i1 signext %s) {
entry:
- ; ALL-LABEL: tst_select_i1_double_reordered:
-
- ; M2: lw $[[T0:[0-9]+]], 16($sp)
- ; M2: andi $[[T1:[0-9]+]], $[[T0]], 1
- ; M2: bnez $[[T1]], $[[BB0:BB[0-9_]+]]
- ; M2: nop
- ; M2: mov.d $f12, $f14
- ; M2: $[[BB0]]:
- ; M2: jr $ra
- ; M2: mov.d $f0, $f12
-
- ; CMOV-32: lw $[[T0:[0-9]+]], 16($sp)
- ; CMOV-32: andi $[[T1:[0-9]+]], $[[T0]], 1
- ; CMOV-32: movn.d $f14, $f12, $[[T1]]
- ; CMOV-32: mov.d $f0, $f14
-
- ; SEL-32: lw $[[T0:[0-9]+]], 16($sp)
- ; SEL-32: mtc1 $[[T0]], $f0
- ; SEL-32: sel.d $f0, $f14, $f12
-
- ; M3: andi $[[T0:[0-9]+]], $6, 1
- ; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
- ; M3: nop
- ; M3: mov.d $f12, $f13
- ; M3: [[BB0]]:
- ; M3: jr $ra
- ; M3: mov.d $f0, $f12
-
- ; CMOV-64: andi $[[T0:[0-9]+]], $6, 1
- ; CMOV-64: movn.d $f13, $f12, $[[T0]]
- ; CMOV-64: mov.d $f0, $f13
-
- ; SEL-64: mtc1 $6, $f0
- ; SEL-64: sel.d $f0, $f13, $f12
-
- ; MM32R3: lw $[[T0:[0-9]+]], 16($sp)
- ; MM32R3: andi16 $[[T1:[0-9]+]], $[[T0:[0-9]+]], 1
- ; MM32R3: movn.d $f14, $f12, $[[T1]]
- ; MM32R3: mov.d $f0, $f14
-
%r = select i1 %s, double %x, double %y
ret double %r
}
define double @tst_select_fcmp_olt_double(double %x, double %y) {
+; M2-LABEL: tst_select_fcmp_olt_double:
+; M2: # %bb.0: # %entry
+; M2-NEXT: c.olt.d $f12, $f14
+; M2-NEXT: bc1t $BB2_2
+; M2-NEXT: nop
+; M2-NEXT: # %bb.1: # %entry
+; M2-NEXT: mov.d $f12, $f14
+; M2-NEXT: $BB2_2: # %entry
+; M2-NEXT: jr $ra
+; M2-NEXT: mov.d $f0, $f12
+;
+; CMOV32R1-LABEL: tst_select_fcmp_olt_double:
+; CMOV32R1: # %bb.0: # %entry
+; CMOV32R1-NEXT: c.olt.d $f12, $f14
+; CMOV32R1-NEXT: movt.d $f14, $f12, $fcc0
+; CMOV32R1-NEXT: jr $ra
+; CMOV32R1-NEXT: mov.d $f0, $f14
+;
+; CMOV32R2-LABEL: tst_select_fcmp_olt_double:
+; CMOV32R2: # %bb.0: # %entry
+; CMOV32R2-NEXT: c.olt.d $f12, $f14
+; CMOV32R2-NEXT: movt.d $f14, $f12, $fcc0
+; CMOV32R2-NEXT: jr $ra
+; CMOV32R2-NEXT: mov.d $f0, $f14
+;
+; 32R6-LABEL: tst_select_fcmp_olt_double:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: cmp.lt.d $f0, $f12, $f14
+; 32R6-NEXT: mfc1 $1, $f0
+; 32R6-NEXT: mtc1 $1, $f0
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: sel.d $f0, $f14, $f12
+;
+; M3-LABEL: tst_select_fcmp_olt_double:
+; M3: # %bb.0: # %entry
+; M3-NEXT: c.olt.d $f12, $f13
+; M3-NEXT: bc1t .LBB2_2
+; M3-NEXT: nop
+; M3-NEXT: # %bb.1: # %entry
+; M3-NEXT: mov.d $f12, $f13
+; M3-NEXT: .LBB2_2: # %entry
+; M3-NEXT: jr $ra
+; M3-NEXT: mov.d $f0, $f12
+;
+; CMOV64-LABEL: tst_select_fcmp_olt_double:
+; CMOV64: # %bb.0: # %entry
+; CMOV64-NEXT: c.olt.d $f12, $f13
+; CMOV64-NEXT: movt.d $f13, $f12, $fcc0
+; CMOV64-NEXT: jr $ra
+; CMOV64-NEXT: mov.d $f0, $f13
+;
+; 64R6-LABEL: tst_select_fcmp_olt_double:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: cmp.lt.d $f0, $f12, $f13
+; 64R6-NEXT: mfc1 $1, $f0
+; 64R6-NEXT: mtc1 $1, $f0
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: sel.d $f0, $f13, $f12
+;
+; MM32R3-LABEL: tst_select_fcmp_olt_double:
+; MM32R3: # %bb.0: # %entry
+; MM32R3-NEXT: c.olt.d $f12, $f14
+; MM32R3-NEXT: movt.d $f14, $f12, $fcc0
+; MM32R3-NEXT: jr $ra
+; MM32R3-NEXT: mov.d $f0, $f14
+;
+; MM32R6-LABEL: tst_select_fcmp_olt_double:
+; MM32R6: # %bb.0: # %entry
+; MM32R6-NEXT: cmp.lt.d $f0, $f12, $f14
+; MM32R6-NEXT: mfc1 $1, $f0
+; MM32R6-NEXT: mtc1 $1, $f0
+; MM32R6-NEXT: sel.d $f0, $f14, $f12
+; MM32R6-NEXT: jrc $ra
entry:
- ; ALL-LABEL: tst_select_fcmp_olt_double:
-
- ; M2: c.olt.d $f12, $f14
- ; M3: c.olt.d $f12, $f13
- ; M2: bc1t [[BB0:\$BB[0-9_]+]]
- ; M3: bc1t [[BB0:\.LBB[0-9_]+]]
- ; M2-M3: nop
- ; M2: mov.d $f12, $f14
- ; M3: mov.d $f12, $f13
- ; M2-M3: [[BB0]]:
- ; M2-M3: jr $ra
- ; M2-M3: mov.d $f0, $f12
-
- ; CMOV-32: c.olt.d $f12, $f14
- ; CMOV-32: movt.d $f14, $f12, $fcc0
- ; CMOV-32: mov.d $f0, $f14
-
- ; SEL-32: cmp.lt.d $f0, $f12, $f14
- ; SEL-32: sel.d $f0, $f14, $f12
-
- ; CMOV-64: c.olt.d $f12, $f13
- ; CMOV-64: movt.d $f13, $f12, $fcc0
- ; CMOV-64: mov.d $f0, $f13
-
- ; SEL-64: cmp.lt.d $f0, $f12, $f13
- ; SEL-64: sel.d $f0, $f13, $f12
-
- ; MM32R3: c.olt.d $f12, $f14
- ; MM32R3: movt.d $f14, $f12, $fcc0
- ; MM32R3: mov.d $f0, $f14
-
%s = fcmp olt double %x, %y
%r = select i1 %s, double %x, double %y
ret double %r
}
define double @tst_select_fcmp_ole_double(double %x, double %y) {
+; M2-LABEL: tst_select_fcmp_ole_double:
+; M2: # %bb.0: # %entry
+; M2-NEXT: c.ole.d $f12, $f14
+; M2-NEXT: bc1t $BB3_2
+; M2-NEXT: nop
+; M2-NEXT: # %bb.1: # %entry
+; M2-NEXT: mov.d $f12, $f14
+; M2-NEXT: $BB3_2: # %entry
+; M2-NEXT: jr $ra
+; M2-NEXT: mov.d $f0, $f12
+;
+; CMOV32R1-LABEL: tst_select_fcmp_ole_double:
+; CMOV32R1: # %bb.0: # %entry
+; CMOV32R1-NEXT: c.ole.d $f12, $f14
+; CMOV32R1-NEXT: movt.d $f14, $f12, $fcc0
+; CMOV32R1-NEXT: jr $ra
+; CMOV32R1-NEXT: mov.d $f0, $f14
+;
+; CMOV32R2-LABEL: tst_select_fcmp_ole_double:
+; CMOV32R2: # %bb.0: # %entry
+; CMOV32R2-NEXT: c.ole.d $f12, $f14
+; CMOV32R2-NEXT: movt.d $f14, $f12, $fcc0
+; CMOV32R2-NEXT: jr $ra
+; CMOV32R2-NEXT: mov.d $f0, $f14
+;
+; 32R6-LABEL: tst_select_fcmp_ole_double:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: cmp.le.d $f0, $f12, $f14
+; 32R6-NEXT: mfc1 $1, $f0
+; 32R6-NEXT: mtc1 $1, $f0
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: sel.d $f0, $f14, $f12
+;
+; M3-LABEL: tst_select_fcmp_ole_double:
+; M3: # %bb.0: # %entry
+; M3-NEXT: c.ole.d $f12, $f13
+; M3-NEXT: bc1t .LBB3_2
+; M3-NEXT: nop
+; M3-NEXT: # %bb.1: # %entry
+; M3-NEXT: mov.d $f12, $f13
+; M3-NEXT: .LBB3_2: # %entry
+; M3-NEXT: jr $ra
+; M3-NEXT: mov.d $f0, $f12
+;
+; CMOV64-LABEL: tst_select_fcmp_ole_double:
+; CMOV64: # %bb.0: # %entry
+; CMOV64-NEXT: c.ole.d $f12, $f13
+; CMOV64-NEXT: movt.d $f13, $f12, $fcc0
+; CMOV64-NEXT: jr $ra
+; CMOV64-NEXT: mov.d $f0, $f13
+;
+; 64R6-LABEL: tst_select_fcmp_ole_double:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: cmp.le.d $f0, $f12, $f13
+; 64R6-NEXT: mfc1 $1, $f0
+; 64R6-NEXT: mtc1 $1, $f0
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: sel.d $f0, $f13, $f12
+;
+; MM32R3-LABEL: tst_select_fcmp_ole_double:
+; MM32R3: # %bb.0: # %entry
+; MM32R3-NEXT: c.ole.d $f12, $f14
+; MM32R3-NEXT: movt.d $f14, $f12, $fcc0
+; MM32R3-NEXT: jr $ra
+; MM32R3-NEXT: mov.d $f0, $f14
+;
+; MM32R6-LABEL: tst_select_fcmp_ole_double:
+; MM32R6: # %bb.0: # %entry
+; MM32R6-NEXT: cmp.le.d $f0, $f12, $f14
+; MM32R6-NEXT: mfc1 $1, $f0
+; MM32R6-NEXT: mtc1 $1, $f0
+; MM32R6-NEXT: sel.d $f0, $f14, $f12
+; MM32R6-NEXT: jrc $ra
entry:
- ; ALL-LABEL: tst_select_fcmp_ole_double:
-
- ; M2: c.ole.d $f12, $f14
- ; M3: c.ole.d $f12, $f13
- ; M2: bc1t [[BB0:\$BB[0-9_]+]]
- ; M3: bc1t [[BB0:\.LBB[0-9_]+]]
- ; M2-M3: nop
- ; M2: mov.d $f12, $f14
- ; M3: mov.d $f12, $f13
- ; M2-M3: [[BB0]]:
- ; M2-M3: jr $ra
- ; M2-M3: mov.d $f0, $f12
-
- ; CMOV-32: c.ole.d $f12, $f14
- ; CMOV-32: movt.d $f14, $f12, $fcc0
- ; CMOV-32: mov.d $f0, $f14
-
- ; SEL-32: cmp.le.d $f0, $f12, $f14
- ; SEL-32: sel.d $f0, $f14, $f12
-
- ; CMOV-64: c.ole.d $f12, $f13
- ; CMOV-64: movt.d $f13, $f12, $fcc0
- ; CMOV-64: mov.d $f0, $f13
-
- ; SEL-64: cmp.le.d $f0, $f12, $f13
- ; SEL-64: sel.d $f0, $f13, $f12
-
- ; MM32R3: c.ole.d $f12, $f14
- ; MM32R3: movt.d $f14, $f12, $fcc0
- ; MM32R3: mov.d $f0, $f14
-
%s = fcmp ole double %x, %y
%r = select i1 %s, double %x, double %y
ret double %r
}
define double @tst_select_fcmp_ogt_double(double %x, double %y) {
+; M2-LABEL: tst_select_fcmp_ogt_double:
+; M2: # %bb.0: # %entry
+; M2-NEXT: c.ule.d $f12, $f14
+; M2-NEXT: bc1f $BB4_2
+; M2-NEXT: nop
+; M2-NEXT: # %bb.1: # %entry
+; M2-NEXT: mov.d $f12, $f14
+; M2-NEXT: $BB4_2: # %entry
+; M2-NEXT: jr $ra
+; M2-NEXT: mov.d $f0, $f12
+;
+; CMOV32R1-LABEL: tst_select_fcmp_ogt_double:
+; CMOV32R1: # %bb.0: # %entry
+; CMOV32R1-NEXT: c.ule.d $f12, $f14
+; CMOV32R1-NEXT: movf.d $f14, $f12, $fcc0
+; CMOV32R1-NEXT: jr $ra
+; CMOV32R1-NEXT: mov.d $f0, $f14
+;
+; CMOV32R2-LABEL: tst_select_fcmp_ogt_double:
+; CMOV32R2: # %bb.0: # %entry
+; CMOV32R2-NEXT: c.ule.d $f12, $f14
+; CMOV32R2-NEXT: movf.d $f14, $f12, $fcc0
+; CMOV32R2-NEXT: jr $ra
+; CMOV32R2-NEXT: mov.d $f0, $f14
+;
+; 32R6-LABEL: tst_select_fcmp_ogt_double:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: cmp.lt.d $f0, $f14, $f12
+; 32R6-NEXT: mfc1 $1, $f0
+; 32R6-NEXT: mtc1 $1, $f0
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: sel.d $f0, $f14, $f12
+;
+; M3-LABEL: tst_select_fcmp_ogt_double:
+; M3: # %bb.0: # %entry
+; M3-NEXT: c.ule.d $f12, $f13
+; M3-NEXT: bc1f .LBB4_2
+; M3-NEXT: nop
+; M3-NEXT: # %bb.1: # %entry
+; M3-NEXT: mov.d $f12, $f13
+; M3-NEXT: .LBB4_2: # %entry
+; M3-NEXT: jr $ra
+; M3-NEXT: mov.d $f0, $f12
+;
+; CMOV64-LABEL: tst_select_fcmp_ogt_double:
+; CMOV64: # %bb.0: # %entry
+; CMOV64-NEXT: c.ule.d $f12, $f13
+; CMOV64-NEXT: movf.d $f13, $f12, $fcc0
+; CMOV64-NEXT: jr $ra
+; CMOV64-NEXT: mov.d $f0, $f13
+;
+; 64R6-LABEL: tst_select_fcmp_ogt_double:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: cmp.lt.d $f0, $f13, $f12
+; 64R6-NEXT: mfc1 $1, $f0
+; 64R6-NEXT: mtc1 $1, $f0
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: sel.d $f0, $f13, $f12
+;
+; MM32R3-LABEL: tst_select_fcmp_ogt_double:
+; MM32R3: # %bb.0: # %entry
+; MM32R3-NEXT: c.ule.d $f12, $f14
+; MM32R3-NEXT: movf.d $f14, $f12, $fcc0
+; MM32R3-NEXT: jr $ra
+; MM32R3-NEXT: mov.d $f0, $f14
+;
+; MM32R6-LABEL: tst_select_fcmp_ogt_double:
+; MM32R6: # %bb.0: # %entry
+; MM32R6-NEXT: cmp.lt.d $f0, $f14, $f12
+; MM32R6-NEXT: mfc1 $1, $f0
+; MM32R6-NEXT: mtc1 $1, $f0
+; MM32R6-NEXT: sel.d $f0, $f14, $f12
+; MM32R6-NEXT: jrc $ra
entry:
- ; ALL-LABEL: tst_select_fcmp_ogt_double:
-
- ; M2: c.ule.d $f12, $f14
- ; M3: c.ule.d $f12, $f13
- ; M2: bc1f [[BB0:\$BB[0-9_]+]]
- ; M3: bc1f [[BB0:\.LBB[0-9_]+]]
- ; M2-M3: nop
- ; M2: mov.d $f12, $f14
- ; M3: mov.d $f12, $f13
- ; M2-M3: [[BB0]]:
- ; M2-M3: jr $ra
- ; M2-M3: mov.d $f0, $f12
-
- ; CMOV-32: c.ule.d $f12, $f14
- ; CMOV-32: movf.d $f14, $f12, $fcc0
- ; CMOV-32: mov.d $f0, $f14
-
- ; SEL-32: cmp.lt.d $f0, $f14, $f12
- ; SEL-32: sel.d $f0, $f14, $f12
-
- ; CMOV-64: c.ule.d $f12, $f13
- ; CMOV-64: movf.d $f13, $f12, $fcc0
- ; CMOV-64: mov.d $f0, $f13
-
- ; SEL-64: cmp.lt.d $f0, $f13, $f12
- ; SEL-64: sel.d $f0, $f13, $f12
-
- ; MM32R3: c.ule.d $f12, $f14
- ; MM32R3: movf.d $f14, $f12, $fcc0
- ; MM32R3: mov.d $f0, $f14
-
%s = fcmp ogt double %x, %y
%r = select i1 %s, double %x, double %y
ret double %r
}
define double @tst_select_fcmp_oge_double(double %x, double %y) {
+; M2-LABEL: tst_select_fcmp_oge_double:
+; M2: # %bb.0: # %entry
+; M2-NEXT: c.ult.d $f12, $f14
+; M2-NEXT: bc1f $BB5_2
+; M2-NEXT: nop
+; M2-NEXT: # %bb.1: # %entry
+; M2-NEXT: mov.d $f12, $f14
+; M2-NEXT: $BB5_2: # %entry
+; M2-NEXT: jr $ra
+; M2-NEXT: mov.d $f0, $f12
+;
+; CMOV32R1-LABEL: tst_select_fcmp_oge_double:
+; CMOV32R1: # %bb.0: # %entry
+; CMOV32R1-NEXT: c.ult.d $f12, $f14
+; CMOV32R1-NEXT: movf.d $f14, $f12, $fcc0
+; CMOV32R1-NEXT: jr $ra
+; CMOV32R1-NEXT: mov.d $f0, $f14
+;
+; CMOV32R2-LABEL: tst_select_fcmp_oge_double:
+; CMOV32R2: # %bb.0: # %entry
+; CMOV32R2-NEXT: c.ult.d $f12, $f14
+; CMOV32R2-NEXT: movf.d $f14, $f12, $fcc0
+; CMOV32R2-NEXT: jr $ra
+; CMOV32R2-NEXT: mov.d $f0, $f14
+;
+; 32R6-LABEL: tst_select_fcmp_oge_double:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: cmp.le.d $f0, $f14, $f12
+; 32R6-NEXT: mfc1 $1, $f0
+; 32R6-NEXT: mtc1 $1, $f0
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: sel.d $f0, $f14, $f12
+;
+; M3-LABEL: tst_select_fcmp_oge_double:
+; M3: # %bb.0: # %entry
+; M3-NEXT: c.ult.d $f12, $f13
+; M3-NEXT: bc1f .LBB5_2
+; M3-NEXT: nop
+; M3-NEXT: # %bb.1: # %entry
+; M3-NEXT: mov.d $f12, $f13
+; M3-NEXT: .LBB5_2: # %entry
+; M3-NEXT: jr $ra
+; M3-NEXT: mov.d $f0, $f12
+;
+; CMOV64-LABEL: tst_select_fcmp_oge_double:
+; CMOV64: # %bb.0: # %entry
+; CMOV64-NEXT: c.ult.d $f12, $f13
+; CMOV64-NEXT: movf.d $f13, $f12, $fcc0
+; CMOV64-NEXT: jr $ra
+; CMOV64-NEXT: mov.d $f0, $f13
+;
+; 64R6-LABEL: tst_select_fcmp_oge_double:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: cmp.le.d $f0, $f13, $f12
+; 64R6-NEXT: mfc1 $1, $f0
+; 64R6-NEXT: mtc1 $1, $f0
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: sel.d $f0, $f13, $f12
+;
+; MM32R3-LABEL: tst_select_fcmp_oge_double:
+; MM32R3: # %bb.0: # %entry
+; MM32R3-NEXT: c.ult.d $f12, $f14
+; MM32R3-NEXT: movf.d $f14, $f12, $fcc0
+; MM32R3-NEXT: jr $ra
+; MM32R3-NEXT: mov.d $f0, $f14
+;
+; MM32R6-LABEL: tst_select_fcmp_oge_double:
+; MM32R6: # %bb.0: # %entry
+; MM32R6-NEXT: cmp.le.d $f0, $f14, $f12
+; MM32R6-NEXT: mfc1 $1, $f0
+; MM32R6-NEXT: mtc1 $1, $f0
+; MM32R6-NEXT: sel.d $f0, $f14, $f12
+; MM32R6-NEXT: jrc $ra
entry:
- ; ALL-LABEL: tst_select_fcmp_oge_double:
-
- ; M2: c.ult.d $f12, $f14
- ; M3: c.ult.d $f12, $f13
- ; M2: bc1f [[BB0:\$BB[0-9_]+]]
- ; M3: bc1f [[BB0:\.LBB[0-9_]+]]
- ; M2-M3: nop
- ; M2: mov.d $f12, $f14
- ; M3: mov.d $f12, $f13
- ; M2-M3: [[BB0]]:
- ; M2-M3: jr $ra
- ; M2-M3: mov.d $f0, $f12
-
- ; CMOV-32: c.ult.d $f12, $f14
- ; CMOV-32: movf.d $f14, $f12, $fcc0
- ; CMOV-32: mov.d $f0, $f14
-
- ; SEL-32: cmp.le.d $f0, $f14, $f12
- ; SEL-32: sel.d $f0, $f14, $f12
-
- ; CMOV-64: c.ult.d $f12, $f13
- ; CMOV-64: movf.d $f13, $f12, $fcc0
- ; CMOV-64: mov.d $f0, $f13
-
- ; SEL-64: cmp.le.d $f0, $f13, $f12
- ; SEL-64: sel.d $f0, $f13, $f12
-
- ; MM32R3: c.ult.d $f12, $f14
- ; MM32R3: movf.d $f14, $f12, $fcc0
- ; MM32R3: mov.d $f0, $f14
-
%s = fcmp oge double %x, %y
%r = select i1 %s, double %x, double %y
ret double %r
}
define double @tst_select_fcmp_oeq_double(double %x, double %y) {
+; M2-LABEL: tst_select_fcmp_oeq_double:
+; M2: # %bb.0: # %entry
+; M2-NEXT: c.eq.d $f12, $f14
+; M2-NEXT: bc1t $BB6_2
+; M2-NEXT: nop
+; M2-NEXT: # %bb.1: # %entry
+; M2-NEXT: mov.d $f12, $f14
+; M2-NEXT: $BB6_2: # %entry
+; M2-NEXT: jr $ra
+; M2-NEXT: mov.d $f0, $f12
+;
+; CMOV32R1-LABEL: tst_select_fcmp_oeq_double:
+; CMOV32R1: # %bb.0: # %entry
+; CMOV32R1-NEXT: c.eq.d $f12, $f14
+; CMOV32R1-NEXT: movt.d $f14, $f12, $fcc0
+; CMOV32R1-NEXT: jr $ra
+; CMOV32R1-NEXT: mov.d $f0, $f14
+;
+; CMOV32R2-LABEL: tst_select_fcmp_oeq_double:
+; CMOV32R2: # %bb.0: # %entry
+; CMOV32R2-NEXT: c.eq.d $f12, $f14
+; CMOV32R2-NEXT: movt.d $f14, $f12, $fcc0
+; CMOV32R2-NEXT: jr $ra
+; CMOV32R2-NEXT: mov.d $f0, $f14
+;
+; 32R6-LABEL: tst_select_fcmp_oeq_double:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: cmp.eq.d $f0, $f12, $f14
+; 32R6-NEXT: mfc1 $1, $f0
+; 32R6-NEXT: mtc1 $1, $f0
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: sel.d $f0, $f14, $f12
+;
+; M3-LABEL: tst_select_fcmp_oeq_double:
+; M3: # %bb.0: # %entry
+; M3-NEXT: c.eq.d $f12, $f13
+; M3-NEXT: bc1t .LBB6_2
+; M3-NEXT: nop
+; M3-NEXT: # %bb.1: # %entry
+; M3-NEXT: mov.d $f12, $f13
+; M3-NEXT: .LBB6_2: # %entry
+; M3-NEXT: jr $ra
+; M3-NEXT: mov.d $f0, $f12
+;
+; CMOV64-LABEL: tst_select_fcmp_oeq_double:
+; CMOV64: # %bb.0: # %entry
+; CMOV64-NEXT: c.eq.d $f12, $f13
+; CMOV64-NEXT: movt.d $f13, $f12, $fcc0
+; CMOV64-NEXT: jr $ra
+; CMOV64-NEXT: mov.d $f0, $f13
+;
+; 64R6-LABEL: tst_select_fcmp_oeq_double:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: cmp.eq.d $f0, $f12, $f13
+; 64R6-NEXT: mfc1 $1, $f0
+; 64R6-NEXT: mtc1 $1, $f0
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: sel.d $f0, $f13, $f12
+;
+; MM32R3-LABEL: tst_select_fcmp_oeq_double:
+; MM32R3: # %bb.0: # %entry
+; MM32R3-NEXT: c.eq.d $f12, $f14
+; MM32R3-NEXT: movt.d $f14, $f12, $fcc0
+; MM32R3-NEXT: jr $ra
+; MM32R3-NEXT: mov.d $f0, $f14
+;
+; MM32R6-LABEL: tst_select_fcmp_oeq_double:
+; MM32R6: # %bb.0: # %entry
+; MM32R6-NEXT: cmp.eq.d $f0, $f12, $f14
+; MM32R6-NEXT: mfc1 $1, $f0
+; MM32R6-NEXT: mtc1 $1, $f0
+; MM32R6-NEXT: sel.d $f0, $f14, $f12
+; MM32R6-NEXT: jrc $ra
entry:
- ; ALL-LABEL: tst_select_fcmp_oeq_double:
-
- ; M2: c.eq.d $f12, $f14
- ; M3: c.eq.d $f12, $f13
- ; M2: bc1t [[BB0:\$BB[0-9_]+]]
- ; M3: bc1t [[BB0:\.LBB[0-9_]+]]
- ; M2-M3: nop
- ; M2: mov.d $f12, $f14
- ; M3: mov.d $f12, $f13
- ; M2-M3: [[BB0]]:
- ; M2-M3: jr $ra
- ; M2-M3: mov.d $f0, $f12
-
- ; CMOV-32: c.eq.d $f12, $f14
- ; CMOV-32: movt.d $f14, $f12, $fcc0
- ; CMOV-32: mov.d $f0, $f14
-
- ; SEL-32: cmp.eq.d $f0, $f12, $f14
- ; SEL-32: sel.d $f0, $f14, $f12
-
- ; CMOV-64: c.eq.d $f12, $f13
- ; CMOV-64: movt.d $f13, $f12, $fcc0
- ; CMOV-64: mov.d $f0, $f13
-
- ; SEL-64: cmp.eq.d $f0, $f12, $f13
- ; SEL-64: sel.d $f0, $f13, $f12
-
- ; MM32R3: c.eq.d $f12, $f14
- ; MM32R3: movt.d $f14, $f12, $fcc0
- ; MM32R3: mov.d $f0, $f14
-
%s = fcmp oeq double %x, %y
%r = select i1 %s, double %x, double %y
ret double %r
}
define double @tst_select_fcmp_one_double(double %x, double %y) {
+; M2-LABEL: tst_select_fcmp_one_double:
+; M2: # %bb.0: # %entry
+; M2-NEXT: c.ueq.d $f12, $f14
+; M2-NEXT: bc1f $BB7_2
+; M2-NEXT: nop
+; M2-NEXT: # %bb.1: # %entry
+; M2-NEXT: mov.d $f12, $f14
+; M2-NEXT: $BB7_2: # %entry
+; M2-NEXT: jr $ra
+; M2-NEXT: mov.d $f0, $f12
+;
+; CMOV32R1-LABEL: tst_select_fcmp_one_double:
+; CMOV32R1: # %bb.0: # %entry
+; CMOV32R1-NEXT: c.ueq.d $f12, $f14
+; CMOV32R1-NEXT: movf.d $f14, $f12, $fcc0
+; CMOV32R1-NEXT: jr $ra
+; CMOV32R1-NEXT: mov.d $f0, $f14
+;
+; CMOV32R2-LABEL: tst_select_fcmp_one_double:
+; CMOV32R2: # %bb.0: # %entry
+; CMOV32R2-NEXT: c.ueq.d $f12, $f14
+; CMOV32R2-NEXT: movf.d $f14, $f12, $fcc0
+; CMOV32R2-NEXT: jr $ra
+; CMOV32R2-NEXT: mov.d $f0, $f14
+;
+; 32R6-LABEL: tst_select_fcmp_one_double:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: cmp.ueq.d $f0, $f12, $f14
+; 32R6-NEXT: mfc1 $1, $f0
+; 32R6-NEXT: not $1, $1
+; 32R6-NEXT: mtc1 $1, $f0
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: sel.d $f0, $f14, $f12
+;
+; M3-LABEL: tst_select_fcmp_one_double:
+; M3: # %bb.0: # %entry
+; M3-NEXT: c.ueq.d $f12, $f13
+; M3-NEXT: bc1f .LBB7_2
+; M3-NEXT: nop
+; M3-NEXT: # %bb.1: # %entry
+; M3-NEXT: mov.d $f12, $f13
+; M3-NEXT: .LBB7_2: # %entry
+; M3-NEXT: jr $ra
+; M3-NEXT: mov.d $f0, $f12
+;
+; CMOV64-LABEL: tst_select_fcmp_one_double:
+; CMOV64: # %bb.0: # %entry
+; CMOV64-NEXT: c.ueq.d $f12, $f13
+; CMOV64-NEXT: movf.d $f13, $f12, $fcc0
+; CMOV64-NEXT: jr $ra
+; CMOV64-NEXT: mov.d $f0, $f13
+;
+; 64R6-LABEL: tst_select_fcmp_one_double:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: cmp.ueq.d $f0, $f12, $f13
+; 64R6-NEXT: mfc1 $1, $f0
+; 64R6-NEXT: not $1, $1
+; 64R6-NEXT: mtc1 $1, $f0
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: sel.d $f0, $f13, $f12
+;
+; MM32R3-LABEL: tst_select_fcmp_one_double:
+; MM32R3: # %bb.0: # %entry
+; MM32R3-NEXT: c.ueq.d $f12, $f14
+; MM32R3-NEXT: movf.d $f14, $f12, $fcc0
+; MM32R3-NEXT: jr $ra
+; MM32R3-NEXT: mov.d $f0, $f14
+;
+; MM32R6-LABEL: tst_select_fcmp_one_double:
+; MM32R6: # %bb.0: # %entry
+; MM32R6-NEXT: cmp.ueq.d $f0, $f12, $f14
+; MM32R6-NEXT: mfc1 $1, $f0
+; MM32R6-NEXT: not $1, $1
+; MM32R6-NEXT: mtc1 $1, $f0
+; MM32R6-NEXT: sel.d $f0, $f14, $f12
+; MM32R6-NEXT: jrc $ra
entry:
- ; ALL-LABEL: tst_select_fcmp_one_double:
-
- ; M2: c.ueq.d $f12, $f14
- ; M3: c.ueq.d $f12, $f13
- ; M2: bc1f [[BB0:\$BB[0-9_]+]]
- ; M3: bc1f [[BB0:\.LBB[0-9_]+]]
- ; M2-M3: nop
- ; M2: mov.d $f12, $f14
- ; M3: mov.d $f12, $f13
- ; M2-M3: [[BB0]]:
- ; M2-M3: jr $ra
- ; M2-M3: mov.d $f0, $f12
-
- ; CMOV-32: c.ueq.d $f12, $f14
- ; CMOV-32: movf.d $f14, $f12, $fcc0
- ; CMOV-32: mov.d $f0, $f14
-
- ; SEL-32: cmp.ueq.d $f0, $f12, $f14
- ; SEL-32: mfc1 $[[T0:[0-9]+]], $f0
- ; SEL-32: not $[[T0]], $[[T0]]
- ; SEL-32: mtc1 $[[T0:[0-9]+]], $f0
- ; SEL-32: sel.d $f0, $f14, $f12
-
- ; CMOV-64: c.ueq.d $f12, $f13
- ; CMOV-64: movf.d $f13, $f12, $fcc0
- ; CMOV-64: mov.d $f0, $f13
-
- ; SEL-64: cmp.ueq.d $f0, $f12, $f13
- ; SEL-64: mfc1 $[[T0:[0-9]+]], $f0
- ; SEL-64: not $[[T0]], $[[T0]]
- ; SEL-64: mtc1 $[[T0:[0-9]+]], $f0
- ; SEL-64: sel.d $f0, $f13, $f12
-
- ; MM32R3: c.ueq.d $f12, $f14
- ; MM32R3: movf.d $f14, $f12, $fcc0
- ; MM32R3: mov.d $f0, $f14
-
%s = fcmp one double %x, %y
%r = select i1 %s, double %x, double %y
ret double %r
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll b/llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll
index 2b3a9b689c0..c0ac43f662f 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll
@@ -1,342 +1,638 @@
-; RUN: llc < %s -march=mips -mcpu=mips2 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,M2,M2-M3
-; RUN: llc < %s -march=mips -mcpu=mips32 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R1
-; RUN: llc < %s -march=mips -mcpu=mips32r2 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
-; RUN: llc < %s -march=mips -mcpu=mips32r3 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
-; RUN: llc < %s -march=mips -mcpu=mips32r5 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
-; RUN: llc < %s -march=mips -mcpu=mips32r6 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,SEL-32,32R6
-; RUN: llc < %s -march=mips64 -mcpu=mips3 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,M3,M2-M3
-; RUN: llc < %s -march=mips64 -mcpu=mips4 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,CMOV,CMOV-64
-; RUN: llc < %s -march=mips64 -mcpu=mips64 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,CMOV,CMOV-64
-; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,CMOV,CMOV-64
-; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,CMOV,CMOV-64
-; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,CMOV,CMOV-64
-; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,SEL-64,64R6
-; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,MM32R3
-; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=ALL,MM32R6,SEL-32
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips2 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefixes=M2
+; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefixes=CMOV32R1
+; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r2 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefixes=CMOV32R2
+; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefixes=CMOV32R2
+; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r5 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefixes=CMOV32R2
+; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefixes=32R6
+; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips3 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefixes=M3
+; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips4 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefixes=CMOV64
+; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefixes=CMOV64
+; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r2 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefixes=CMOV64
+; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r3 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefixes=CMOV64
+; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r5 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefixes=CMOV64
+; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r6 -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefixes=64R6
+; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -mattr=+micromips -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefixes=MM32R3
+; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs | FileCheck %s \
+; RUN: -check-prefixes=MM32R6
define float @tst_select_i1_float(i1 signext %s, float %x, float %y) {
+; M2-LABEL: tst_select_i1_float:
+; M2: # %bb.0: # %entry
+; M2-NEXT: andi $1, $4, 1
+; M2-NEXT: bnez $1, $BB0_2
+; M2-NEXT: nop
+; M2-NEXT: # %bb.1: # %entry
+; M2-NEXT: jr $ra
+; M2-NEXT: mtc1 $6, $f0
+; M2-NEXT: $BB0_2:
+; M2-NEXT: jr $ra
+; M2-NEXT: mtc1 $5, $f0
+;
+; CMOV32R1-LABEL: tst_select_i1_float:
+; CMOV32R1: # %bb.0: # %entry
+; CMOV32R1-NEXT: mtc1 $6, $f0
+; CMOV32R1-NEXT: andi $1, $4, 1
+; CMOV32R1-NEXT: mtc1 $5, $f1
+; CMOV32R1-NEXT: jr $ra
+; CMOV32R1-NEXT: movn.s $f0, $f1, $1
+;
+; CMOV32R2-LABEL: tst_select_i1_float:
+; CMOV32R2: # %bb.0: # %entry
+; CMOV32R2-NEXT: mtc1 $6, $f0
+; CMOV32R2-NEXT: andi $1, $4, 1
+; CMOV32R2-NEXT: mtc1 $5, $f1
+; CMOV32R2-NEXT: jr $ra
+; CMOV32R2-NEXT: movn.s $f0, $f1, $1
+;
+; 32R6-LABEL: tst_select_i1_float:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: mtc1 $5, $f1
+; 32R6-NEXT: mtc1 $6, $f2
+; 32R6-NEXT: mtc1 $4, $f0
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: sel.s $f0, $f2, $f1
+;
+; M3-LABEL: tst_select_i1_float:
+; M3: # %bb.0: # %entry
+; M3-NEXT: andi $1, $4, 1
+; M3-NEXT: bnez $1, .LBB0_2
+; M3-NEXT: nop
+; M3-NEXT: # %bb.1: # %entry
+; M3-NEXT: mov.s $f13, $f14
+; M3-NEXT: .LBB0_2: # %entry
+; M3-NEXT: jr $ra
+; M3-NEXT: mov.s $f0, $f13
+;
+; CMOV64-LABEL: tst_select_i1_float:
+; CMOV64: # %bb.0: # %entry
+; CMOV64-NEXT: andi $1, $4, 1
+; CMOV64-NEXT: movn.s $f14, $f13, $1
+; CMOV64-NEXT: jr $ra
+; CMOV64-NEXT: mov.s $f0, $f14
+;
+; 64R6-LABEL: tst_select_i1_float:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: mtc1 $4, $f0
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: sel.s $f0, $f14, $f13
+;
+; MM32R3-LABEL: tst_select_i1_float:
+; MM32R3: # %bb.0: # %entry
+; MM32R3-NEXT: mtc1 $6, $f0
+; MM32R3-NEXT: andi16 $2, $4, 1
+; MM32R3-NEXT: mtc1 $5, $f1
+; MM32R3-NEXT: jr $ra
+; MM32R3-NEXT: movn.s $f0, $f1, $2
+;
+; MM32R6-LABEL: tst_select_i1_float:
+; MM32R6: # %bb.0: # %entry
+; MM32R6-NEXT: mtc1 $5, $f1
+; MM32R6-NEXT: mtc1 $6, $f2
+; MM32R6-NEXT: mtc1 $4, $f0
+; MM32R6-NEXT: sel.s $f0, $f2, $f1
+; MM32R6-NEXT: jrc $ra
entry:
- ; ALL-LABEL: tst_select_i1_float:
-
- ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
- ; M2: bnez $[[T0]], [[BB0:\$BB[0-9_]+]]
- ; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
- ; M2-M3: nop
- ; M2: jr $ra
- ; M2: mtc1 $6, $f0
- ; M3: mov.s $f13, $f14
- ; M2-M3: [[BB0]]:
- ; M2-M3: jr $ra
- ; M2: mtc1 $5, $f0
- ; M3: mov.s $f0, $f13
-
- ; CMOV-32: mtc1 $6, $f0
- ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1
- ; CMOV-32: mtc1 $5, $f1
- ; CMOV-32: movn.s $f0, $f1, $[[T0]]
-
- ; SEL-32: mtc1 $5, $[[F0:f[0-9]+]]
- ; SEL-32: mtc1 $6, $[[F1:f[0-9]+]]
- ; SEL-32: mtc1 $4, $f0
- ; SEL-32: sel.s $f0, $[[F1]], $[[F0]]
-
- ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1
- ; CMOV-64: movn.s $f14, $f13, $[[T0]]
- ; CMOV-64: mov.s $f0, $f14
-
- ; SEL-64: mtc1 $4, $f0
- ; SEL-64: sel.s $f0, $f14, $f13
-
- ; MM32R3: mtc1 $6, $[[F0:f[0-9]+]]
- ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1
- ; MM32R3: mtc1 $5, $[[F1:f[0-9]+]]
- ; MM32R3: movn.s $f0, $[[F1]], $[[T0]]
-
%r = select i1 %s, float %x, float %y
ret float %r
}
define float @tst_select_i1_float_reordered(float %x, float %y,
+; M2-LABEL: tst_select_i1_float_reordered:
+; M2: # %bb.0: # %entry
+; M2-NEXT: andi $1, $6, 1
+; M2-NEXT: bnez $1, $BB1_2
+; M2-NEXT: nop
+; M2-NEXT: # %bb.1: # %entry
+; M2-NEXT: mov.s $f12, $f14
+; M2-NEXT: $BB1_2: # %entry
+; M2-NEXT: jr $ra
+; M2-NEXT: mov.s $f0, $f12
+;
+; CMOV32R1-LABEL: tst_select_i1_float_reordered:
+; CMOV32R1: # %bb.0: # %entry
+; CMOV32R1-NEXT: andi $1, $6, 1
+; CMOV32R1-NEXT: movn.s $f14, $f12, $1
+; CMOV32R1-NEXT: jr $ra
+; CMOV32R1-NEXT: mov.s $f0, $f14
+;
+; CMOV32R2-LABEL: tst_select_i1_float_reordered:
+; CMOV32R2: # %bb.0: # %entry
+; CMOV32R2-NEXT: andi $1, $6, 1
+; CMOV32R2-NEXT: movn.s $f14, $f12, $1
+; CMOV32R2-NEXT: jr $ra
+; CMOV32R2-NEXT: mov.s $f0, $f14
+;
+; 32R6-LABEL: tst_select_i1_float_reordered:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: mtc1 $6, $f0
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: sel.s $f0, $f14, $f12
+;
+; M3-LABEL: tst_select_i1_float_reordered:
+; M3: # %bb.0: # %entry
+; M3-NEXT: andi $1, $6, 1
+; M3-NEXT: bnez $1, .LBB1_2
+; M3-NEXT: nop
+; M3-NEXT: # %bb.1: # %entry
+; M3-NEXT: mov.s $f12, $f13
+; M3-NEXT: .LBB1_2: # %entry
+; M3-NEXT: jr $ra
+; M3-NEXT: mov.s $f0, $f12
+;
+; CMOV64-LABEL: tst_select_i1_float_reordered:
+; CMOV64: # %bb.0: # %entry
+; CMOV64-NEXT: andi $1, $6, 1
+; CMOV64-NEXT: movn.s $f13, $f12, $1
+; CMOV64-NEXT: jr $ra
+; CMOV64-NEXT: mov.s $f0, $f13
+;
+; 64R6-LABEL: tst_select_i1_float_reordered:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: mtc1 $6, $f0
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: sel.s $f0, $f13, $f12
+;
+; MM32R3-LABEL: tst_select_i1_float_reordered:
+; MM32R3: # %bb.0: # %entry
+; MM32R3-NEXT: andi16 $2, $6, 1
+; MM32R3-NEXT: movn.s $f14, $f12, $2
+; MM32R3-NEXT: jr $ra
+; MM32R3-NEXT: mov.s $f0, $f14
+;
+; MM32R6-LABEL: tst_select_i1_float_reordered:
+; MM32R6: # %bb.0: # %entry
+; MM32R6-NEXT: mtc1 $6, $f0
+; MM32R6-NEXT: sel.s $f0, $f14, $f12
+; MM32R6-NEXT: jrc $ra
i1 signext %s) {
entry:
- ; ALL-LABEL: tst_select_i1_float_reordered:
-
- ; M2-M3: andi $[[T0:[0-9]+]], $6, 1
- ; M2: bnez $[[T0]], [[BB0:\$BB[0-9_]+]]
- ; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
- ; M2-M3: nop
- ; M2: mov.s $f12, $f14
- ; M3: mov.s $f12, $f13
- ; M2-M3: [[BB0]]:
- ; M2-M3: jr $ra
- ; M2-M3: mov.s $f0, $f12
-
- ; CMOV-32: andi $[[T0:[0-9]+]], $6, 1
- ; CMOV-32: movn.s $f14, $f12, $[[T0]]
- ; CMOV-32: mov.s $f0, $f14
-
- ; SEL-32: mtc1 $6, $f0
- ; SEL-32: sel.s $f0, $f14, $f12
-
- ; CMOV-64: andi $[[T0:[0-9]+]], $6, 1
- ; CMOV-64: movn.s $f13, $f12, $[[T0]]
- ; CMOV-64: mov.s $f0, $f13
-
- ; SEL-64: mtc1 $6, $f0
- ; SEL-64: sel.s $f0, $f13, $f12
-
- ; MM32R3: andi16 $[[T0:[0-9]+]], $6, 1
- ; MM32R3: movn.s $[[F0:f[0-9]+]], $f12, $[[T0]]
- ; MM32R3: mov.s $f0, $[[F0]]
-
%r = select i1 %s, float %x, float %y
ret float %r
}
define float @tst_select_fcmp_olt_float(float %x, float %y) {
+; M2-LABEL: tst_select_fcmp_olt_float:
+; M2: # %bb.0: # %entry
+; M2-NEXT: c.olt.s $f12, $f14
+; M2-NEXT: bc1t $BB2_2
+; M2-NEXT: nop
+; M2-NEXT: # %bb.1: # %entry
+; M2-NEXT: mov.s $f12, $f14
+; M2-NEXT: $BB2_2: # %entry
+; M2-NEXT: jr $ra
+; M2-NEXT: mov.s $f0, $f12
+;
+; CMOV32R1-LABEL: tst_select_fcmp_olt_float:
+; CMOV32R1: # %bb.0: # %entry
+; CMOV32R1-NEXT: c.olt.s $f12, $f14
+; CMOV32R1-NEXT: movt.s $f14, $f12, $fcc0
+; CMOV32R1-NEXT: jr $ra
+; CMOV32R1-NEXT: mov.s $f0, $f14
+;
+; CMOV32R2-LABEL: tst_select_fcmp_olt_float:
+; CMOV32R2: # %bb.0: # %entry
+; CMOV32R2-NEXT: c.olt.s $f12, $f14
+; CMOV32R2-NEXT: movt.s $f14, $f12, $fcc0
+; CMOV32R2-NEXT: jr $ra
+; CMOV32R2-NEXT: mov.s $f0, $f14
+;
+; 32R6-LABEL: tst_select_fcmp_olt_float:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: cmp.lt.s $f0, $f12, $f14
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: sel.s $f0, $f14, $f12
+;
+; M3-LABEL: tst_select_fcmp_olt_float:
+; M3: # %bb.0: # %entry
+; M3-NEXT: c.olt.s $f12, $f13
+; M3-NEXT: bc1t .LBB2_2
+; M3-NEXT: nop
+; M3-NEXT: # %bb.1: # %entry
+; M3-NEXT: mov.s $f12, $f13
+; M3-NEXT: .LBB2_2: # %entry
+; M3-NEXT: jr $ra
+; M3-NEXT: mov.s $f0, $f12
+;
+; CMOV64-LABEL: tst_select_fcmp_olt_float:
+; CMOV64: # %bb.0: # %entry
+; CMOV64-NEXT: c.olt.s $f12, $f13
+; CMOV64-NEXT: movt.s $f13, $f12, $fcc0
+; CMOV64-NEXT: jr $ra
+; CMOV64-NEXT: mov.s $f0, $f13
+;
+; 64R6-LABEL: tst_select_fcmp_olt_float:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: cmp.lt.s $f0, $f12, $f13
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: sel.s $f0, $f13, $f12
+;
+; MM32R3-LABEL: tst_select_fcmp_olt_float:
+; MM32R3: # %bb.0: # %entry
+; MM32R3-NEXT: c.olt.s $f12, $f14
+; MM32R3-NEXT: movt.s $f14, $f12, $fcc0
+; MM32R3-NEXT: jr $ra
+; MM32R3-NEXT: mov.s $f0, $f14
+;
+; MM32R6-LABEL: tst_select_fcmp_olt_float:
+; MM32R6: # %bb.0: # %entry
+; MM32R6-NEXT: cmp.lt.s $f0, $f12, $f14
+; MM32R6-NEXT: sel.s $f0, $f14, $f12
+; MM32R6-NEXT: jrc $ra
entry:
- ; ALL-LABEL: tst_select_fcmp_olt_float:
-
- ; M2: c.olt.s $f12, $f14
- ; M3: c.olt.s $f12, $f13
- ; M2: bc1t [[BB0:\$BB[0-9_]+]]
- ; M3: bc1t [[BB0:\.LBB[0-9_]+]]
- ; M2-M3: nop
- ; M2: mov.s $f12, $f14
- ; M3: mov.s $f12, $f13
- ; M2-M3: [[BB0]]:
- ; M2-M3: jr $ra
- ; M2-M3: mov.s $f0, $f12
-
- ; CMOV-32: c.olt.s $f12, $f14
- ; CMOV-32: movt.s $f14, $f12, $fcc0
- ; CMOV-32: mov.s $f0, $f14
-
- ; SEL-32: cmp.lt.s $f0, $f12, $f14
- ; SEL-32: sel.s $f0, $f14, $f12
-
- ; CMOV-64: c.olt.s $f12, $f13
- ; CMOV-64: movt.s $f13, $f12, $fcc0
- ; CMOV-64: mov.s $f0, $f13
-
- ; SEL-64: cmp.lt.s $f0, $f12, $f13
- ; SEL-64: sel.s $f0, $f13, $f12
-
- ; MM32R3: c.olt.s $f12, $f14
- ; MM32R3: movt.s $f14, $f12, $fcc0
- ; MM32R3: mov.s $f0, $f14
-
%s = fcmp olt float %x, %y
%r = select i1 %s, float %x, float %y
ret float %r
}
define float @tst_select_fcmp_ole_float(float %x, float %y) {
+; M2-LABEL: tst_select_fcmp_ole_float:
+; M2: # %bb.0: # %entry
+; M2-NEXT: c.ole.s $f12, $f14
+; M2-NEXT: bc1t $BB3_2
+; M2-NEXT: nop
+; M2-NEXT: # %bb.1: # %entry
+; M2-NEXT: mov.s $f12, $f14
+; M2-NEXT: $BB3_2: # %entry
+; M2-NEXT: jr $ra
+; M2-NEXT: mov.s $f0, $f12
+;
+; CMOV32R1-LABEL: tst_select_fcmp_ole_float:
+; CMOV32R1: # %bb.0: # %entry
+; CMOV32R1-NEXT: c.ole.s $f12, $f14
+; CMOV32R1-NEXT: movt.s $f14, $f12, $fcc0
+; CMOV32R1-NEXT: jr $ra
+; CMOV32R1-NEXT: mov.s $f0, $f14
+;
+; CMOV32R2-LABEL: tst_select_fcmp_ole_float:
+; CMOV32R2: # %bb.0: # %entry
+; CMOV32R2-NEXT: c.ole.s $f12, $f14
+; CMOV32R2-NEXT: movt.s $f14, $f12, $fcc0
+; CMOV32R2-NEXT: jr $ra
+; CMOV32R2-NEXT: mov.s $f0, $f14
+;
+; 32R6-LABEL: tst_select_fcmp_ole_float:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: cmp.le.s $f0, $f12, $f14
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: sel.s $f0, $f14, $f12
+;
+; M3-LABEL: tst_select_fcmp_ole_float:
+; M3: # %bb.0: # %entry
+; M3-NEXT: c.ole.s $f12, $f13
+; M3-NEXT: bc1t .LBB3_2
+; M3-NEXT: nop
+; M3-NEXT: # %bb.1: # %entry
+; M3-NEXT: mov.s $f12, $f13
+; M3-NEXT: .LBB3_2: # %entry
+; M3-NEXT: jr $ra
+; M3-NEXT: mov.s $f0, $f12
+;
+; CMOV64-LABEL: tst_select_fcmp_ole_float:
+; CMOV64: # %bb.0: # %entry
+; CMOV64-NEXT: c.ole.s $f12, $f13
+; CMOV64-NEXT: movt.s $f13, $f12, $fcc0
+; CMOV64-NEXT: jr $ra
+; CMOV64-NEXT: mov.s $f0, $f13
+;
+; 64R6-LABEL: tst_select_fcmp_ole_float:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: cmp.le.s $f0, $f12, $f13
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: sel.s $f0, $f13, $f12
+;
+; MM32R3-LABEL: tst_select_fcmp_ole_float:
+; MM32R3: # %bb.0: # %entry
+; MM32R3-NEXT: c.ole.s $f12, $f14
+; MM32R3-NEXT: movt.s $f14, $f12, $fcc0
+; MM32R3-NEXT: jr $ra
+; MM32R3-NEXT: mov.s $f0, $f14
+;
+; MM32R6-LABEL: tst_select_fcmp_ole_float:
+; MM32R6: # %bb.0: # %entry
+; MM32R6-NEXT: cmp.le.s $f0, $f12, $f14
+; MM32R6-NEXT: sel.s $f0, $f14, $f12
+; MM32R6-NEXT: jrc $ra
entry:
- ; ALL-LABEL: tst_select_fcmp_ole_float:
-
- ; M2: c.ole.s $f12, $f14
- ; M3: c.ole.s $f12, $f13
- ; M2: bc1t [[BB0:\$BB[0-9_]+]]
- ; M3: bc1t [[BB0:\.LBB[0-9_]+]]
- ; M2-M3: nop
- ; M2: mov.s $f12, $f14
- ; M3: mov.s $f12, $f13
- ; M2-M3: [[BB0]]:
- ; M2-M3: jr $ra
- ; M2-M3: mov.s $f0, $f12
-
- ; CMOV-32: c.ole.s $f12, $f14
- ; CMOV-32: movt.s $f14, $f12, $fcc0
- ; CMOV-32: mov.s $f0, $f14
-
- ; SEL-32: cmp.le.s $f0, $f12, $f14
- ; SEL-32: sel.s $f0, $f14, $f12
-
- ; CMOV-64: c.ole.s $f12, $f13
- ; CMOV-64: movt.s $f13, $f12, $fcc0
- ; CMOV-64: mov.s $f0, $f13
-
- ; SEL-64: cmp.le.s $f0, $f12, $f13
- ; SEL-64: sel.s $f0, $f13, $f12
-
- ; MM32R3: c.ole.s $f12, $f14
- ; MM32R3: movt.s $f14, $f12, $fcc0
- ; MM32R3: mov.s $f0, $f14
-
%s = fcmp ole float %x, %y
%r = select i1 %s, float %x, float %y
ret float %r
}
define float @tst_select_fcmp_ogt_float(float %x, float %y) {
+; M2-LABEL: tst_select_fcmp_ogt_float:
+; M2: # %bb.0: # %entry
+; M2-NEXT: c.ule.s $f12, $f14
+; M2-NEXT: bc1f $BB4_2
+; M2-NEXT: nop
+; M2-NEXT: # %bb.1: # %entry
+; M2-NEXT: mov.s $f12, $f14
+; M2-NEXT: $BB4_2: # %entry
+; M2-NEXT: jr $ra
+; M2-NEXT: mov.s $f0, $f12
+;
+; CMOV32R1-LABEL: tst_select_fcmp_ogt_float:
+; CMOV32R1: # %bb.0: # %entry
+; CMOV32R1-NEXT: c.ule.s $f12, $f14
+; CMOV32R1-NEXT: movf.s $f14, $f12, $fcc0
+; CMOV32R1-NEXT: jr $ra
+; CMOV32R1-NEXT: mov.s $f0, $f14
+;
+; CMOV32R2-LABEL: tst_select_fcmp_ogt_float:
+; CMOV32R2: # %bb.0: # %entry
+; CMOV32R2-NEXT: c.ule.s $f12, $f14
+; CMOV32R2-NEXT: movf.s $f14, $f12, $fcc0
+; CMOV32R2-NEXT: jr $ra
+; CMOV32R2-NEXT: mov.s $f0, $f14
+;
+; 32R6-LABEL: tst_select_fcmp_ogt_float:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: cmp.lt.s $f0, $f14, $f12
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: sel.s $f0, $f14, $f12
+;
+; M3-LABEL: tst_select_fcmp_ogt_float:
+; M3: # %bb.0: # %entry
+; M3-NEXT: c.ule.s $f12, $f13
+; M3-NEXT: bc1f .LBB4_2
+; M3-NEXT: nop
+; M3-NEXT: # %bb.1: # %entry
+; M3-NEXT: mov.s $f12, $f13
+; M3-NEXT: .LBB4_2: # %entry
+; M3-NEXT: jr $ra
+; M3-NEXT: mov.s $f0, $f12
+;
+; CMOV64-LABEL: tst_select_fcmp_ogt_float:
+; CMOV64: # %bb.0: # %entry
+; CMOV64-NEXT: c.ule.s $f12, $f13
+; CMOV64-NEXT: movf.s $f13, $f12, $fcc0
+; CMOV64-NEXT: jr $ra
+; CMOV64-NEXT: mov.s $f0, $f13
+;
+; 64R6-LABEL: tst_select_fcmp_ogt_float:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: cmp.lt.s $f0, $f13, $f12
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: sel.s $f0, $f13, $f12
+;
+; MM32R3-LABEL: tst_select_fcmp_ogt_float:
+; MM32R3: # %bb.0: # %entry
+; MM32R3-NEXT: c.ule.s $f12, $f14
+; MM32R3-NEXT: movf.s $f14, $f12, $fcc0
+; MM32R3-NEXT: jr $ra
+; MM32R3-NEXT: mov.s $f0, $f14
+;
+; MM32R6-LABEL: tst_select_fcmp_ogt_float:
+; MM32R6: # %bb.0: # %entry
+; MM32R6-NEXT: cmp.lt.s $f0, $f14, $f12
+; MM32R6-NEXT: sel.s $f0, $f14, $f12
+; MM32R6-NEXT: jrc $ra
entry:
- ; ALL-LABEL: tst_select_fcmp_ogt_float:
-
- ; M2: c.ule.s $f12, $f14
- ; M3: c.ule.s $f12, $f13
- ; M2: bc1f [[BB0:\$BB[0-9_]+]]
- ; M3: bc1f [[BB0:\.LBB[0-9_]+]]
- ; M2-M3: nop
- ; M2: mov.s $f12, $f14
- ; M3: mov.s $f12, $f13
- ; M2-M3: [[BB0]]:
- ; M2-M3: jr $ra
- ; M2-M3: mov.s $f0, $f12
-
- ; CMOV-32: c.ule.s $f12, $f14
- ; CMOV-32: movf.s $f14, $f12, $fcc0
- ; CMOV-32: mov.s $f0, $f14
-
- ; SEL-32: cmp.lt.s $f0, $f14, $f12
- ; SEL-32: sel.s $f0, $f14, $f12
-
- ; CMOV-64: c.ule.s $f12, $f13
- ; CMOV-64: movf.s $f13, $f12, $fcc0
- ; CMOV-64: mov.s $f0, $f13
-
- ; SEL-64: cmp.lt.s $f0, $f13, $f12
- ; SEL-64: sel.s $f0, $f13, $f12
-
- ; MM32R3: c.ule.s $f12, $f14
- ; MM32R3: movf.s $f14, $f12, $fcc0
- ; MM32R3: mov.s $f0, $f14
-
%s = fcmp ogt float %x, %y
%r = select i1 %s, float %x, float %y
ret float %r
}
define float @tst_select_fcmp_oge_float(float %x, float %y) {
+; M2-LABEL: tst_select_fcmp_oge_float:
+; M2: # %bb.0: # %entry
+; M2-NEXT: c.ult.s $f12, $f14
+; M2-NEXT: bc1f $BB5_2
+; M2-NEXT: nop
+; M2-NEXT: # %bb.1: # %entry
+; M2-NEXT: mov.s $f12, $f14
+; M2-NEXT: $BB5_2: # %entry
+; M2-NEXT: jr $ra
+; M2-NEXT: mov.s $f0, $f12
+;
+; CMOV32R1-LABEL: tst_select_fcmp_oge_float:
+; CMOV32R1: # %bb.0: # %entry
+; CMOV32R1-NEXT: c.ult.s $f12, $f14
+; CMOV32R1-NEXT: movf.s $f14, $f12, $fcc0
+; CMOV32R1-NEXT: jr $ra
+; CMOV32R1-NEXT: mov.s $f0, $f14
+;
+; CMOV32R2-LABEL: tst_select_fcmp_oge_float:
+; CMOV32R2: # %bb.0: # %entry
+; CMOV32R2-NEXT: c.ult.s $f12, $f14
+; CMOV32R2-NEXT: movf.s $f14, $f12, $fcc0
+; CMOV32R2-NEXT: jr $ra
+; CMOV32R2-NEXT: mov.s $f0, $f14
+;
+; 32R6-LABEL: tst_select_fcmp_oge_float:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: cmp.le.s $f0, $f14, $f12
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: sel.s $f0, $f14, $f12
+;
+; M3-LABEL: tst_select_fcmp_oge_float:
+; M3: # %bb.0: # %entry
+; M3-NEXT: c.ult.s $f12, $f13
+; M3-NEXT: bc1f .LBB5_2
+; M3-NEXT: nop
+; M3-NEXT: # %bb.1: # %entry
+; M3-NEXT: mov.s $f12, $f13
+; M3-NEXT: .LBB5_2: # %entry
+; M3-NEXT: jr $ra
+; M3-NEXT: mov.s $f0, $f12
+;
+; CMOV64-LABEL: tst_select_fcmp_oge_float:
+; CMOV64: # %bb.0: # %entry
+; CMOV64-NEXT: c.ult.s $f12, $f13
+; CMOV64-NEXT: movf.s $f13, $f12, $fcc0
+; CMOV64-NEXT: jr $ra
+; CMOV64-NEXT: mov.s $f0, $f13
+;
+; 64R6-LABEL: tst_select_fcmp_oge_float:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: cmp.le.s $f0, $f13, $f12
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: sel.s $f0, $f13, $f12
+;
+; MM32R3-LABEL: tst_select_fcmp_oge_float:
+; MM32R3: # %bb.0: # %entry
+; MM32R3-NEXT: c.ult.s $f12, $f14
+; MM32R3-NEXT: movf.s $f14, $f12, $fcc0
+; MM32R3-NEXT: jr $ra
+; MM32R3-NEXT: mov.s $f0, $f14
+;
+; MM32R6-LABEL: tst_select_fcmp_oge_float:
+; MM32R6: # %bb.0: # %entry
+; MM32R6-NEXT: cmp.le.s $f0, $f14, $f12
+; MM32R6-NEXT: sel.s $f0, $f14, $f12
+; MM32R6-NEXT: jrc $ra
entry:
- ; ALL-LABEL: tst_select_fcmp_oge_float:
-
- ; M2: c.ult.s $f12, $f14
- ; M3: c.ult.s $f12, $f13
- ; M2: bc1f [[BB0:\$BB[0-9_]+]]
- ; M3: bc1f [[BB0:\.LBB[0-9_]+]]
- ; M2-M3: nop
- ; M2: mov.s $f12, $f14
- ; M3: mov.s $f12, $f13
- ; M2-M3: [[BB0]]:
- ; M2-M3: jr $ra
- ; M2-M3: mov.s $f0, $f12
-
- ; CMOV-32: c.ult.s $f12, $f14
- ; CMOV-32: movf.s $f14, $f12, $fcc0
- ; CMOV-32: mov.s $f0, $f14
-
- ; SEL-32: cmp.le.s $f0, $f14, $f12
- ; SEL-32: sel.s $f0, $f14, $f12
-
- ; CMOV-64: c.ult.s $f12, $f13
- ; CMOV-64: movf.s $f13, $f12, $fcc0
- ; CMOV-64: mov.s $f0, $f13
-
- ; SEL-64: cmp.le.s $f0, $f13, $f12
- ; SEL-64: sel.s $f0, $f13, $f12
-
- ; MM32R3: c.ult.s $f12, $f14
- ; MM32R3: movf.s $f14, $f12, $fcc0
- ; MM32R3: mov.s $f0, $f14
-
%s = fcmp oge float %x, %y
%r = select i1 %s, float %x, float %y
ret float %r
}
define float @tst_select_fcmp_oeq_float(float %x, float %y) {
+; M2-LABEL: tst_select_fcmp_oeq_float:
+; M2: # %bb.0: # %entry
+; M2-NEXT: c.eq.s $f12, $f14
+; M2-NEXT: bc1t $BB6_2
+; M2-NEXT: nop
+; M2-NEXT: # %bb.1: # %entry
+; M2-NEXT: mov.s $f12, $f14
+; M2-NEXT: $BB6_2: # %entry
+; M2-NEXT: jr $ra
+; M2-NEXT: mov.s $f0, $f12
+;
+; CMOV32R1-LABEL: tst_select_fcmp_oeq_float:
+; CMOV32R1: # %bb.0: # %entry
+; CMOV32R1-NEXT: c.eq.s $f12, $f14
+; CMOV32R1-NEXT: movt.s $f14, $f12, $fcc0
+; CMOV32R1-NEXT: jr $ra
+; CMOV32R1-NEXT: mov.s $f0, $f14
+;
+; CMOV32R2-LABEL: tst_select_fcmp_oeq_float:
+; CMOV32R2: # %bb.0: # %entry
+; CMOV32R2-NEXT: c.eq.s $f12, $f14
+; CMOV32R2-NEXT: movt.s $f14, $f12, $fcc0
+; CMOV32R2-NEXT: jr $ra
+; CMOV32R2-NEXT: mov.s $f0, $f14
+;
+; 32R6-LABEL: tst_select_fcmp_oeq_float:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: cmp.eq.s $f0, $f12, $f14
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: sel.s $f0, $f14, $f12
+;
+; M3-LABEL: tst_select_fcmp_oeq_float:
+; M3: # %bb.0: # %entry
+; M3-NEXT: c.eq.s $f12, $f13
+; M3-NEXT: bc1t .LBB6_2
+; M3-NEXT: nop
+; M3-NEXT: # %bb.1: # %entry
+; M3-NEXT: mov.s $f12, $f13
+; M3-NEXT: .LBB6_2: # %entry
+; M3-NEXT: jr $ra
+; M3-NEXT: mov.s $f0, $f12
+;
+; CMOV64-LABEL: tst_select_fcmp_oeq_float:
+; CMOV64: # %bb.0: # %entry
+; CMOV64-NEXT: c.eq.s $f12, $f13
+; CMOV64-NEXT: movt.s $f13, $f12, $fcc0
+; CMOV64-NEXT: jr $ra
+; CMOV64-NEXT: mov.s $f0, $f13
+;
+; 64R6-LABEL: tst_select_fcmp_oeq_float:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: cmp.eq.s $f0, $f12, $f13
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: sel.s $f0, $f13, $f12
+;
+; MM32R3-LABEL: tst_select_fcmp_oeq_float:
+; MM32R3: # %bb.0: # %entry
+; MM32R3-NEXT: c.eq.s $f12, $f14
+; MM32R3-NEXT: movt.s $f14, $f12, $fcc0
+; MM32R3-NEXT: jr $ra
+; MM32R3-NEXT: mov.s $f0, $f14
+;
+; MM32R6-LABEL: tst_select_fcmp_oeq_float:
+; MM32R6: # %bb.0: # %entry
+; MM32R6-NEXT: cmp.eq.s $f0, $f12, $f14
+; MM32R6-NEXT: sel.s $f0, $f14, $f12
+; MM32R6-NEXT: jrc $ra
entry:
- ; ALL-LABEL: tst_select_fcmp_oeq_float:
-
- ; M2: c.eq.s $f12, $f14
- ; M3: c.eq.s $f12, $f13
- ; M2: bc1t [[BB0:\$BB[0-9_]+]]
- ; M3: bc1t [[BB0:\.LBB[0-9_]+]]
- ; M2-M3: nop
- ; M2: mov.s $f12, $f14
- ; M3: mov.s $f12, $f13
- ; M2-M3: [[BB0]]:
- ; M2-M3: jr $ra
- ; M2-M3: mov.s $f0, $f12
-
- ; CMOV-32: c.eq.s $f12, $f14
- ; CMOV-32: movt.s $f14, $f12, $fcc0
- ; CMOV-32: mov.s $f0, $f14
-
- ; SEL-32: cmp.eq.s $f0, $f12, $f14
- ; SEL-32: sel.s $f0, $f14, $f12
-
- ; CMOV-64: c.eq.s $f12, $f13
- ; CMOV-64: movt.s $f13, $f12, $fcc0
- ; CMOV-64: mov.s $f0, $f13
-
- ; SEL-64: cmp.eq.s $f0, $f12, $f13
- ; SEL-64: sel.s $f0, $f13, $f12
-
- ; MM32R3: c.eq.s $f12, $f14
- ; MM32R3: movt.s $f14, $f12, $fcc0
- ; MM32R3: mov.s $f0, $f14
-
%s = fcmp oeq float %x, %y
%r = select i1 %s, float %x, float %y
ret float %r
}
define float @tst_select_fcmp_one_float(float %x, float %y) {
+; M2-LABEL: tst_select_fcmp_one_float:
+; M2: # %bb.0: # %entry
+; M2-NEXT: c.ueq.s $f12, $f14
+; M2-NEXT: bc1f $BB7_2
+; M2-NEXT: nop
+; M2-NEXT: # %bb.1: # %entry
+; M2-NEXT: mov.s $f12, $f14
+; M2-NEXT: $BB7_2: # %entry
+; M2-NEXT: jr $ra
+; M2-NEXT: mov.s $f0, $f12
+;
+; CMOV32R1-LABEL: tst_select_fcmp_one_float:
+; CMOV32R1: # %bb.0: # %entry
+; CMOV32R1-NEXT: c.ueq.s $f12, $f14
+; CMOV32R1-NEXT: movf.s $f14, $f12, $fcc0
+; CMOV32R1-NEXT: jr $ra
+; CMOV32R1-NEXT: mov.s $f0, $f14
+;
+; CMOV32R2-LABEL: tst_select_fcmp_one_float:
+; CMOV32R2: # %bb.0: # %entry
+; CMOV32R2-NEXT: c.ueq.s $f12, $f14
+; CMOV32R2-NEXT: movf.s $f14, $f12, $fcc0
+; CMOV32R2-NEXT: jr $ra
+; CMOV32R2-NEXT: mov.s $f0, $f14
+;
+; 32R6-LABEL: tst_select_fcmp_one_float:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: cmp.ueq.s $f0, $f12, $f14
+; 32R6-NEXT: mfc1 $1, $f0
+; 32R6-NEXT: not $1, $1
+; 32R6-NEXT: mtc1 $1, $f0
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: sel.s $f0, $f14, $f12
+;
+; M3-LABEL: tst_select_fcmp_one_float:
+; M3: # %bb.0: # %entry
+; M3-NEXT: c.ueq.s $f12, $f13
+; M3-NEXT: bc1f .LBB7_2
+; M3-NEXT: nop
+; M3-NEXT: # %bb.1: # %entry
+; M3-NEXT: mov.s $f12, $f13
+; M3-NEXT: .LBB7_2: # %entry
+; M3-NEXT: jr $ra
+; M3-NEXT: mov.s $f0, $f12
+;
+; CMOV64-LABEL: tst_select_fcmp_one_float:
+; CMOV64: # %bb.0: # %entry
+; CMOV64-NEXT: c.ueq.s $f12, $f13
+; CMOV64-NEXT: movf.s $f13, $f12, $fcc0
+; CMOV64-NEXT: jr $ra
+; CMOV64-NEXT: mov.s $f0, $f13
+;
+; 64R6-LABEL: tst_select_fcmp_one_float:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: cmp.ueq.s $f0, $f12, $f13
+; 64R6-NEXT: mfc1 $1, $f0
+; 64R6-NEXT: not $1, $1
+; 64R6-NEXT: mtc1 $1, $f0
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: sel.s $f0, $f13, $f12
+;
+; MM32R3-LABEL: tst_select_fcmp_one_float:
+; MM32R3: # %bb.0: # %entry
+; MM32R3-NEXT: c.ueq.s $f12, $f14
+; MM32R3-NEXT: movf.s $f14, $f12, $fcc0
+; MM32R3-NEXT: jr $ra
+; MM32R3-NEXT: mov.s $f0, $f14
+;
+; MM32R6-LABEL: tst_select_fcmp_one_float:
+; MM32R6: # %bb.0: # %entry
+; MM32R6-NEXT: cmp.ueq.s $f0, $f12, $f14
+; MM32R6-NEXT: mfc1 $1, $f0
+; MM32R6-NEXT: not $1, $1
+; MM32R6-NEXT: mtc1 $1, $f0
+; MM32R6-NEXT: sel.s $f0, $f14, $f12
+; MM32R6-NEXT: jrc $ra
entry:
- ; ALL-LABEL: tst_select_fcmp_one_float:
-
- ; M2: c.ueq.s $f12, $f14
- ; M3: c.ueq.s $f12, $f13
- ; M2: bc1f [[BB0:\$BB[0-9_]+]]
- ; M3: bc1f [[BB0:\.LBB[0-9_]+]]
- ; M2-M3: nop
- ; M2: mov.s $f12, $f14
- ; M3: mov.s $f12, $f13
- ; M2-M3: [[BB0]]:
- ; M2-M3: jr $ra
- ; M2-M3: mov.s $f0, $f12
-
- ; CMOV-32: c.ueq.s $f12, $f14
- ; CMOV-32: movf.s $f14, $f12, $fcc0
- ; CMOV-32: mov.s $f0, $f14
-
- ; SEL-32: cmp.ueq.s $f0, $f12, $f14
- ; SEL-32: mfc1 $[[T0:[0-9]+]], $f0
- ; SEL-32: not $[[T0]], $[[T0]]
- ; SEL-32: mtc1 $[[T0:[0-9]+]], $f0
- ; SEL-32: sel.s $f0, $f14, $f12
-
- ; CMOV-64: c.ueq.s $f12, $f13
- ; CMOV-64: movf.s $f13, $f12, $fcc0
- ; CMOV-64: mov.s $f0, $f13
-
- ; SEL-64: cmp.ueq.s $f0, $f12, $f13
- ; SEL-64: mfc1 $[[T0:[0-9]+]], $f0
- ; SEL-64: not $[[T0]], $[[T0]]
- ; SEL-64: mtc1 $[[T0:[0-9]+]], $f0
- ; SEL-64: sel.s $f0, $f13, $f12
-
- ; MM32R3: c.ueq.s $f12, $f14
- ; MM32R3: movf.s $f14, $f12, $fcc0
- ; MM32R3: mov.s $f0, $f14
-
%s = fcmp one float %x, %y
%r = select i1 %s, float %x, float %y
ret float %r
diff --git a/llvm/test/CodeGen/Mips/o32_cc_byval.ll b/llvm/test/CodeGen/Mips/o32_cc_byval.ll
index eadf4abfc75..634d02d4be7 100644
--- a/llvm/test/CodeGen/Mips/o32_cc_byval.ll
+++ b/llvm/test/CodeGen/Mips/o32_cc_byval.ll
@@ -1,4 +1,5 @@
-; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=mipsel-unknown-linux-gnu -relocation-model=pic < %s | FileCheck %s
%0 = type { i8, i16, i32, i64, double, i32, [4 x i8] }
%struct.S1 = type { i8, i16, i32, i64, double, i32 }
@@ -9,24 +10,75 @@
@f1.s2 = internal unnamed_addr constant %struct.S2 { [4 x i32] [i32 7, i32 8, i32 9, i32 10] }, align 4
define void @f1() nounwind {
-entry:
; CHECK-LABEL: f1:
-; CHECK-DAG: lw $[[R1:[0-9]+]], %got(f1.s1)
-; CHECK-DAG: addiu $[[R0:[0-9]+]], $[[R1]], %lo(f1.s1)
-; CHECK-DAG: lw $[[R7:[0-9]+]], 12($[[R0]])
-; CHECK-DAG: lw $[[R3:[0-9]+]], 16($[[R0]])
-; CHECK-DAG: lw $[[R4:[0-9]+]], 20($[[R0]])
-; CHECK-DAG: lw $[[R5:[0-9]+]], 24($[[R0]])
-; CHECK-DAG: lw $[[R6:[0-9]+]], 28($[[R0]])
-; CHECK-DAG: sw $[[R6]], 36($sp)
-; CHECK-DAG: sw $[[R5]], 32($sp)
-; CHECK-DAG: sw $[[R4]], 28($sp)
-; CHECK-DAG: sw $[[R3]], 24($sp)
-; CHECK-DAG: sw $[[R7]], 20($sp)
-; CHECK-DAG: lw $[[R2:[0-9]+]], 8($[[R0]])
-; CHECK-DAG: sw $[[R2]], 16($sp)
-; CHECK-DAG: lw $6, %lo(f1.s1)($[[R1]])
-; CHECK-DAG: lw $7, 4($[[R0]])
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lui $2, %hi(_gp_disp)
+; CHECK-NEXT: addiu $2, $2, %lo(_gp_disp)
+; CHECK-NEXT: addiu $sp, $sp, -64
+; CHECK-NEXT: sw $ra, 60($sp) # 4-byte Folded Spill
+; CHECK-NEXT: sw $18, 56($sp) # 4-byte Folded Spill
+; CHECK-NEXT: sw $17, 52($sp) # 4-byte Folded Spill
+; CHECK-NEXT: sw $16, 48($sp) # 4-byte Folded Spill
+; CHECK-NEXT: addu $16, $2, $25
+; CHECK-NEXT: lw $17, %got(f1.s1)($16)
+; CHECK-NEXT: addiu $18, $17, %lo(f1.s1)
+; CHECK-NEXT: lw $1, 12($18)
+; CHECK-NEXT: lw $2, 16($18)
+; CHECK-NEXT: lw $3, 20($18)
+; CHECK-NEXT: lw $4, 24($18)
+; CHECK-NEXT: lw $5, 28($18)
+; CHECK-NEXT: sw $5, 36($sp)
+; CHECK-NEXT: sw $4, 32($sp)
+; CHECK-NEXT: sw $3, 28($sp)
+; CHECK-NEXT: sw $2, 24($sp)
+; CHECK-NEXT: sw $1, 20($sp)
+; CHECK-NEXT: lw $1, 8($18)
+; CHECK-NEXT: sw $1, 16($sp)
+; CHECK-NEXT: lw $6, %lo(f1.s1)($17)
+; CHECK-NEXT: lw $7, 4($18)
+; CHECK-NEXT: lw $1, %got($CPI0_0)($16)
+; CHECK-NEXT: lwc1 $f12, %lo($CPI0_0)($1)
+; CHECK-NEXT: lw $25, %call16(callee1)($16)
+; CHECK-NEXT: jalr $25
+; CHECK-NEXT: move $gp, $16
+; CHECK-NEXT: lw $1, %got(f1.s2)($16)
+; CHECK-NEXT: addiu $2, $1, %lo(f1.s2)
+; CHECK-NEXT: lw $7, 12($2)
+; CHECK-NEXT: lw $6, 8($2)
+; CHECK-NEXT: lw $5, 4($2)
+; CHECK-NEXT: lw $4, %lo(f1.s2)($1)
+; CHECK-NEXT: lw $25, %call16(callee2)($16)
+; CHECK-NEXT: jalr $25
+; CHECK-NEXT: move $gp, $16
+; CHECK-NEXT: addiu $1, $zero, 11
+; CHECK-NEXT: lw $2, %got($CPI0_1)($16)
+; CHECK-NEXT: lwc1 $f12, %lo($CPI0_1)($2)
+; CHECK-NEXT: sb $1, 40($sp)
+; CHECK-NEXT: lw $1, 16($18)
+; CHECK-NEXT: lw $2, 20($18)
+; CHECK-NEXT: lw $3, 24($18)
+; CHECK-NEXT: lw $4, 28($18)
+; CHECK-NEXT: sw $4, 36($sp)
+; CHECK-NEXT: sw $3, 32($sp)
+; CHECK-NEXT: sw $2, 28($sp)
+; CHECK-NEXT: sw $1, 24($sp)
+; CHECK-NEXT: lw $1, 12($18)
+; CHECK-NEXT: sw $1, 20($sp)
+; CHECK-NEXT: lw $1, 8($18)
+; CHECK-NEXT: sw $1, 16($sp)
+; CHECK-NEXT: lw $7, 4($18)
+; CHECK-NEXT: lw $6, %lo(f1.s1)($17)
+; CHECK-NEXT: lbu $5, 40($sp)
+; CHECK-NEXT: lw $25, %call16(callee3)($16)
+; CHECK-NEXT: jalr $25
+; CHECK-NEXT: move $gp, $16
+; CHECK-NEXT: lw $16, 48($sp) # 4-byte Folded Reload
+; CHECK-NEXT: lw $17, 52($sp) # 4-byte Folded Reload
+; CHECK-NEXT: lw $18, 56($sp) # 4-byte Folded Reload
+; CHECK-NEXT: lw $ra, 60($sp) # 4-byte Folded Reload
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: addiu $sp, $sp, 64
+entry:
%agg.tmp10 = alloca %struct.S3, align 4
call void @callee1(float 2.000000e+01, %struct.S1* byval bitcast (%0* @f1.s1 to %struct.S1*)) nounwind
call void @callee2(%struct.S2* byval @f1.s2) nounwind
@@ -43,22 +95,35 @@ declare void @callee2(%struct.S2* byval)
declare void @callee3(float, %struct.S3* byval, %struct.S1* byval)
define void @f2(float %f, %struct.S1* nocapture byval %s1) nounwind {
+; CHECK-LABEL: f2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lui $2, %hi(_gp_disp)
+; CHECK-NEXT: addiu $2, $2, %lo(_gp_disp)
+; CHECK-NEXT: addiu $sp, $sp, -48
+; CHECK-NEXT: sw $ra, 44($sp) # 4-byte Folded Spill
+; CHECK-NEXT: addu $gp, $2, $25
+; CHECK-NEXT: sw $6, 56($sp)
+; CHECK-NEXT: sw $7, 60($sp)
+; CHECK-NEXT: lw $4, 80($sp)
+; CHECK-NEXT: ldc1 $f0, 72($sp)
+; CHECK-NEXT: lw $1, 64($sp)
+; CHECK-NEXT: lw $2, 68($sp)
+; CHECK-NEXT: lh $3, 58($sp)
+; CHECK-NEXT: lb $5, 56($sp)
+; CHECK-NEXT: swc1 $f12, 36($sp)
+; CHECK-NEXT: sw $5, 32($sp)
+; CHECK-NEXT: sw $3, 28($sp)
+; CHECK-NEXT: sw $2, 20($sp)
+; CHECK-NEXT: sw $1, 16($sp)
+; CHECK-NEXT: sw $7, 24($sp)
+; CHECK-NEXT: mfc1 $6, $f0
+; CHECK-NEXT: lw $25, %call16(callee4)($gp)
+; CHECK-NEXT: jalr $25
+; CHECK-NEXT: mfc1 $7, $f1
+; CHECK-NEXT: lw $ra, 44($sp) # 4-byte Folded Reload
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: addiu $sp, $sp, 48
entry:
-; CHECK: addiu $sp, $sp, -48
-; CHECK-DAG: sw $7, 60($sp)
-; CHECK-DAG: sw $6, 56($sp)
-; CHECK-DAG: ldc1 $f[[F0:[0-9]+]], 72($sp)
-; CHECK-DAG: lw $[[R3:[0-9]+]], 64($sp)
-; CHECK-DAG: lw $[[R4:[0-9]+]], 68($sp)
-; CHECK-DAG: lh $[[R1:[0-9]+]], 58($sp)
-; CHECK-DAG: lb $[[R0:[0-9]+]], 56($sp)
-; CHECK-DAG: sw $[[R0]], 32($sp)
-; CHECK-DAG: sw $[[R1]], 28($sp)
-; CHECK-DAG: sw $[[R4]], 20($sp)
-; CHECK-DAG: sw $[[R3]], 16($sp)
-; CHECK-DAG: sw $7, 24($sp)
-; CHECK: mfc1 $6, $f[[F0]]
-
%i2 = getelementptr inbounds %struct.S1, %struct.S1* %s1, i32 0, i32 5
%tmp = load i32, i32* %i2, align 4
%d = getelementptr inbounds %struct.S1, %struct.S1* %s1, i32 0, i32 4
@@ -78,14 +143,37 @@ entry:
declare void @callee4(i32, double, i64, i32, i16 signext, i8 signext, float)
define void @f3(%struct.S2* nocapture byval %s2) nounwind {
+; CHECK-LABEL: f3:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lui $2, %hi(_gp_disp)
+; CHECK-NEXT: addiu $2, $2, %lo(_gp_disp)
+; CHECK-NEXT: addiu $sp, $sp, -48
+; CHECK-NEXT: sw $ra, 44($sp) # 4-byte Folded Spill
+; CHECK-NEXT: addu $gp, $2, $25
+; CHECK-NEXT: sw $7, 60($sp)
+; CHECK-NEXT: sw $6, 56($sp)
+; CHECK-NEXT: sw $5, 52($sp)
+; CHECK-NEXT: sw $4, 48($sp)
+; CHECK-NEXT: addiu $1, $zero, 3
+; CHECK-NEXT: addiu $2, $zero, 4
+; CHECK-NEXT: addiu $3, $zero, 5
+; CHECK-NEXT: lui $5, 16576
+; CHECK-NEXT: sw $5, 36($sp)
+; CHECK-NEXT: sw $3, 32($sp)
+; CHECK-NEXT: sw $2, 28($sp)
+; CHECK-NEXT: sw $1, 16($sp)
+; CHECK-NEXT: sw $7, 24($sp)
+; CHECK-NEXT: sw $zero, 20($sp)
+; CHECK-NEXT: lw $1, %got($CPI2_0)($gp)
+; CHECK-NEXT: ldc1 $f0, %lo($CPI2_0)($1)
+; CHECK-NEXT: mfc1 $6, $f0
+; CHECK-NEXT: lw $25, %call16(callee4)($gp)
+; CHECK-NEXT: jalr $25
+; CHECK-NEXT: mfc1 $7, $f1
+; CHECK-NEXT: lw $ra, 44($sp) # 4-byte Folded Reload
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: addiu $sp, $sp, 48
entry:
-; CHECK: addiu $sp, $sp, -48
-; CHECK-DAG: sw $7, 60($sp)
-; CHECK-DAG: sw $6, 56($sp)
-; CHECK-DAG: sw $5, 52($sp)
-; CHECK-DAG: sw $4, 48($sp)
-; CHECK-DAG: sw $7, 24($sp)
-
%arrayidx = getelementptr inbounds %struct.S2, %struct.S2* %s2, i32 0, i32 0, i32 0
%tmp = load i32, i32* %arrayidx, align 4
%arrayidx2 = getelementptr inbounds %struct.S2, %struct.S2* %s2, i32 0, i32 0, i32 3
@@ -95,17 +183,39 @@ entry:
}
define void @f4(float %f, %struct.S3* nocapture byval %s3, %struct.S1* nocapture byval %s1) nounwind {
+; CHECK-LABEL: f4:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lui $2, %hi(_gp_disp)
+; CHECK-NEXT: addiu $2, $2, %lo(_gp_disp)
+; CHECK-NEXT: addiu $sp, $sp, -48
+; CHECK-NEXT: sw $ra, 44($sp) # 4-byte Folded Spill
+; CHECK-NEXT: addu $gp, $2, $25
+; CHECK-NEXT: sw $5, 52($sp)
+; CHECK-NEXT: sw $6, 56($sp)
+; CHECK-NEXT: sw $7, 60($sp)
+; CHECK-NEXT: lw $1, 80($sp)
+; CHECK-NEXT: lb $2, 52($sp)
+; CHECK-NEXT: addiu $3, $zero, 4
+; CHECK-NEXT: lui $4, 16576
+; CHECK-NEXT: sw $4, 36($sp)
+; CHECK-NEXT: sw $2, 32($sp)
+; CHECK-NEXT: sw $3, 28($sp)
+; CHECK-NEXT: sw $1, 24($sp)
+; CHECK-NEXT: addiu $1, $zero, 3
+; CHECK-NEXT: sw $1, 16($sp)
+; CHECK-NEXT: sw $zero, 20($sp)
+; CHECK-NEXT: lw $1, %got($CPI3_0)($gp)
+; CHECK-NEXT: ldc1 $f0, %lo($CPI3_0)($1)
+; CHECK-NEXT: mfc1 $6, $f0
+; CHECK-NEXT: mfc1 $1, $f1
+; CHECK-NEXT: lw $25, %call16(callee4)($gp)
+; CHECK-NEXT: move $4, $7
+; CHECK-NEXT: jalr $25
+; CHECK-NEXT: move $7, $1
+; CHECK-NEXT: lw $ra, 44($sp) # 4-byte Folded Reload
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: addiu $sp, $sp, 48
entry:
-; CHECK: addiu $sp, $sp, -48
-; CHECK-DAG: sw $7, 60($sp)
-; CHECK-DAG: sw $6, 56($sp)
-; CHECK-DAG: sw $5, 52($sp)
-; CHECK-DAG: lw $[[R1:[0-9]+]], 80($sp)
-; CHECK-DAG: lb $[[R0:[0-9]+]], 52($sp)
-; CHECK-DAG: sw $[[R0]], 32($sp)
-; CHECK-DAG: sw $[[R1]], 24($sp)
-; CHECK: move $4, $7
-
%i = getelementptr inbounds %struct.S1, %struct.S1* %s1, i32 0, i32 2
%tmp = load i32, i32* %i, align 4
%i2 = getelementptr inbounds %struct.S1, %struct.S1* %s1, i32 0, i32 5
@@ -119,6 +229,27 @@ entry:
%struct.S4 = type { [4 x i32] }
define void @f5(i64 %a0, %struct.S4* nocapture byval %a1) nounwind {
+; CHECK-LABEL: f5:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lui $2, %hi(_gp_disp)
+; CHECK-NEXT: addiu $2, $2, %lo(_gp_disp)
+; CHECK-NEXT: addiu $sp, $sp, -32
+; CHECK-NEXT: sw $ra, 28($sp) # 4-byte Folded Spill
+; CHECK-NEXT: addu $gp, $2, $25
+; CHECK-NEXT: sw $7, 44($sp)
+; CHECK-NEXT: sw $6, 40($sp)
+; CHECK-NEXT: sw $5, 20($sp)
+; CHECK-NEXT: sw $4, 16($sp)
+; CHECK-NEXT: lw $7, 52($sp)
+; CHECK-NEXT: lw $6, 48($sp)
+; CHECK-NEXT: lw $5, 44($sp)
+; CHECK-NEXT: lw $4, 40($sp)
+; CHECK-NEXT: lw $25, %call16(f6)($gp)
+; CHECK-NEXT: jalr $25
+; CHECK-NEXT: nop
+; CHECK-NEXT: lw $ra, 28($sp) # 4-byte Folded Reload
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: addiu $sp, $sp, 32
entry:
tail call void @f6(%struct.S4* byval %a1, i64 %a0) nounwind
ret void
diff --git a/llvm/test/CodeGen/Mips/select.ll b/llvm/test/CodeGen/Mips/select.ll
index 9d47c9b8a75..18cd40f7248 100644
--- a/llvm/test/CodeGen/Mips/select.ll
+++ b/llvm/test/CodeGen/Mips/select.ll
@@ -1,706 +1,989 @@
-; RUN: llc < %s -march=mipsel -mcpu=mips32 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefixes=ALL,32
-; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefixes=ALL,32R2
-; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefixes=ALL,32R6
-; RUN: llc < %s -march=mips64el -mcpu=mips64 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefixes=ALL,64
-; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefixes=ALL,64R2
-; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefixes=ALL,64R6
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=32
+; RUN: llc < %s -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r2 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=32R2
+; RUN: llc < %s -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r6 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=32R6
+; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnu -mcpu=mips64 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=64
+; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnu -mcpu=mips64r2 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=64R2
+; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnu -mcpu=mips64r6 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=64R6
@d2 = external global double
@d3 = external global double
define i32 @i32_icmp_ne_i32_val(i32 signext %s, i32 signext %f0, i32 signext %f1) nounwind readnone {
+; 32-LABEL: i32_icmp_ne_i32_val:
+; 32: # %bb.0: # %entry
+; 32-NEXT: movn $5, $6, $4
+; 32-NEXT: jr $ra
+; 32-NEXT: move $2, $5
+;
+; 32R2-LABEL: i32_icmp_ne_i32_val:
+; 32R2: # %bb.0: # %entry
+; 32R2-NEXT: movn $5, $6, $4
+; 32R2-NEXT: jr $ra
+; 32R2-NEXT: move $2, $5
+;
+; 32R6-LABEL: i32_icmp_ne_i32_val:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: seleqz $1, $5, $4
+; 32R6-NEXT: selnez $2, $6, $4
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: or $2, $2, $1
+;
+; 64-LABEL: i32_icmp_ne_i32_val:
+; 64: # %bb.0: # %entry
+; 64-NEXT: movn $5, $6, $4
+; 64-NEXT: jr $ra
+; 64-NEXT: move $2, $5
+;
+; 64R2-LABEL: i32_icmp_ne_i32_val:
+; 64R2: # %bb.0: # %entry
+; 64R2-NEXT: movn $5, $6, $4
+; 64R2-NEXT: jr $ra
+; 64R2-NEXT: move $2, $5
+;
+; 64R6-LABEL: i32_icmp_ne_i32_val:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: seleqz $1, $5, $4
+; 64R6-NEXT: selnez $2, $6, $4
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: or $2, $2, $1
entry:
-; ALL-LABEL: i32_icmp_ne_i32_val:
-
-; 32: movn $5, $6, $4
-; 32: move $2, $5
-
-; 32R2: movn $5, $6, $4
-; 32R2: move $2, $5
-
-; 32R6-DAG: seleqz $[[T0:[0-9]+]], $5, $4
-; 32R6-DAG: selnez $[[T1:[0-9]+]], $6, $4
-; 32R6: or $2, $[[T1]], $[[T0]]
-
-; 64: movn $5, $6, $4
-; 64: move $2, $5
-
-; 64R2: movn $5, $6, $4
-; 64R2: move $2, $5
-
-; 64R6-DAG: seleqz $[[T0:[0-9]+]], $5, $4
-; 64R6-DAG: selnez $[[T1:[0-9]+]], $6, $4
-; 64R6: or $2, $[[T1]], $[[T0]]
-
%tobool = icmp ne i32 %s, 0
%cond = select i1 %tobool, i32 %f1, i32 %f0
ret i32 %cond
}
-define i64 @i32_icmp_ne_i64_val(i32 signext %s, i64 %f0, i64 %f1) nounwind readnone {
-entry:
-; ALL-LABEL: i32_icmp_ne_i64_val:
-
-; 32-DAG: lw $[[F1:[0-9]+]], 16($sp)
-; 32-DAG: movn $6, $[[F1]], $4
-; 32-DAG: lw $[[F1H:[0-9]+]], 20($sp)
-; 32: movn $7, $[[F1H]], $4
-; 32: move $2, $6
-; 32: move $3, $7
-
-; 32R2-DAG: lw $[[F1:[0-9]+]], 16($sp)
-; 32R2-DAG: movn $6, $[[F1]], $4
-; 32R2-DAG: lw $[[F1H:[0-9]+]], 20($sp)
-; 32R2: movn $7, $[[F1H]], $4
-; 32R2: move $2, $6
-; 32R2: move $3, $7
-
-; 32R6-DAG: lw $[[F1:[0-9]+]], 16($sp)
-; 32R6-DAG: seleqz $[[T0:[0-9]+]], $6, $4
-; 32R6-DAG: selnez $[[T1:[0-9]+]], $[[F1]], $4
-; 32R6: or $2, $[[T1]], $[[T0]]
-; 32R6-DAG: lw $[[F1H:[0-9]+]], 20($sp)
-; 32R6-DAG: seleqz $[[T0:[0-9]+]], $7, $4
-; 32R6-DAG: selnez $[[T1:[0-9]+]], $[[F1H]], $4
-; 32R6: or $3, $[[T1]], $[[T0]]
-
-; 64: movn $5, $6, $4
-; 64: move $2, $5
-
-; 64R2: movn $5, $6, $4
-; 64R2: move $2, $5
-
-; FIXME: This sll works around an implementation detail in the code generator
+; FIXME: The sll works around an implementation detail in the code generator
; (setcc's result is i32 so bits 32-63 are undefined). It's not really
; needed.
-; 64R6-DAG: sll $[[CC:[0-9]+]], $4, 0
-; 64R6-DAG: seleqz $[[T0:[0-9]+]], $5, $[[CC]]
-; 64R6-DAG: selnez $[[T1:[0-9]+]], $6, $[[CC]]
-; 64R6: or $2, $[[T1]], $[[T0]]
+define i64 @i32_icmp_ne_i64_val(i32 signext %s, i64 %f0, i64 %f1) nounwind readnone {
+; 32-LABEL: i32_icmp_ne_i64_val:
+; 32: # %bb.0: # %entry
+; 32-NEXT: lw $1, 16($sp)
+; 32-NEXT: movn $6, $1, $4
+; 32-NEXT: lw $1, 20($sp)
+; 32-NEXT: movn $7, $1, $4
+; 32-NEXT: move $2, $6
+; 32-NEXT: jr $ra
+; 32-NEXT: move $3, $7
+;
+; 32R2-LABEL: i32_icmp_ne_i64_val:
+; 32R2: # %bb.0: # %entry
+; 32R2-NEXT: lw $1, 16($sp)
+; 32R2-NEXT: movn $6, $1, $4
+; 32R2-NEXT: lw $1, 20($sp)
+; 32R2-NEXT: movn $7, $1, $4
+; 32R2-NEXT: move $2, $6
+; 32R2-NEXT: jr $ra
+; 32R2-NEXT: move $3, $7
+;
+; 32R6-LABEL: i32_icmp_ne_i64_val:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: seleqz $1, $6, $4
+; 32R6-NEXT: lw $2, 16($sp)
+; 32R6-NEXT: selnez $2, $2, $4
+; 32R6-NEXT: or $2, $2, $1
+; 32R6-NEXT: seleqz $1, $7, $4
+; 32R6-NEXT: lw $3, 20($sp)
+; 32R6-NEXT: selnez $3, $3, $4
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: or $3, $3, $1
+;
+; 64-LABEL: i32_icmp_ne_i64_val:
+; 64: # %bb.0: # %entry
+; 64-NEXT: movn $5, $6, $4
+; 64-NEXT: jr $ra
+; 64-NEXT: move $2, $5
+;
+; 64R2-LABEL: i32_icmp_ne_i64_val:
+; 64R2: # %bb.0: # %entry
+; 64R2-NEXT: movn $5, $6, $4
+; 64R2-NEXT: jr $ra
+; 64R2-NEXT: move $2, $5
+;
+; 64R6-LABEL: i32_icmp_ne_i64_val:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: sll $1, $4, 0
+; 64R6-NEXT: seleqz $2, $5, $1
+; 64R6-NEXT: selnez $1, $6, $1
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: or $2, $1, $2
+entry:
%tobool = icmp ne i32 %s, 0
%cond = select i1 %tobool, i64 %f1, i64 %f0
ret i64 %cond
}
define i64 @i64_icmp_ne_i64_val(i64 %s, i64 %f0, i64 %f1) nounwind readnone {
+; 32-LABEL: i64_icmp_ne_i64_val:
+; 32: # %bb.0: # %entry
+; 32-NEXT: or $1, $4, $5
+; 32-NEXT: lw $2, 16($sp)
+; 32-NEXT: movn $6, $2, $1
+; 32-NEXT: lw $2, 20($sp)
+; 32-NEXT: movn $7, $2, $1
+; 32-NEXT: move $2, $6
+; 32-NEXT: jr $ra
+; 32-NEXT: move $3, $7
+;
+; 32R2-LABEL: i64_icmp_ne_i64_val:
+; 32R2: # %bb.0: # %entry
+; 32R2-NEXT: or $1, $4, $5
+; 32R2-NEXT: lw $2, 16($sp)
+; 32R2-NEXT: movn $6, $2, $1
+; 32R2-NEXT: lw $2, 20($sp)
+; 32R2-NEXT: movn $7, $2, $1
+; 32R2-NEXT: move $2, $6
+; 32R2-NEXT: jr $ra
+; 32R2-NEXT: move $3, $7
+;
+; 32R6-LABEL: i64_icmp_ne_i64_val:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: or $1, $4, $5
+; 32R6-NEXT: seleqz $2, $6, $1
+; 32R6-NEXT: lw $3, 16($sp)
+; 32R6-NEXT: selnez $3, $3, $1
+; 32R6-NEXT: or $2, $3, $2
+; 32R6-NEXT: seleqz $3, $7, $1
+; 32R6-NEXT: lw $4, 20($sp)
+; 32R6-NEXT: selnez $1, $4, $1
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: or $3, $1, $3
+;
+; 64-LABEL: i64_icmp_ne_i64_val:
+; 64: # %bb.0: # %entry
+; 64-NEXT: movn $5, $6, $4
+; 64-NEXT: jr $ra
+; 64-NEXT: move $2, $5
+;
+; 64R2-LABEL: i64_icmp_ne_i64_val:
+; 64R2: # %bb.0: # %entry
+; 64R2-NEXT: movn $5, $6, $4
+; 64R2-NEXT: jr $ra
+; 64R2-NEXT: move $2, $5
+;
+; 64R6-LABEL: i64_icmp_ne_i64_val:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: seleqz $1, $5, $4
+; 64R6-NEXT: selnez $2, $6, $4
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: or $2, $2, $1
entry:
-; ALL-LABEL: i64_icmp_ne_i64_val:
-
-; 32-DAG: or $[[CC:[0-9]+]], $4
-; 32-DAG: lw $[[F1:[0-9]+]], 16($sp)
-; 32-DAG: movn $6, $[[F1]], $[[CC]]
-; 32-DAG: lw $[[F1H:[0-9]+]], 20($sp)
-; 32: movn $7, $[[F1H]], $[[CC]]
-; 32: move $2, $6
-; 32: move $3, $7
-
-; 32R2-DAG: or $[[CC:[0-9]+]], $4
-; 32R2-DAG: lw $[[F1:[0-9]+]], 16($sp)
-; 32R2-DAG: movn $6, $[[F1]], $[[CC]]
-; 32R2-DAG: lw $[[F1H:[0-9]+]], 20($sp)
-; 32R2: movn $7, $[[F1H]], $[[CC]]
-; 32R2: move $2, $6
-; 32R2: move $3, $7
-
-; 32R6-DAG: lw $[[F1:[0-9]+]], 16($sp)
-; 32R6-DAG: or $[[T2:[0-9]+]], $4, $5
-; 32R6-DAG: seleqz $[[T0:[0-9]+]], $6, $[[T2]]
-; 32R6-DAG: selnez $[[T1:[0-9]+]], $[[F1]], $[[T2]]
-; 32R6: or $2, $[[T1]], $[[T0]]
-; 32R6-DAG: lw $[[F1H:[0-9]+]], 20($sp)
-; 32R6-DAG: seleqz $[[T0:[0-9]+]], $7, $[[T2]]
-; 32R6-DAG: selnez $[[T1:[0-9]+]], $[[F1H]], $[[T2]]
-; 32R6: or $3, $[[T1]], $[[T0]]
-
-; 64: movn $5, $6, $4
-; 64: move $2, $5
-
-; 64R2: movn $5, $6, $4
-; 64R2: move $2, $5
-
-; 64R6-DAG: seleqz $[[T0:[0-9]+]], $5, $4
-; 64R6-DAG: selnez $[[T1:[0-9]+]], $6, $4
-; 64R6: or $2, $[[T1]], $[[T0]]
-
%tobool = icmp ne i64 %s, 0
%cond = select i1 %tobool, i64 %f1, i64 %f0
ret i64 %cond
}
define float @i32_icmp_ne_f32_val(i32 signext %s, float %f0, float %f1) nounwind readnone {
+; 32-LABEL: i32_icmp_ne_f32_val:
+; 32: # %bb.0: # %entry
+; 32-NEXT: mtc1 $6, $f0
+; 32-NEXT: mtc1 $5, $f1
+; 32-NEXT: jr $ra
+; 32-NEXT: movn.s $f0, $f1, $4
+;
+; 32R2-LABEL: i32_icmp_ne_f32_val:
+; 32R2: # %bb.0: # %entry
+; 32R2-NEXT: mtc1 $6, $f0
+; 32R2-NEXT: mtc1 $5, $f1
+; 32R2-NEXT: jr $ra
+; 32R2-NEXT: movn.s $f0, $f1, $4
+;
+; 32R6-LABEL: i32_icmp_ne_f32_val:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: sltu $1, $zero, $4
+; 32R6-NEXT: negu $1, $1
+; 32R6-NEXT: mtc1 $5, $f1
+; 32R6-NEXT: mtc1 $6, $f2
+; 32R6-NEXT: mtc1 $1, $f0
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: sel.s $f0, $f2, $f1
+;
+; 64-LABEL: i32_icmp_ne_f32_val:
+; 64: # %bb.0: # %entry
+; 64-NEXT: movn.s $f14, $f13, $4
+; 64-NEXT: jr $ra
+; 64-NEXT: mov.s $f0, $f14
+;
+; 64R2-LABEL: i32_icmp_ne_f32_val:
+; 64R2: # %bb.0: # %entry
+; 64R2-NEXT: movn.s $f14, $f13, $4
+; 64R2-NEXT: jr $ra
+; 64R2-NEXT: mov.s $f0, $f14
+;
+; 64R6-LABEL: i32_icmp_ne_f32_val:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: sltu $1, $zero, $4
+; 64R6-NEXT: negu $1, $1
+; 64R6-NEXT: mtc1 $1, $f0
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: sel.s $f0, $f14, $f13
entry:
-; ALL-LABEL: i32_icmp_ne_f32_val:
-
-; 32-DAG: mtc1 $5, $[[F0:f[0-9]+]]
-; 32-DAG: mtc1 $6, $[[F1:f0]]
-; 32: movn.s $[[F1]], $[[F0]], $4
-
-; 32R2-DAG: mtc1 $5, $[[F0:f[0-9]+]]
-; 32R2-DAG: mtc1 $6, $[[F1:f0]]
-; 32R2: movn.s $[[F1]], $[[F0]], $4
-
-; 32R6: sltu $[[T0:[0-9]+]], $zero, $4
-; 32R6: negu $[[T0]], $[[T0]]
-; 32R6-DAG: mtc1 $5, $[[F0:f[0-9]+]]
-; 32R6-DAG: mtc1 $6, $[[F1:f[0-9]+]]
-; 32R6: mtc1 $[[T0]], $[[CC:f0]]
-; 32R6: sel.s $[[CC]], $[[F1]], $[[F0]]
-
-; 64: movn.s $f14, $f13, $4
-; 64: mov.s $f0, $f14
-
-; 64R2: movn.s $f14, $f13, $4
-; 64R2: mov.s $f0, $f14
-
-; 64R6: sltu $[[T0:[0-9]+]], $zero, $4
-; 64R6: mtc1 $[[T0]], $[[CC:f0]]
-; 64R6: sel.s $[[CC]], $f14, $f13
-
%tobool = icmp ne i32 %s, 0
%cond = select i1 %tobool, float %f0, float %f1
ret float %cond
}
define double @i32_icmp_ne_f64_val(i32 signext %s, double %f0, double %f1) nounwind readnone {
+; 32-LABEL: i32_icmp_ne_f64_val:
+; 32: # %bb.0: # %entry
+; 32-NEXT: mtc1 $6, $f2
+; 32-NEXT: mtc1 $7, $f3
+; 32-NEXT: ldc1 $f0, 16($sp)
+; 32-NEXT: jr $ra
+; 32-NEXT: movn.d $f0, $f2, $4
+;
+; 32R2-LABEL: i32_icmp_ne_f64_val:
+; 32R2: # %bb.0: # %entry
+; 32R2-NEXT: mtc1 $6, $f2
+; 32R2-NEXT: mthc1 $7, $f2
+; 32R2-NEXT: ldc1 $f0, 16($sp)
+; 32R2-NEXT: jr $ra
+; 32R2-NEXT: movn.d $f0, $f2, $4
+;
+; 32R6-LABEL: i32_icmp_ne_f64_val:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: mtc1 $6, $f1
+; 32R6-NEXT: mthc1 $7, $f1
+; 32R6-NEXT: sltu $1, $zero, $4
+; 32R6-NEXT: negu $1, $1
+; 32R6-NEXT: mtc1 $1, $f0
+; 32R6-NEXT: ldc1 $f2, 16($sp)
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: sel.d $f0, $f2, $f1
+;
+; 64-LABEL: i32_icmp_ne_f64_val:
+; 64: # %bb.0: # %entry
+; 64-NEXT: movn.d $f14, $f13, $4
+; 64-NEXT: jr $ra
+; 64-NEXT: mov.d $f0, $f14
+;
+; 64R2-LABEL: i32_icmp_ne_f64_val:
+; 64R2: # %bb.0: # %entry
+; 64R2-NEXT: movn.d $f14, $f13, $4
+; 64R2-NEXT: jr $ra
+; 64R2-NEXT: mov.d $f0, $f14
+;
+; 64R6-LABEL: i32_icmp_ne_f64_val:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: sltu $1, $zero, $4
+; 64R6-NEXT: negu $1, $1
+; 64R6-NEXT: mtc1 $1, $f0
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: sel.d $f0, $f14, $f13
entry:
-; ALL-LABEL: i32_icmp_ne_f64_val:
-
-; 32-DAG: mtc1 $6, $[[F0:f[1-3]*[02468]+]]
-; 32-DAG: mtc1 $7, $[[F0H:f[1-3]*[13579]+]]
-; 32-DAG: ldc1 $[[F1:f0]], 16($sp)
-; 32: movn.d $[[F1]], $[[F0]], $4
-
-; 32R2-DAG: mtc1 $6, $[[F0:f[0-9]+]]
-; 32R2-DAG: mthc1 $7, $[[F0]]
-; 32R2-DAG: ldc1 $[[F1:f0]], 16($sp)
-; 32R2: movn.d $[[F1]], $[[F0]], $4
-
-; 32R6-DAG: mtc1 $6, $[[F0:f[0-9]+]]
-; 32R6-DAG: mthc1 $7, $[[F0]]
-; 32R6-DAG: sltu $[[T0:[0-9]+]], $zero, $4
-; 32R6-DAG: mtc1 $[[T0]], $[[CC:f0]]
-; 32R6-DAG: ldc1 $[[F1:f[0-9]+]], 16($sp)
-; 32R6: sel.d $[[CC]], $[[F1]], $[[F0]]
-
-; 64: movn.d $f14, $f13, $4
-; 64: mov.d $f0, $f14
-
-; 64R2: movn.d $f14, $f13, $4
-; 64R2: mov.d $f0, $f14
-
-; 64R6-DAG: sltu $[[T0:[0-9]+]], $zero, $4
-; 64R6-DAG: mtc1 $[[T0]], $[[CC:f0]]
-; 64R6: sel.d $[[CC]], $f14, $f13
-
%tobool = icmp ne i32 %s, 0
%cond = select i1 %tobool, double %f0, double %f1
ret double %cond
}
define float @f32_fcmp_oeq_f32_val(float %f0, float %f1, float %f2, float %f3) nounwind readnone {
+; 32-LABEL: f32_fcmp_oeq_f32_val:
+; 32: # %bb.0: # %entry
+; 32-NEXT: mtc1 $7, $f0
+; 32-NEXT: mtc1 $6, $f1
+; 32-NEXT: c.eq.s $f1, $f0
+; 32-NEXT: movt.s $f14, $f12, $fcc0
+; 32-NEXT: jr $ra
+; 32-NEXT: mov.s $f0, $f14
+;
+; 32R2-LABEL: f32_fcmp_oeq_f32_val:
+; 32R2: # %bb.0: # %entry
+; 32R2-NEXT: mtc1 $7, $f0
+; 32R2-NEXT: mtc1 $6, $f1
+; 32R2-NEXT: c.eq.s $f1, $f0
+; 32R2-NEXT: movt.s $f14, $f12, $fcc0
+; 32R2-NEXT: jr $ra
+; 32R2-NEXT: mov.s $f0, $f14
+;
+; 32R6-LABEL: f32_fcmp_oeq_f32_val:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: mtc1 $7, $f0
+; 32R6-NEXT: mtc1 $6, $f1
+; 32R6-NEXT: cmp.eq.s $f0, $f1, $f0
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: sel.s $f0, $f14, $f12
+;
+; 64-LABEL: f32_fcmp_oeq_f32_val:
+; 64: # %bb.0: # %entry
+; 64-NEXT: c.eq.s $f14, $f15
+; 64-NEXT: movt.s $f13, $f12, $fcc0
+; 64-NEXT: jr $ra
+; 64-NEXT: mov.s $f0, $f13
+;
+; 64R2-LABEL: f32_fcmp_oeq_f32_val:
+; 64R2: # %bb.0: # %entry
+; 64R2-NEXT: c.eq.s $f14, $f15
+; 64R2-NEXT: movt.s $f13, $f12, $fcc0
+; 64R2-NEXT: jr $ra
+; 64R2-NEXT: mov.s $f0, $f13
+;
+; 64R6-LABEL: f32_fcmp_oeq_f32_val:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: cmp.eq.s $f0, $f14, $f15
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: sel.s $f0, $f13, $f12
entry:
-; ALL-LABEL: f32_fcmp_oeq_f32_val:
-
-; 32-DAG: mtc1 $6, $[[F2:f[0-9]+]]
-; 32-DAG: mtc1 $7, $[[F3:f[0-9]+]]
-; 32: c.eq.s $[[F2]], $[[F3]]
-; 32: movt.s $f14, $f12, $fcc0
-; 32: mov.s $f0, $f14
-
-; 32R2-DAG: mtc1 $6, $[[F2:f[0-9]+]]
-; 32R2-DAG: mtc1 $7, $[[F3:f[0-9]+]]
-; 32R2: c.eq.s $[[F2]], $[[F3]]
-; 32R2: movt.s $f14, $f12, $fcc0
-; 32R2: mov.s $f0, $f14
-
-; 32R6-DAG: mtc1 $6, $[[F2:f[0-9]+]]
-; 32R6-DAG: mtc1 $7, $[[F3:f[0-9]+]]
-; 32R6: cmp.eq.s $[[CC:f0]], $[[F2]], $[[F3]]
-; 32R6: sel.s $[[CC]], $f14, $f12
-
-; 64: c.eq.s $f14, $f15
-; 64: movt.s $f13, $f12, $fcc0
-; 64: mov.s $f0, $f13
-
-; 64R2: c.eq.s $f14, $f15
-; 64R2: movt.s $f13, $f12, $fcc0
-; 64R2: mov.s $f0, $f13
-
-; 64R6: cmp.eq.s $[[CC:f0]], $f14, $f15
-; 64R6: sel.s $[[CC]], $f13, $f12
-
%cmp = fcmp oeq float %f2, %f3
%cond = select i1 %cmp, float %f0, float %f1
ret float %cond
}
define float @f32_fcmp_olt_f32_val(float %f0, float %f1, float %f2, float %f3) nounwind readnone {
+; 32-LABEL: f32_fcmp_olt_f32_val:
+; 32: # %bb.0: # %entry
+; 32-NEXT: mtc1 $7, $f0
+; 32-NEXT: mtc1 $6, $f1
+; 32-NEXT: c.olt.s $f1, $f0
+; 32-NEXT: movt.s $f14, $f12, $fcc0
+; 32-NEXT: jr $ra
+; 32-NEXT: mov.s $f0, $f14
+;
+; 32R2-LABEL: f32_fcmp_olt_f32_val:
+; 32R2: # %bb.0: # %entry
+; 32R2-NEXT: mtc1 $7, $f0
+; 32R2-NEXT: mtc1 $6, $f1
+; 32R2-NEXT: c.olt.s $f1, $f0
+; 32R2-NEXT: movt.s $f14, $f12, $fcc0
+; 32R2-NEXT: jr $ra
+; 32R2-NEXT: mov.s $f0, $f14
+;
+; 32R6-LABEL: f32_fcmp_olt_f32_val:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: mtc1 $7, $f0
+; 32R6-NEXT: mtc1 $6, $f1
+; 32R6-NEXT: cmp.lt.s $f0, $f1, $f0
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: sel.s $f0, $f14, $f12
+;
+; 64-LABEL: f32_fcmp_olt_f32_val:
+; 64: # %bb.0: # %entry
+; 64-NEXT: c.olt.s $f14, $f15
+; 64-NEXT: movt.s $f13, $f12, $fcc0
+; 64-NEXT: jr $ra
+; 64-NEXT: mov.s $f0, $f13
+;
+; 64R2-LABEL: f32_fcmp_olt_f32_val:
+; 64R2: # %bb.0: # %entry
+; 64R2-NEXT: c.olt.s $f14, $f15
+; 64R2-NEXT: movt.s $f13, $f12, $fcc0
+; 64R2-NEXT: jr $ra
+; 64R2-NEXT: mov.s $f0, $f13
+;
+; 64R6-LABEL: f32_fcmp_olt_f32_val:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: cmp.lt.s $f0, $f14, $f15
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: sel.s $f0, $f13, $f12
entry:
-; ALL-LABEL: f32_fcmp_olt_f32_val:
-
-; 32-DAG: mtc1 $6, $[[F2:f[0-9]+]]
-; 32-DAG: mtc1 $7, $[[F3:f[0-9]+]]
-; 32: c.olt.s $[[F2]], $[[F3]]
-; 32: movt.s $f14, $f12, $fcc0
-; 32: mov.s $f0, $f14
-
-; 32R2-DAG: mtc1 $6, $[[F2:f[0-9]+]]
-; 32R2-DAG: mtc1 $7, $[[F3:f[0-9]+]]
-; 32R2: c.olt.s $[[F2]], $[[F3]]
-; 32R2: movt.s $f14, $f12, $fcc0
-; 32R2: mov.s $f0, $f14
-
-; 32R6-DAG: mtc1 $6, $[[F2:f[0-9]+]]
-; 32R6-DAG: mtc1 $7, $[[F3:f[0-9]+]]
-; 32R6: cmp.lt.s $[[CC:f0]], $[[F2]], $[[F3]]
-; 32R6: sel.s $[[CC]], $f14, $f12
-
-; 64: c.olt.s $f14, $f15
-; 64: movt.s $f13, $f12, $fcc0
-; 64: mov.s $f0, $f13
-
-; 64R2: c.olt.s $f14, $f15
-; 64R2: movt.s $f13, $f12, $fcc0
-; 64R2: mov.s $f0, $f13
-
-; 64R6: cmp.lt.s $[[CC:f0]], $f14, $f15
-; 64R6: sel.s $[[CC]], $f13, $f12
-
%cmp = fcmp olt float %f2, %f3
%cond = select i1 %cmp, float %f0, float %f1
ret float %cond
}
define float @f32_fcmp_ogt_f32_val(float %f0, float %f1, float %f2, float %f3) nounwind readnone {
+; 32-LABEL: f32_fcmp_ogt_f32_val:
+; 32: # %bb.0: # %entry
+; 32-NEXT: mtc1 $7, $f0
+; 32-NEXT: mtc1 $6, $f1
+; 32-NEXT: c.ule.s $f1, $f0
+; 32-NEXT: movf.s $f14, $f12, $fcc0
+; 32-NEXT: jr $ra
+; 32-NEXT: mov.s $f0, $f14
+;
+; 32R2-LABEL: f32_fcmp_ogt_f32_val:
+; 32R2: # %bb.0: # %entry
+; 32R2-NEXT: mtc1 $7, $f0
+; 32R2-NEXT: mtc1 $6, $f1
+; 32R2-NEXT: c.ule.s $f1, $f0
+; 32R2-NEXT: movf.s $f14, $f12, $fcc0
+; 32R2-NEXT: jr $ra
+; 32R2-NEXT: mov.s $f0, $f14
+;
+; 32R6-LABEL: f32_fcmp_ogt_f32_val:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: mtc1 $6, $f0
+; 32R6-NEXT: mtc1 $7, $f1
+; 32R6-NEXT: cmp.lt.s $f0, $f1, $f0
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: sel.s $f0, $f14, $f12
+;
+; 64-LABEL: f32_fcmp_ogt_f32_val:
+; 64: # %bb.0: # %entry
+; 64-NEXT: c.ule.s $f14, $f15
+; 64-NEXT: movf.s $f13, $f12, $fcc0
+; 64-NEXT: jr $ra
+; 64-NEXT: mov.s $f0, $f13
+;
+; 64R2-LABEL: f32_fcmp_ogt_f32_val:
+; 64R2: # %bb.0: # %entry
+; 64R2-NEXT: c.ule.s $f14, $f15
+; 64R2-NEXT: movf.s $f13, $f12, $fcc0
+; 64R2-NEXT: jr $ra
+; 64R2-NEXT: mov.s $f0, $f13
+;
+; 64R6-LABEL: f32_fcmp_ogt_f32_val:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: cmp.lt.s $f0, $f15, $f14
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: sel.s $f0, $f13, $f12
entry:
-; ALL-LABEL: f32_fcmp_ogt_f32_val:
-
-; 32-DAG: mtc1 $6, $[[F2:f[0-9]+]]
-; 32-DAG: mtc1 $7, $[[F3:f[0-9]+]]
-; 32: c.ule.s $[[F2]], $[[F3]]
-; 32: movf.s $f14, $f12, $fcc0
-; 32: mov.s $f0, $f14
-
-; 32R2-DAG: mtc1 $6, $[[F2:f[0-9]+]]
-; 32R2-DAG: mtc1 $7, $[[F3:f[0-9]+]]
-; 32R2: c.ule.s $[[F2]], $[[F3]]
-; 32R2: movf.s $f14, $f12, $fcc0
-; 32R2: mov.s $f0, $f14
-
-; 32R6-DAG: mtc1 $6, $[[F2:f[0-9]+]]
-; 32R6-DAG: mtc1 $7, $[[F3:f[0-9]+]]
-; 32R6: cmp.lt.s $[[CC:f0]], $[[F3]], $[[F2]]
-; 32R6: sel.s $[[CC]], $f14, $f12
-
-; 64: c.ule.s $f14, $f15
-; 64: movf.s $f13, $f12, $fcc0
-; 64: mov.s $f0, $f13
-
-; 64R2: c.ule.s $f14, $f15
-; 64R2: movf.s $f13, $f12, $fcc0
-; 64R2: mov.s $f0, $f13
-
-; 64R6: cmp.lt.s $[[CC:f0]], $f15, $f14
-; 64R6: sel.s $[[CC]], $f13, $f12
-
%cmp = fcmp ogt float %f2, %f3
%cond = select i1 %cmp, float %f0, float %f1
ret float %cond
}
define double @f32_fcmp_ogt_f64_val(double %f0, double %f1, float %f2, float %f3) nounwind readnone {
+; 32-LABEL: f32_fcmp_ogt_f64_val:
+; 32: # %bb.0: # %entry
+; 32-NEXT: lwc1 $f0, 20($sp)
+; 32-NEXT: lwc1 $f1, 16($sp)
+; 32-NEXT: c.ule.s $f1, $f0
+; 32-NEXT: movf.d $f14, $f12, $fcc0
+; 32-NEXT: jr $ra
+; 32-NEXT: mov.d $f0, $f14
+;
+; 32R2-LABEL: f32_fcmp_ogt_f64_val:
+; 32R2: # %bb.0: # %entry
+; 32R2-NEXT: lwc1 $f0, 20($sp)
+; 32R2-NEXT: lwc1 $f1, 16($sp)
+; 32R2-NEXT: c.ule.s $f1, $f0
+; 32R2-NEXT: movf.d $f14, $f12, $fcc0
+; 32R2-NEXT: jr $ra
+; 32R2-NEXT: mov.d $f0, $f14
+;
+; 32R6-LABEL: f32_fcmp_ogt_f64_val:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: lwc1 $f0, 16($sp)
+; 32R6-NEXT: lwc1 $f1, 20($sp)
+; 32R6-NEXT: cmp.lt.s $f0, $f1, $f0
+; 32R6-NEXT: mfc1 $1, $f0
+; 32R6-NEXT: mtc1 $1, $f0
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: sel.d $f0, $f14, $f12
+;
+; 64-LABEL: f32_fcmp_ogt_f64_val:
+; 64: # %bb.0: # %entry
+; 64-NEXT: c.ule.s $f14, $f15
+; 64-NEXT: movf.d $f13, $f12, $fcc0
+; 64-NEXT: jr $ra
+; 64-NEXT: mov.d $f0, $f13
+;
+; 64R2-LABEL: f32_fcmp_ogt_f64_val:
+; 64R2: # %bb.0: # %entry
+; 64R2-NEXT: c.ule.s $f14, $f15
+; 64R2-NEXT: movf.d $f13, $f12, $fcc0
+; 64R2-NEXT: jr $ra
+; 64R2-NEXT: mov.d $f0, $f13
+;
+; 64R6-LABEL: f32_fcmp_ogt_f64_val:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: cmp.lt.s $f0, $f15, $f14
+; 64R6-NEXT: mfc1 $1, $f0
+; 64R6-NEXT: mtc1 $1, $f0
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: sel.d $f0, $f13, $f12
entry:
-; ALL-LABEL: f32_fcmp_ogt_f64_val:
-
-; 32-DAG: lwc1 $[[F2:f[0-9]+]], 16($sp)
-; 32-DAG: lwc1 $[[F3:f[0-9]+]], 20($sp)
-; 32: c.ule.s $[[F2]], $[[F3]]
-; 32: movf.d $f14, $f12, $fcc0
-; 32: mov.d $f0, $f14
-
-; 32R2-DAG: lwc1 $[[F2:f[0-9]+]], 16($sp)
-; 32R2-DAG: lwc1 $[[F3:f[0-9]+]], 20($sp)
-; 32R2: c.ule.s $[[F2]], $[[F3]]
-; 32R2: movf.d $f14, $f12, $fcc0
-; 32R2: mov.d $f0, $f14
-
-; 32R6-DAG: lwc1 $[[F2:f[0-9]+]], 16($sp)
-; 32R6-DAG: lwc1 $[[F3:f[0-9]+]], 20($sp)
-; 32R6: cmp.lt.s $[[CC:f0]], $[[F3]], $[[F2]]
-; 32R6: sel.d $[[CC]], $f14, $f12
-
-; 64: c.ule.s $f14, $f15
-; 64: movf.d $f13, $f12, $fcc0
-; 64: mov.d $f0, $f13
-
-; 64R2: c.ule.s $f14, $f15
-; 64R2: movf.d $f13, $f12, $fcc0
-; 64R2: mov.d $f0, $f13
-
-; 64R6: cmp.lt.s $[[CC:f0]], $f15, $f14
-; 64R6: sel.d $[[CC]], $f13, $f12
-
%cmp = fcmp ogt float %f2, %f3
%cond = select i1 %cmp, double %f0, double %f1
ret double %cond
}
define double @f64_fcmp_oeq_f64_val(double %f0, double %f1, double %f2, double %f3) nounwind readnone {
+; 32-LABEL: f64_fcmp_oeq_f64_val:
+; 32: # %bb.0: # %entry
+; 32-NEXT: ldc1 $f0, 24($sp)
+; 32-NEXT: ldc1 $f2, 16($sp)
+; 32-NEXT: c.eq.d $f2, $f0
+; 32-NEXT: movt.d $f14, $f12, $fcc0
+; 32-NEXT: jr $ra
+; 32-NEXT: mov.d $f0, $f14
+;
+; 32R2-LABEL: f64_fcmp_oeq_f64_val:
+; 32R2: # %bb.0: # %entry
+; 32R2-NEXT: ldc1 $f0, 24($sp)
+; 32R2-NEXT: ldc1 $f2, 16($sp)
+; 32R2-NEXT: c.eq.d $f2, $f0
+; 32R2-NEXT: movt.d $f14, $f12, $fcc0
+; 32R2-NEXT: jr $ra
+; 32R2-NEXT: mov.d $f0, $f14
+;
+; 32R6-LABEL: f64_fcmp_oeq_f64_val:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: ldc1 $f0, 24($sp)
+; 32R6-NEXT: ldc1 $f1, 16($sp)
+; 32R6-NEXT: cmp.eq.d $f0, $f1, $f0
+; 32R6-NEXT: mfc1 $1, $f0
+; 32R6-NEXT: mtc1 $1, $f0
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: sel.d $f0, $f14, $f12
+;
+; 64-LABEL: f64_fcmp_oeq_f64_val:
+; 64: # %bb.0: # %entry
+; 64-NEXT: c.eq.d $f14, $f15
+; 64-NEXT: movt.d $f13, $f12, $fcc0
+; 64-NEXT: jr $ra
+; 64-NEXT: mov.d $f0, $f13
+;
+; 64R2-LABEL: f64_fcmp_oeq_f64_val:
+; 64R2: # %bb.0: # %entry
+; 64R2-NEXT: c.eq.d $f14, $f15
+; 64R2-NEXT: movt.d $f13, $f12, $fcc0
+; 64R2-NEXT: jr $ra
+; 64R2-NEXT: mov.d $f0, $f13
+;
+; 64R6-LABEL: f64_fcmp_oeq_f64_val:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: cmp.eq.d $f0, $f14, $f15
+; 64R6-NEXT: mfc1 $1, $f0
+; 64R6-NEXT: mtc1 $1, $f0
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: sel.d $f0, $f13, $f12
entry:
-; ALL-LABEL: f64_fcmp_oeq_f64_val:
-
-; 32-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp)
-; 32-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp)
-; 32: c.eq.d $[[F2]], $[[F3]]
-; 32: movt.d $f14, $f12, $fcc0
-; 32: mov.d $f0, $f14
-
-; 32R2-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp)
-; 32R2-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp)
-; 32R2: c.eq.d $[[F2]], $[[F3]]
-; 32R2: movt.d $f14, $f12, $fcc0
-; 32R2: mov.d $f0, $f14
-
-; 32R6-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp)
-; 32R6-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp)
-; 32R6: cmp.eq.d $[[CC:f0]], $[[F2]], $[[F3]]
-; 32R6: sel.d $[[CC]], $f14, $f12
-
-; 64: c.eq.d $f14, $f15
-; 64: movt.d $f13, $f12, $fcc0
-; 64: mov.d $f0, $f13
-
-; 64R2: c.eq.d $f14, $f15
-; 64R2: movt.d $f13, $f12, $fcc0
-; 64R2: mov.d $f0, $f13
-
-; 64R6: cmp.eq.d $[[CC:f0]], $f14, $f15
-; 64R6: sel.d $[[CC]], $f13, $f12
-
%cmp = fcmp oeq double %f2, %f3
%cond = select i1 %cmp, double %f0, double %f1
ret double %cond
}
define double @f64_fcmp_olt_f64_val(double %f0, double %f1, double %f2, double %f3) nounwind readnone {
+; 32-LABEL: f64_fcmp_olt_f64_val:
+; 32: # %bb.0: # %entry
+; 32-NEXT: ldc1 $f0, 24($sp)
+; 32-NEXT: ldc1 $f2, 16($sp)
+; 32-NEXT: c.olt.d $f2, $f0
+; 32-NEXT: movt.d $f14, $f12, $fcc0
+; 32-NEXT: jr $ra
+; 32-NEXT: mov.d $f0, $f14
+;
+; 32R2-LABEL: f64_fcmp_olt_f64_val:
+; 32R2: # %bb.0: # %entry
+; 32R2-NEXT: ldc1 $f0, 24($sp)
+; 32R2-NEXT: ldc1 $f2, 16($sp)
+; 32R2-NEXT: c.olt.d $f2, $f0
+; 32R2-NEXT: movt.d $f14, $f12, $fcc0
+; 32R2-NEXT: jr $ra
+; 32R2-NEXT: mov.d $f0, $f14
+;
+; 32R6-LABEL: f64_fcmp_olt_f64_val:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: ldc1 $f0, 24($sp)
+; 32R6-NEXT: ldc1 $f1, 16($sp)
+; 32R6-NEXT: cmp.lt.d $f0, $f1, $f0
+; 32R6-NEXT: mfc1 $1, $f0
+; 32R6-NEXT: mtc1 $1, $f0
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: sel.d $f0, $f14, $f12
+;
+; 64-LABEL: f64_fcmp_olt_f64_val:
+; 64: # %bb.0: # %entry
+; 64-NEXT: c.olt.d $f14, $f15
+; 64-NEXT: movt.d $f13, $f12, $fcc0
+; 64-NEXT: jr $ra
+; 64-NEXT: mov.d $f0, $f13
+;
+; 64R2-LABEL: f64_fcmp_olt_f64_val:
+; 64R2: # %bb.0: # %entry
+; 64R2-NEXT: c.olt.d $f14, $f15
+; 64R2-NEXT: movt.d $f13, $f12, $fcc0
+; 64R2-NEXT: jr $ra
+; 64R2-NEXT: mov.d $f0, $f13
+;
+; 64R6-LABEL: f64_fcmp_olt_f64_val:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: cmp.lt.d $f0, $f14, $f15
+; 64R6-NEXT: mfc1 $1, $f0
+; 64R6-NEXT: mtc1 $1, $f0
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: sel.d $f0, $f13, $f12
entry:
-; ALL-LABEL: f64_fcmp_olt_f64_val:
-
-; 32-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp)
-; 32-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp)
-; 32: c.olt.d $[[F2]], $[[F3]]
-; 32: movt.d $f14, $f12, $fcc0
-; 32: mov.d $f0, $f14
-
-; 32R2-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp)
-; 32R2-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp)
-; 32R2: c.olt.d $[[F2]], $[[F3]]
-; 32R2: movt.d $f14, $f12, $fcc0
-; 32R2: mov.d $f0, $f14
-
-; 32R6-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp)
-; 32R6-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp)
-; 32R6: cmp.lt.d $[[CC:f0]], $[[F2]], $[[F3]]
-; 32R6: sel.d $[[CC]], $f14, $f12
-
-; 64: c.olt.d $f14, $f15
-; 64: movt.d $f13, $f12, $fcc0
-; 64: mov.d $f0, $f13
-
-; 64R2: c.olt.d $f14, $f15
-; 64R2: movt.d $f13, $f12, $fcc0
-; 64R2: mov.d $f0, $f13
-
-; 64R6: cmp.lt.d $[[CC:f0]], $f14, $f15
-; 64R6: sel.d $[[CC]], $f13, $f12
-
%cmp = fcmp olt double %f2, %f3
%cond = select i1 %cmp, double %f0, double %f1
ret double %cond
}
define double @f64_fcmp_ogt_f64_val(double %f0, double %f1, double %f2, double %f3) nounwind readnone {
+; 32-LABEL: f64_fcmp_ogt_f64_val:
+; 32: # %bb.0: # %entry
+; 32-NEXT: ldc1 $f0, 24($sp)
+; 32-NEXT: ldc1 $f2, 16($sp)
+; 32-NEXT: c.ule.d $f2, $f0
+; 32-NEXT: movf.d $f14, $f12, $fcc0
+; 32-NEXT: jr $ra
+; 32-NEXT: mov.d $f0, $f14
+;
+; 32R2-LABEL: f64_fcmp_ogt_f64_val:
+; 32R2: # %bb.0: # %entry
+; 32R2-NEXT: ldc1 $f0, 24($sp)
+; 32R2-NEXT: ldc1 $f2, 16($sp)
+; 32R2-NEXT: c.ule.d $f2, $f0
+; 32R2-NEXT: movf.d $f14, $f12, $fcc0
+; 32R2-NEXT: jr $ra
+; 32R2-NEXT: mov.d $f0, $f14
+;
+; 32R6-LABEL: f64_fcmp_ogt_f64_val:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: ldc1 $f0, 16($sp)
+; 32R6-NEXT: ldc1 $f1, 24($sp)
+; 32R6-NEXT: cmp.lt.d $f0, $f1, $f0
+; 32R6-NEXT: mfc1 $1, $f0
+; 32R6-NEXT: mtc1 $1, $f0
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: sel.d $f0, $f14, $f12
+;
+; 64-LABEL: f64_fcmp_ogt_f64_val:
+; 64: # %bb.0: # %entry
+; 64-NEXT: c.ule.d $f14, $f15
+; 64-NEXT: movf.d $f13, $f12, $fcc0
+; 64-NEXT: jr $ra
+; 64-NEXT: mov.d $f0, $f13
+;
+; 64R2-LABEL: f64_fcmp_ogt_f64_val:
+; 64R2: # %bb.0: # %entry
+; 64R2-NEXT: c.ule.d $f14, $f15
+; 64R2-NEXT: movf.d $f13, $f12, $fcc0
+; 64R2-NEXT: jr $ra
+; 64R2-NEXT: mov.d $f0, $f13
+;
+; 64R6-LABEL: f64_fcmp_ogt_f64_val:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: cmp.lt.d $f0, $f15, $f14
+; 64R6-NEXT: mfc1 $1, $f0
+; 64R6-NEXT: mtc1 $1, $f0
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: sel.d $f0, $f13, $f12
entry:
-; ALL-LABEL: f64_fcmp_ogt_f64_val:
-
-; 32-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp)
-; 32-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp)
-; 32: c.ule.d $[[F2]], $[[F3]]
-; 32: movf.d $f14, $f12, $fcc0
-; 32: mov.d $f0, $f14
-
-; 32R2-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp)
-; 32R2-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp)
-; 32R2: c.ule.d $[[F2]], $[[F3]]
-; 32R2: movf.d $f14, $f12, $fcc0
-; 32R2: mov.d $f0, $f14
-
-; 32R6-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp)
-; 32R6-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp)
-; 32R6: cmp.lt.d $[[CC:f0]], $[[F3]], $[[F2]]
-; 32R6: sel.d $[[CC]], $f14, $f12
-
-; 64: c.ule.d $f14, $f15
-; 64: movf.d $f13, $f12, $fcc0
-; 64: mov.d $f0, $f13
-
-; 64R2: c.ule.d $f14, $f15
-; 64R2: movf.d $f13, $f12, $fcc0
-; 64R2: mov.d $f0, $f13
-
-; 64R6: cmp.lt.d $[[CC:f0]], $f15, $f14
-; 64R6: sel.d $[[CC]], $f13, $f12
-
%cmp = fcmp ogt double %f2, %f3
%cond = select i1 %cmp, double %f0, double %f1
ret double %cond
}
define float @f64_fcmp_ogt_f32_val(float %f0, float %f1, double %f2, double %f3) nounwind readnone {
+; 32-LABEL: f64_fcmp_ogt_f32_val:
+; 32: # %bb.0: # %entry
+; 32-NEXT: mtc1 $6, $f0
+; 32-NEXT: mtc1 $7, $f1
+; 32-NEXT: ldc1 $f2, 16($sp)
+; 32-NEXT: c.ule.d $f0, $f2
+; 32-NEXT: movf.s $f14, $f12, $fcc0
+; 32-NEXT: jr $ra
+; 32-NEXT: mov.s $f0, $f14
+;
+; 32R2-LABEL: f64_fcmp_ogt_f32_val:
+; 32R2: # %bb.0: # %entry
+; 32R2-NEXT: mtc1 $6, $f0
+; 32R2-NEXT: mthc1 $7, $f0
+; 32R2-NEXT: ldc1 $f2, 16($sp)
+; 32R2-NEXT: c.ule.d $f0, $f2
+; 32R2-NEXT: movf.s $f14, $f12, $fcc0
+; 32R2-NEXT: jr $ra
+; 32R2-NEXT: mov.s $f0, $f14
+;
+; 32R6-LABEL: f64_fcmp_ogt_f32_val:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: mtc1 $6, $f0
+; 32R6-NEXT: mthc1 $7, $f0
+; 32R6-NEXT: ldc1 $f1, 16($sp)
+; 32R6-NEXT: cmp.lt.d $f0, $f1, $f0
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: sel.s $f0, $f14, $f12
+;
+; 64-LABEL: f64_fcmp_ogt_f32_val:
+; 64: # %bb.0: # %entry
+; 64-NEXT: c.ule.d $f14, $f15
+; 64-NEXT: movf.s $f13, $f12, $fcc0
+; 64-NEXT: jr $ra
+; 64-NEXT: mov.s $f0, $f13
+;
+; 64R2-LABEL: f64_fcmp_ogt_f32_val:
+; 64R2: # %bb.0: # %entry
+; 64R2-NEXT: c.ule.d $f14, $f15
+; 64R2-NEXT: movf.s $f13, $f12, $fcc0
+; 64R2-NEXT: jr $ra
+; 64R2-NEXT: mov.s $f0, $f13
+;
+; 64R6-LABEL: f64_fcmp_ogt_f32_val:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: cmp.lt.d $f0, $f15, $f14
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: sel.s $f0, $f13, $f12
entry:
-; ALL-LABEL: f64_fcmp_ogt_f32_val:
-
-; 32-DAG: mtc1 $6, $[[F2:f[1-3]*[02468]+]]
-; 32-DAG: mtc1 $7, $[[F2H:f[1-3]*[13579]+]]
-; 32-DAG: ldc1 $[[F3:f[0-9]+]], 16($sp)
-; 32: c.ule.d $[[F2]], $[[F3]]
-; 32: movf.s $f14, $f12, $fcc0
-; 32: mov.s $f0, $f14
-
-; 32R2-DAG: mtc1 $6, $[[F2:f[0-9]+]]
-; 32R2-DAG: mthc1 $7, $[[F2]]
-; 32R2-DAG: ldc1 $[[F3:f[0-9]+]], 16($sp)
-; 32R2: c.ule.d $[[F2]], $[[F3]]
-; 32R2: movf.s $f14, $f12, $fcc0
-; 32R2: mov.s $f0, $f14
-
-; 32R6-DAG: mtc1 $6, $[[F2:f[0-9]+]]
-; 32R6-DAG: mthc1 $7, $[[F2]]
-; 32R6-DAG: ldc1 $[[F3:f[0-9]+]], 16($sp)
-; 32R6: cmp.lt.d $[[CC:f0]], $[[F3]], $[[F2]]
-; 32R6: sel.s $[[CC]], $f14, $f12
-
-; 64: c.ule.d $f14, $f15
-; 64: movf.s $f13, $f12, $fcc0
-; 64: mov.s $f0, $f13
-
-; 64R2: c.ule.d $f14, $f15
-; 64R2: movf.s $f13, $f12, $fcc0
-; 64R2: mov.s $f0, $f13
-
-; 64R6: cmp.lt.d $[[CC:f0]], $f15, $f14
-; 64R6: sel.s $[[CC]], $f13, $f12
-
%cmp = fcmp ogt double %f2, %f3
%cond = select i1 %cmp, float %f0, float %f1
ret float %cond
}
define i32 @f32_fcmp_oeq_i32_val(i32 signext %f0, i32 signext %f1, float %f2, float %f3) nounwind readnone {
+; 32-LABEL: f32_fcmp_oeq_i32_val:
+; 32: # %bb.0: # %entry
+; 32-NEXT: mtc1 $7, $f0
+; 32-NEXT: mtc1 $6, $f1
+; 32-NEXT: c.eq.s $f1, $f0
+; 32-NEXT: movt $5, $4, $fcc0
+; 32-NEXT: jr $ra
+; 32-NEXT: move $2, $5
+;
+; 32R2-LABEL: f32_fcmp_oeq_i32_val:
+; 32R2: # %bb.0: # %entry
+; 32R2-NEXT: mtc1 $7, $f0
+; 32R2-NEXT: mtc1 $6, $f1
+; 32R2-NEXT: c.eq.s $f1, $f0
+; 32R2-NEXT: movt $5, $4, $fcc0
+; 32R2-NEXT: jr $ra
+; 32R2-NEXT: move $2, $5
+;
+; 32R6-LABEL: f32_fcmp_oeq_i32_val:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: mtc1 $7, $f0
+; 32R6-NEXT: mtc1 $6, $f1
+; 32R6-NEXT: cmp.eq.s $f0, $f1, $f0
+; 32R6-NEXT: mfc1 $1, $f0
+; 32R6-NEXT: andi $1, $1, 1
+; 32R6-NEXT: seleqz $2, $5, $1
+; 32R6-NEXT: selnez $1, $4, $1
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: or $2, $1, $2
+;
+; 64-LABEL: f32_fcmp_oeq_i32_val:
+; 64: # %bb.0: # %entry
+; 64-NEXT: c.eq.s $f14, $f15
+; 64-NEXT: movt $5, $4, $fcc0
+; 64-NEXT: jr $ra
+; 64-NEXT: move $2, $5
+;
+; 64R2-LABEL: f32_fcmp_oeq_i32_val:
+; 64R2: # %bb.0: # %entry
+; 64R2-NEXT: c.eq.s $f14, $f15
+; 64R2-NEXT: movt $5, $4, $fcc0
+; 64R2-NEXT: jr $ra
+; 64R2-NEXT: move $2, $5
+;
+; 64R6-LABEL: f32_fcmp_oeq_i32_val:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: cmp.eq.s $f0, $f14, $f15
+; 64R6-NEXT: mfc1 $1, $f0
+; 64R6-NEXT: andi $1, $1, 1
+; 64R6-NEXT: seleqz $2, $5, $1
+; 64R6-NEXT: selnez $1, $4, $1
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: or $2, $1, $2
entry:
-; ALL-LABEL: f32_fcmp_oeq_i32_val:
-
-; 32-DAG: mtc1 $6, $[[F2:f[0-9]+]]
-; 32-DAG: mtc1 $7, $[[F3:f[0-9]+]]
-; 32: c.eq.s $[[F2]], $[[F3]]
-; 32: movt $5, $4, $fcc0
-; 32: move $2, $5
-
-; 32R2-DAG: mtc1 $6, $[[F2:f[0-9]+]]
-; 32R2-DAG: mtc1 $7, $[[F3:f[0-9]+]]
-; 32R2: c.eq.s $[[F2]], $[[F3]]
-; 32R2: movt $5, $4, $fcc0
-; 32R2: move $2, $5
-
-; 32R6-DAG: mtc1 $6, $[[F2:f[0-9]+]]
-; 32R6-DAG: mtc1 $7, $[[F3:f[0-9]+]]
-; 32R6: cmp.eq.s $[[CC:f[0-9]+]], $[[F2]], $[[F3]]
-; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
-; 32R6: andi $[[CCGPR]], $[[CCGPR]], 1
-; 32R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; 32R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
-; 32R6: or $2, $[[NE]], $[[EQ]]
-
-; 64: c.eq.s $f14, $f15
-; 64: movt $5, $4, $fcc0
-; 64: move $2, $5
-
-; 64R2: c.eq.s $f14, $f15
-; 64R2: movt $5, $4, $fcc0
-; 64R2: move $2, $5
-
-; 64R6: cmp.eq.s $[[CC:f[0-9]+]], $f14, $f15
-; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
-; 64R6: andi $[[CCGPR]], $[[CCGPR]], 1
-; 64R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; 64R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
-; 64R6: or $2, $[[NE]], $[[EQ]]
-
%cmp = fcmp oeq float %f2, %f3
%cond = select i1 %cmp, i32 %f0, i32 %f1
ret i32 %cond
}
define i32 @f32_fcmp_olt_i32_val(i32 signext %f0, i32 signext %f1, float %f2, float %f3) nounwind readnone {
+; 32-LABEL: f32_fcmp_olt_i32_val:
+; 32: # %bb.0: # %entry
+; 32-NEXT: mtc1 $7, $f0
+; 32-NEXT: mtc1 $6, $f1
+; 32-NEXT: c.olt.s $f1, $f0
+; 32-NEXT: movt $5, $4, $fcc0
+; 32-NEXT: jr $ra
+; 32-NEXT: move $2, $5
+;
+; 32R2-LABEL: f32_fcmp_olt_i32_val:
+; 32R2: # %bb.0: # %entry
+; 32R2-NEXT: mtc1 $7, $f0
+; 32R2-NEXT: mtc1 $6, $f1
+; 32R2-NEXT: c.olt.s $f1, $f0
+; 32R2-NEXT: movt $5, $4, $fcc0
+; 32R2-NEXT: jr $ra
+; 32R2-NEXT: move $2, $5
+;
+; 32R6-LABEL: f32_fcmp_olt_i32_val:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: mtc1 $7, $f0
+; 32R6-NEXT: mtc1 $6, $f1
+; 32R6-NEXT: cmp.lt.s $f0, $f1, $f0
+; 32R6-NEXT: mfc1 $1, $f0
+; 32R6-NEXT: andi $1, $1, 1
+; 32R6-NEXT: seleqz $2, $5, $1
+; 32R6-NEXT: selnez $1, $4, $1
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: or $2, $1, $2
+;
+; 64-LABEL: f32_fcmp_olt_i32_val:
+; 64: # %bb.0: # %entry
+; 64-NEXT: c.olt.s $f14, $f15
+; 64-NEXT: movt $5, $4, $fcc0
+; 64-NEXT: jr $ra
+; 64-NEXT: move $2, $5
+;
+; 64R2-LABEL: f32_fcmp_olt_i32_val:
+; 64R2: # %bb.0: # %entry
+; 64R2-NEXT: c.olt.s $f14, $f15
+; 64R2-NEXT: movt $5, $4, $fcc0
+; 64R2-NEXT: jr $ra
+; 64R2-NEXT: move $2, $5
+;
+; 64R6-LABEL: f32_fcmp_olt_i32_val:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: cmp.lt.s $f0, $f14, $f15
+; 64R6-NEXT: mfc1 $1, $f0
+; 64R6-NEXT: andi $1, $1, 1
+; 64R6-NEXT: seleqz $2, $5, $1
+; 64R6-NEXT: selnez $1, $4, $1
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: or $2, $1, $2
entry:
-; ALL-LABEL: f32_fcmp_olt_i32_val:
-
-; 32-DAG: mtc1 $6, $[[F2:f[0-9]+]]
-; 32-DAG: mtc1 $7, $[[F3:f[0-9]+]]
-; 32: c.olt.s $[[F2]], $[[F3]]
-; 32: movt $5, $4, $fcc0
-; 32: move $2, $5
-
-; 32R2-DAG: mtc1 $6, $[[F2:f[0-9]+]]
-; 32R2-DAG: mtc1 $7, $[[F3:f[0-9]+]]
-; 32R2: c.olt.s $[[F2]], $[[F3]]
-; 32R2: movt $5, $4, $fcc0
-; 32R2: move $2, $5
-
-; 32R6-DAG: mtc1 $6, $[[F2:f[0-9]+]]
-; 32R6-DAG: mtc1 $7, $[[F3:f[0-9]+]]
-; 32R6: cmp.lt.s $[[CC:f[0-9]+]], $[[F2]], $[[F3]]
-; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
-; 32R6: andi $[[CCGPR]], $[[CCGPR]], 1
-; 32R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; 32R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
-; 32R6: or $2, $[[NE]], $[[EQ]]
-
-; 64: c.olt.s $f14, $f15
-; 64: movt $5, $4, $fcc0
-; 64: move $2, $5
-
-; 64R2: c.olt.s $f14, $f15
-; 64R2: movt $5, $4, $fcc0
-; 64R2: move $2, $5
-
-; 64R6: cmp.lt.s $[[CC:f[0-9]+]], $f14, $f15
-; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
-; 64R6: andi $[[CCGPR]], $[[CCGPR]], 1
-; 64R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; 64R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
-; 64R6: or $2, $[[NE]], $[[EQ]]
%cmp = fcmp olt float %f2, %f3
%cond = select i1 %cmp, i32 %f0, i32 %f1
ret i32 %cond
}
define i32 @f32_fcmp_ogt_i32_val(i32 signext %f0, i32 signext %f1, float %f2, float %f3) nounwind readnone {
+; 32-LABEL: f32_fcmp_ogt_i32_val:
+; 32: # %bb.0: # %entry
+; 32-NEXT: mtc1 $7, $f0
+; 32-NEXT: mtc1 $6, $f1
+; 32-NEXT: c.ule.s $f1, $f0
+; 32-NEXT: movf $5, $4, $fcc0
+; 32-NEXT: jr $ra
+; 32-NEXT: move $2, $5
+;
+; 32R2-LABEL: f32_fcmp_ogt_i32_val:
+; 32R2: # %bb.0: # %entry
+; 32R2-NEXT: mtc1 $7, $f0
+; 32R2-NEXT: mtc1 $6, $f1
+; 32R2-NEXT: c.ule.s $f1, $f0
+; 32R2-NEXT: movf $5, $4, $fcc0
+; 32R2-NEXT: jr $ra
+; 32R2-NEXT: move $2, $5
+;
+; 32R6-LABEL: f32_fcmp_ogt_i32_val:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: mtc1 $6, $f0
+; 32R6-NEXT: mtc1 $7, $f1
+; 32R6-NEXT: cmp.lt.s $f0, $f1, $f0
+; 32R6-NEXT: mfc1 $1, $f0
+; 32R6-NEXT: andi $1, $1, 1
+; 32R6-NEXT: seleqz $2, $5, $1
+; 32R6-NEXT: selnez $1, $4, $1
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: or $2, $1, $2
+;
+; 64-LABEL: f32_fcmp_ogt_i32_val:
+; 64: # %bb.0: # %entry
+; 64-NEXT: c.ule.s $f14, $f15
+; 64-NEXT: movf $5, $4, $fcc0
+; 64-NEXT: jr $ra
+; 64-NEXT: move $2, $5
+;
+; 64R2-LABEL: f32_fcmp_ogt_i32_val:
+; 64R2: # %bb.0: # %entry
+; 64R2-NEXT: c.ule.s $f14, $f15
+; 64R2-NEXT: movf $5, $4, $fcc0
+; 64R2-NEXT: jr $ra
+; 64R2-NEXT: move $2, $5
+;
+; 64R6-LABEL: f32_fcmp_ogt_i32_val:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: cmp.lt.s $f0, $f15, $f14
+; 64R6-NEXT: mfc1 $1, $f0
+; 64R6-NEXT: andi $1, $1, 1
+; 64R6-NEXT: seleqz $2, $5, $1
+; 64R6-NEXT: selnez $1, $4, $1
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: or $2, $1, $2
entry:
-; ALL-LABEL: f32_fcmp_ogt_i32_val:
-
-; 32-DAG: mtc1 $6, $[[F2:f[0-9]+]]
-; 32-DAG: mtc1 $7, $[[F3:f[0-9]+]]
-; 32: c.ule.s $[[F2]], $[[F3]]
-; 32: movf $5, $4, $fcc0
-; 32: move $2, $5
-
-; 32R2-DAG: mtc1 $6, $[[F2:f[0-9]+]]
-; 32R2-DAG: mtc1 $7, $[[F3:f[0-9]+]]
-; 32R2: c.ule.s $[[F2]], $[[F3]]
-; 32R2: movf $5, $4, $fcc0
-; 32R2: move $2, $5
-
-; 32R6-DAG: mtc1 $6, $[[F2:f[0-9]+]]
-; 32R6-DAG: mtc1 $7, $[[F3:f[0-9]+]]
-; 32R6: cmp.lt.s $[[CC:f[0-9]+]], $[[F3]], $[[F2]]
-; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
-; 32R6: andi $[[CCGPR]], $[[CCGPR]], 1
-; 32R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; 32R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
-; 32R6: or $2, $[[NE]], $[[EQ]]
-
-; 64: c.ule.s $f14, $f15
-; 64: movf $5, $4, $fcc0
-; 64: move $2, $5
-
-; 64R2: c.ule.s $f14, $f15
-; 64R2: movf $5, $4, $fcc0
-; 64R2: move $2, $5
-
-; 64R6: cmp.lt.s $[[CC:f[0-9]+]], $f15, $f14
-; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
-; 64R6: andi $[[CCGPR]], $[[CCGPR]], 1
-; 64R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; 64R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
-; 64R6: or $2, $[[NE]], $[[EQ]]
-
%cmp = fcmp ogt float %f2, %f3
%cond = select i1 %cmp, i32 %f0, i32 %f1
ret i32 %cond
}
define i32 @f64_fcmp_oeq_i32_val(i32 signext %f0, i32 signext %f1) nounwind readonly {
+; 32-LABEL: f64_fcmp_oeq_i32_val:
+; 32: # %bb.0: # %entry
+; 32-NEXT: lui $2, %hi(_gp_disp)
+; 32-NEXT: addiu $2, $2, %lo(_gp_disp)
+; 32-NEXT: addu $1, $2, $25
+; 32-NEXT: lw $2, %got(d3)($1)
+; 32-NEXT: ldc1 $f0, 0($2)
+; 32-NEXT: lw $1, %got(d2)($1)
+; 32-NEXT: ldc1 $f2, 0($1)
+; 32-NEXT: c.eq.d $f2, $f0
+; 32-NEXT: movt $5, $4, $fcc0
+; 32-NEXT: jr $ra
+; 32-NEXT: move $2, $5
+;
+; 32R2-LABEL: f64_fcmp_oeq_i32_val:
+; 32R2: # %bb.0: # %entry
+; 32R2-NEXT: lui $2, %hi(_gp_disp)
+; 32R2-NEXT: addiu $2, $2, %lo(_gp_disp)
+; 32R2-NEXT: addu $1, $2, $25
+; 32R2-NEXT: lw $2, %got(d3)($1)
+; 32R2-NEXT: ldc1 $f0, 0($2)
+; 32R2-NEXT: lw $1, %got(d2)($1)
+; 32R2-NEXT: ldc1 $f2, 0($1)
+; 32R2-NEXT: c.eq.d $f2, $f0
+; 32R2-NEXT: movt $5, $4, $fcc0
+; 32R2-NEXT: jr $ra
+; 32R2-NEXT: move $2, $5
+;
+; 32R6-LABEL: f64_fcmp_oeq_i32_val:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: lui $2, %hi(_gp_disp)
+; 32R6-NEXT: addiu $2, $2, %lo(_gp_disp)
+; 32R6-NEXT: addu $1, $2, $25
+; 32R6-NEXT: lw $2, %got(d3)($1)
+; 32R6-NEXT: ldc1 $f0, 0($2)
+; 32R6-NEXT: lw $1, %got(d2)($1)
+; 32R6-NEXT: ldc1 $f1, 0($1)
+; 32R6-NEXT: cmp.eq.d $f0, $f1, $f0
+; 32R6-NEXT: mfc1 $1, $f0
+; 32R6-NEXT: andi $1, $1, 1
+; 32R6-NEXT: seleqz $2, $5, $1
+; 32R6-NEXT: selnez $1, $4, $1
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: or $2, $1, $2
+;
+; 64-LABEL: f64_fcmp_oeq_i32_val:
+; 64: # %bb.0: # %entry
+; 64-NEXT: lui $1, %hi(%neg(%gp_rel(f64_fcmp_oeq_i32_val)))
+; 64-NEXT: daddu $1, $1, $25
+; 64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(f64_fcmp_oeq_i32_val)))
+; 64-NEXT: ld $2, %got_disp(d3)($1)
+; 64-NEXT: ldc1 $f0, 0($2)
+; 64-NEXT: ld $1, %got_disp(d2)($1)
+; 64-NEXT: ldc1 $f1, 0($1)
+; 64-NEXT: c.eq.d $f1, $f0
+; 64-NEXT: movt $5, $4, $fcc0
+; 64-NEXT: jr $ra
+; 64-NEXT: move $2, $5
+;
+; 64R2-LABEL: f64_fcmp_oeq_i32_val:
+; 64R2: # %bb.0: # %entry
+; 64R2-NEXT: lui $1, %hi(%neg(%gp_rel(f64_fcmp_oeq_i32_val)))
+; 64R2-NEXT: daddu $1, $1, $25
+; 64R2-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(f64_fcmp_oeq_i32_val)))
+; 64R2-NEXT: ld $2, %got_disp(d3)($1)
+; 64R2-NEXT: ldc1 $f0, 0($2)
+; 64R2-NEXT: ld $1, %got_disp(d2)($1)
+; 64R2-NEXT: ldc1 $f1, 0($1)
+; 64R2-NEXT: c.eq.d $f1, $f0
+; 64R2-NEXT: movt $5, $4, $fcc0
+; 64R2-NEXT: jr $ra
+; 64R2-NEXT: move $2, $5
+;
+; 64R6-LABEL: f64_fcmp_oeq_i32_val:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: lui $1, %hi(%neg(%gp_rel(f64_fcmp_oeq_i32_val)))
+; 64R6-NEXT: daddu $1, $1, $25
+; 64R6-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(f64_fcmp_oeq_i32_val)))
+; 64R6-NEXT: ld $2, %got_disp(d3)($1)
+; 64R6-NEXT: ldc1 $f0, 0($2)
+; 64R6-NEXT: ld $1, %got_disp(d2)($1)
+; 64R6-NEXT: ldc1 $f1, 0($1)
+; 64R6-NEXT: cmp.eq.d $f0, $f1, $f0
+; 64R6-NEXT: mfc1 $1, $f0
+; 64R6-NEXT: andi $1, $1, 1
+; 64R6-NEXT: seleqz $2, $5, $1
+; 64R6-NEXT: selnez $1, $4, $1
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: or $2, $1, $2
entry:
-; ALL-LABEL: f64_fcmp_oeq_i32_val:
-
-; 32-DAG: addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp)
-; 32-DAG: addu $[[GOT:[0-9]+]], $[[T0]], $25
-; 32-DAG: lw $[[D2:[0-9]+]], %got(d2)($1)
-; 32-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
-; 32-DAG: lw $[[D3:[0-9]+]], %got(d3)($1)
-; 32-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
-; 32: c.eq.d $[[TMP]], $[[TMP1]]
-; 32: movt $5, $4, $fcc0
-; 32: move $2, $5
-
-; 32R2-DAG: addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp)
-; 32R2-DAG: addu $[[GOT:[0-9]+]], $[[T0]], $25
-; 32R2-DAG: lw $[[D2:[0-9]+]], %got(d2)($1)
-; 32R2-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
-; 32R2-DAG: lw $[[D3:[0-9]+]], %got(d3)($1)
-; 32R2-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
-; 32R2: c.eq.d $[[TMP]], $[[TMP1]]
-; 32R2: movt $5, $4, $fcc0
-; 32R2: move $2, $5
-
-; 32R6-DAG: addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp)
-; 32R6-DAG: addu $[[GOT:[0-9]+]], $[[T0]], $25
-; 32R6-DAG: lw $[[D2:[0-9]+]], %got(d2)($1)
-; 32R6-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
-; 32R6-DAG: lw $[[D3:[0-9]+]], %got(d3)($1)
-; 32R6-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
-; 32R6: cmp.eq.d $[[CC:f[0-9]+]], $[[TMP]], $[[TMP1]]
-; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
-; 32R6: andi $[[CCGPR]], $[[CCGPR]], 1
-; 32R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; 32R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
-; 32R6: or $2, $[[NE]], $[[EQ]]
-
-; 64-DAG: daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_oeq_i32_val)))
-; 64-DAG: daddu $[[GOT:[0-9]+]], $[[T0]], $25
-; 64-DAG: ld $[[D2:[0-9]+]], %got_disp(d2)($1)
-; 64-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
-; 64-DAG: ld $[[D3:[0-9]+]], %got_disp(d3)($1)
-; 64-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
-; 64: c.eq.d $[[TMP]], $[[TMP1]]
-; 64: movt $5, $4, $fcc0
-; 64: move $2, $5
-
-; 64R2-DAG: daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_oeq_i32_val)))
-; 64R2-DAG: daddu $[[GOT:[0-9]+]], $[[T0]], $25
-; 64R2-DAG: ld $[[D2:[0-9]+]], %got_disp(d2)($1)
-; 64R2-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
-; 64R2-DAG: ld $[[D3:[0-9]+]], %got_disp(d3)($1)
-; 64R2-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
-; 64R2: c.eq.d $[[TMP]], $[[TMP1]]
-; 64R2: movt $5, $4, $fcc0
-; 64R2: move $2, $5
-
-; 64R6-DAG: daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_oeq_i32_val)))
-; 64R6-DAG: daddu $[[GOT:[0-9]+]], $[[T0]], $25
-; 64R6-DAG: ld $[[D2:[0-9]+]], %got_disp(d2)($1)
-; 64R6-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
-; 64R6-DAG: ld $[[D3:[0-9]+]], %got_disp(d3)($1)
-; 64R6-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
-; 64R6: cmp.eq.d $[[CC:f[0-9]+]], $[[TMP]], $[[TMP1]]
-; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
-; 64R6: andi $[[CCGPR]], $[[CCGPR]], 1
-; 64R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; 64R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
-; 64R6: or $2, $[[NE]], $[[EQ]]
-
%tmp = load double, double* @d2, align 8
%tmp1 = load double, double* @d3, align 8
%cmp = fcmp oeq double %tmp, %tmp1
@@ -709,75 +992,96 @@ entry:
}
define i32 @f64_fcmp_olt_i32_val(i32 signext %f0, i32 signext %f1) nounwind readonly {
+; 32-LABEL: f64_fcmp_olt_i32_val:
+; 32: # %bb.0: # %entry
+; 32-NEXT: lui $2, %hi(_gp_disp)
+; 32-NEXT: addiu $2, $2, %lo(_gp_disp)
+; 32-NEXT: addu $1, $2, $25
+; 32-NEXT: lw $2, %got(d3)($1)
+; 32-NEXT: ldc1 $f0, 0($2)
+; 32-NEXT: lw $1, %got(d2)($1)
+; 32-NEXT: ldc1 $f2, 0($1)
+; 32-NEXT: c.olt.d $f2, $f0
+; 32-NEXT: movt $5, $4, $fcc0
+; 32-NEXT: jr $ra
+; 32-NEXT: move $2, $5
+;
+; 32R2-LABEL: f64_fcmp_olt_i32_val:
+; 32R2: # %bb.0: # %entry
+; 32R2-NEXT: lui $2, %hi(_gp_disp)
+; 32R2-NEXT: addiu $2, $2, %lo(_gp_disp)
+; 32R2-NEXT: addu $1, $2, $25
+; 32R2-NEXT: lw $2, %got(d3)($1)
+; 32R2-NEXT: ldc1 $f0, 0($2)
+; 32R2-NEXT: lw $1, %got(d2)($1)
+; 32R2-NEXT: ldc1 $f2, 0($1)
+; 32R2-NEXT: c.olt.d $f2, $f0
+; 32R2-NEXT: movt $5, $4, $fcc0
+; 32R2-NEXT: jr $ra
+; 32R2-NEXT: move $2, $5
+;
+; 32R6-LABEL: f64_fcmp_olt_i32_val:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: lui $2, %hi(_gp_disp)
+; 32R6-NEXT: addiu $2, $2, %lo(_gp_disp)
+; 32R6-NEXT: addu $1, $2, $25
+; 32R6-NEXT: lw $2, %got(d3)($1)
+; 32R6-NEXT: ldc1 $f0, 0($2)
+; 32R6-NEXT: lw $1, %got(d2)($1)
+; 32R6-NEXT: ldc1 $f1, 0($1)
+; 32R6-NEXT: cmp.lt.d $f0, $f1, $f0
+; 32R6-NEXT: mfc1 $1, $f0
+; 32R6-NEXT: andi $1, $1, 1
+; 32R6-NEXT: seleqz $2, $5, $1
+; 32R6-NEXT: selnez $1, $4, $1
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: or $2, $1, $2
+;
+; 64-LABEL: f64_fcmp_olt_i32_val:
+; 64: # %bb.0: # %entry
+; 64-NEXT: lui $1, %hi(%neg(%gp_rel(f64_fcmp_olt_i32_val)))
+; 64-NEXT: daddu $1, $1, $25
+; 64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(f64_fcmp_olt_i32_val)))
+; 64-NEXT: ld $2, %got_disp(d3)($1)
+; 64-NEXT: ldc1 $f0, 0($2)
+; 64-NEXT: ld $1, %got_disp(d2)($1)
+; 64-NEXT: ldc1 $f1, 0($1)
+; 64-NEXT: c.olt.d $f1, $f0
+; 64-NEXT: movt $5, $4, $fcc0
+; 64-NEXT: jr $ra
+; 64-NEXT: move $2, $5
+;
+; 64R2-LABEL: f64_fcmp_olt_i32_val:
+; 64R2: # %bb.0: # %entry
+; 64R2-NEXT: lui $1, %hi(%neg(%gp_rel(f64_fcmp_olt_i32_val)))
+; 64R2-NEXT: daddu $1, $1, $25
+; 64R2-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(f64_fcmp_olt_i32_val)))
+; 64R2-NEXT: ld $2, %got_disp(d3)($1)
+; 64R2-NEXT: ldc1 $f0, 0($2)
+; 64R2-NEXT: ld $1, %got_disp(d2)($1)
+; 64R2-NEXT: ldc1 $f1, 0($1)
+; 64R2-NEXT: c.olt.d $f1, $f0
+; 64R2-NEXT: movt $5, $4, $fcc0
+; 64R2-NEXT: jr $ra
+; 64R2-NEXT: move $2, $5
+;
+; 64R6-LABEL: f64_fcmp_olt_i32_val:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: lui $1, %hi(%neg(%gp_rel(f64_fcmp_olt_i32_val)))
+; 64R6-NEXT: daddu $1, $1, $25
+; 64R6-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(f64_fcmp_olt_i32_val)))
+; 64R6-NEXT: ld $2, %got_disp(d3)($1)
+; 64R6-NEXT: ldc1 $f0, 0($2)
+; 64R6-NEXT: ld $1, %got_disp(d2)($1)
+; 64R6-NEXT: ldc1 $f1, 0($1)
+; 64R6-NEXT: cmp.lt.d $f0, $f1, $f0
+; 64R6-NEXT: mfc1 $1, $f0
+; 64R6-NEXT: andi $1, $1, 1
+; 64R6-NEXT: seleqz $2, $5, $1
+; 64R6-NEXT: selnez $1, $4, $1
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: or $2, $1, $2
entry:
-; ALL-LABEL: f64_fcmp_olt_i32_val:
-
-; 32-DAG: addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp)
-; 32-DAG: addu $[[GOT:[0-9]+]], $[[T0]], $25
-; 32-DAG: lw $[[D2:[0-9]+]], %got(d2)($1)
-; 32-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
-; 32-DAG: lw $[[D3:[0-9]+]], %got(d3)($1)
-; 32-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
-; 32: c.olt.d $[[TMP]], $[[TMP1]]
-; 32: movt $5, $4, $fcc0
-; 32: move $2, $5
-
-; 32R2-DAG: addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp)
-; 32R2-DAG: addu $[[GOT:[0-9]+]], $[[T0]], $25
-; 32R2-DAG: lw $[[D2:[0-9]+]], %got(d2)($1)
-; 32R2-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
-; 32R2-DAG: lw $[[D3:[0-9]+]], %got(d3)($1)
-; 32R2-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
-; 32R2: c.olt.d $[[TMP]], $[[TMP1]]
-; 32R2: movt $5, $4, $fcc0
-; 32R2: move $2, $5
-
-; 32R6-DAG: addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp)
-; 32R6-DAG: addu $[[GOT:[0-9]+]], $[[T0]], $25
-; 32R6-DAG: lw $[[D2:[0-9]+]], %got(d2)($1)
-; 32R6-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
-; 32R6-DAG: lw $[[D3:[0-9]+]], %got(d3)($1)
-; 32R6-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
-; 32R6: cmp.lt.d $[[CC:f[0-9]+]], $[[TMP]], $[[TMP1]]
-; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
-; 32R6: andi $[[CCGPR]], $[[CCGPR]], 1
-; 32R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; 32R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
-; 32R6: or $2, $[[NE]], $[[EQ]]
-
-; 64-DAG: daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_olt_i32_val)))
-; 64-DAG: daddu $[[GOT:[0-9]+]], $[[T0]], $25
-; 64-DAG: ld $[[D2:[0-9]+]], %got_disp(d2)($1)
-; 64-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
-; 64-DAG: ld $[[D3:[0-9]+]], %got_disp(d3)($1)
-; 64-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
-; 64: c.olt.d $[[TMP]], $[[TMP1]]
-; 64: movt $5, $4, $fcc0
-; 64: move $2, $5
-
-; 64R2-DAG: daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_olt_i32_val)))
-; 64R2-DAG: daddu $[[GOT:[0-9]+]], $[[T0]], $25
-; 64R2-DAG: ld $[[D2:[0-9]+]], %got_disp(d2)($1)
-; 64R2-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
-; 64R2-DAG: ld $[[D3:[0-9]+]], %got_disp(d3)($1)
-; 64R2-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
-; 64R2: c.olt.d $[[TMP]], $[[TMP1]]
-; 64R2: movt $5, $4, $fcc0
-; 64R2: move $2, $5
-
-; 64R6-DAG: daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_olt_i32_val)))
-; 64R6-DAG: daddu $[[GOT:[0-9]+]], $[[T0]], $25
-; 64R6-DAG: ld $[[D2:[0-9]+]], %got_disp(d2)($1)
-; 64R6-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
-; 64R6-DAG: ld $[[D3:[0-9]+]], %got_disp(d3)($1)
-; 64R6-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
-; 64R6: cmp.lt.d $[[CC:f[0-9]+]], $[[TMP]], $[[TMP1]]
-; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
-; 64R6: andi $[[CCGPR]], $[[CCGPR]], 1
-; 64R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; 64R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
-; 64R6: or $2, $[[NE]], $[[EQ]]
-
%tmp = load double, double* @d2, align 8
%tmp1 = load double, double* @d3, align 8
%cmp = fcmp olt double %tmp, %tmp1
@@ -786,75 +1090,96 @@ entry:
}
define i32 @f64_fcmp_ogt_i32_val(i32 signext %f0, i32 signext %f1) nounwind readonly {
+; 32-LABEL: f64_fcmp_ogt_i32_val:
+; 32: # %bb.0: # %entry
+; 32-NEXT: lui $2, %hi(_gp_disp)
+; 32-NEXT: addiu $2, $2, %lo(_gp_disp)
+; 32-NEXT: addu $1, $2, $25
+; 32-NEXT: lw $2, %got(d3)($1)
+; 32-NEXT: ldc1 $f0, 0($2)
+; 32-NEXT: lw $1, %got(d2)($1)
+; 32-NEXT: ldc1 $f2, 0($1)
+; 32-NEXT: c.ule.d $f2, $f0
+; 32-NEXT: movf $5, $4, $fcc0
+; 32-NEXT: jr $ra
+; 32-NEXT: move $2, $5
+;
+; 32R2-LABEL: f64_fcmp_ogt_i32_val:
+; 32R2: # %bb.0: # %entry
+; 32R2-NEXT: lui $2, %hi(_gp_disp)
+; 32R2-NEXT: addiu $2, $2, %lo(_gp_disp)
+; 32R2-NEXT: addu $1, $2, $25
+; 32R2-NEXT: lw $2, %got(d3)($1)
+; 32R2-NEXT: ldc1 $f0, 0($2)
+; 32R2-NEXT: lw $1, %got(d2)($1)
+; 32R2-NEXT: ldc1 $f2, 0($1)
+; 32R2-NEXT: c.ule.d $f2, $f0
+; 32R2-NEXT: movf $5, $4, $fcc0
+; 32R2-NEXT: jr $ra
+; 32R2-NEXT: move $2, $5
+;
+; 32R6-LABEL: f64_fcmp_ogt_i32_val:
+; 32R6: # %bb.0: # %entry
+; 32R6-NEXT: lui $2, %hi(_gp_disp)
+; 32R6-NEXT: addiu $2, $2, %lo(_gp_disp)
+; 32R6-NEXT: addu $1, $2, $25
+; 32R6-NEXT: lw $2, %got(d2)($1)
+; 32R6-NEXT: ldc1 $f0, 0($2)
+; 32R6-NEXT: lw $1, %got(d3)($1)
+; 32R6-NEXT: ldc1 $f1, 0($1)
+; 32R6-NEXT: cmp.lt.d $f0, $f1, $f0
+; 32R6-NEXT: mfc1 $1, $f0
+; 32R6-NEXT: andi $1, $1, 1
+; 32R6-NEXT: seleqz $2, $5, $1
+; 32R6-NEXT: selnez $1, $4, $1
+; 32R6-NEXT: jr $ra
+; 32R6-NEXT: or $2, $1, $2
+;
+; 64-LABEL: f64_fcmp_ogt_i32_val:
+; 64: # %bb.0: # %entry
+; 64-NEXT: lui $1, %hi(%neg(%gp_rel(f64_fcmp_ogt_i32_val)))
+; 64-NEXT: daddu $1, $1, $25
+; 64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(f64_fcmp_ogt_i32_val)))
+; 64-NEXT: ld $2, %got_disp(d3)($1)
+; 64-NEXT: ldc1 $f0, 0($2)
+; 64-NEXT: ld $1, %got_disp(d2)($1)
+; 64-NEXT: ldc1 $f1, 0($1)
+; 64-NEXT: c.ule.d $f1, $f0
+; 64-NEXT: movf $5, $4, $fcc0
+; 64-NEXT: jr $ra
+; 64-NEXT: move $2, $5
+;
+; 64R2-LABEL: f64_fcmp_ogt_i32_val:
+; 64R2: # %bb.0: # %entry
+; 64R2-NEXT: lui $1, %hi(%neg(%gp_rel(f64_fcmp_ogt_i32_val)))
+; 64R2-NEXT: daddu $1, $1, $25
+; 64R2-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(f64_fcmp_ogt_i32_val)))
+; 64R2-NEXT: ld $2, %got_disp(d3)($1)
+; 64R2-NEXT: ldc1 $f0, 0($2)
+; 64R2-NEXT: ld $1, %got_disp(d2)($1)
+; 64R2-NEXT: ldc1 $f1, 0($1)
+; 64R2-NEXT: c.ule.d $f1, $f0
+; 64R2-NEXT: movf $5, $4, $fcc0
+; 64R2-NEXT: jr $ra
+; 64R2-NEXT: move $2, $5
+;
+; 64R6-LABEL: f64_fcmp_ogt_i32_val:
+; 64R6: # %bb.0: # %entry
+; 64R6-NEXT: lui $1, %hi(%neg(%gp_rel(f64_fcmp_ogt_i32_val)))
+; 64R6-NEXT: daddu $1, $1, $25
+; 64R6-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(f64_fcmp_ogt_i32_val)))
+; 64R6-NEXT: ld $2, %got_disp(d2)($1)
+; 64R6-NEXT: ldc1 $f0, 0($2)
+; 64R6-NEXT: ld $1, %got_disp(d3)($1)
+; 64R6-NEXT: ldc1 $f1, 0($1)
+; 64R6-NEXT: cmp.lt.d $f0, $f1, $f0
+; 64R6-NEXT: mfc1 $1, $f0
+; 64R6-NEXT: andi $1, $1, 1
+; 64R6-NEXT: seleqz $2, $5, $1
+; 64R6-NEXT: selnez $1, $4, $1
+; 64R6-NEXT: jr $ra
+; 64R6-NEXT: or $2, $1, $2
entry:
-; ALL-LABEL: f64_fcmp_ogt_i32_val:
-
-; 32-DAG: addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp)
-; 32-DAG: addu $[[GOT:[0-9]+]], $[[T0]], $25
-; 32-DAG: lw $[[D2:[0-9]+]], %got(d2)($1)
-; 32-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
-; 32-DAG: lw $[[D3:[0-9]+]], %got(d3)($1)
-; 32-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
-; 32: c.ule.d $[[TMP]], $[[TMP1]]
-; 32: movf $5, $4, $fcc0
-; 32: move $2, $5
-
-; 32R2-DAG: addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp)
-; 32R2-DAG: addu $[[GOT:[0-9]+]], $[[T0]], $25
-; 32R2-DAG: lw $[[D2:[0-9]+]], %got(d2)($1)
-; 32R2-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
-; 32R2-DAG: lw $[[D3:[0-9]+]], %got(d3)($1)
-; 32R2-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
-; 32R2: c.ule.d $[[TMP]], $[[TMP1]]
-; 32R2: movf $5, $4, $fcc0
-; 32R2: move $2, $5
-
-; 32R6-DAG: addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp)
-; 32R6-DAG: addu $[[GOT:[0-9]+]], $[[T0]], $25
-; 32R6-DAG: lw $[[D2:[0-9]+]], %got(d2)($1)
-; 32R6-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
-; 32R6-DAG: lw $[[D3:[0-9]+]], %got(d3)($1)
-; 32R6-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
-; 32R6: cmp.lt.d $[[CC:f[0-9]+]], $[[TMP1]], $[[TMP]]
-; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
-; 32R6: andi $[[CCGPR]], $[[CCGPR]], 1
-; 32R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; 32R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
-; 32R6: or $2, $[[NE]], $[[EQ]]
-
-; 64-DAG: daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_ogt_i32_val)))
-; 64-DAG: daddu $[[GOT:[0-9]+]], $[[T0]], $25
-; 64-DAG: ld $[[D2:[0-9]+]], %got_disp(d2)($1)
-; 64-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
-; 64-DAG: ld $[[D3:[0-9]+]], %got_disp(d3)($1)
-; 64-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
-; 64: c.ule.d $[[TMP]], $[[TMP1]]
-; 64: movf $5, $4, $fcc0
-; 64: move $2, $5
-
-; 64R2-DAG: daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_ogt_i32_val)))
-; 64R2-DAG: daddu $[[GOT:[0-9]+]], $[[T0]], $25
-; 64R2-DAG: ld $[[D2:[0-9]+]], %got_disp(d2)($1)
-; 64R2-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
-; 64R2-DAG: ld $[[D3:[0-9]+]], %got_disp(d3)($1)
-; 64R2-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
-; 64R2: c.ule.d $[[TMP]], $[[TMP1]]
-; 64R2: movf $5, $4, $fcc0
-; 64R2: move $2, $5
-
-; 64R6-DAG: daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_ogt_i32_val)))
-; 64R6-DAG: daddu $[[GOT:[0-9]+]], $[[T0]], $25
-; 64R6-DAG: ld $[[D2:[0-9]+]], %got_disp(d2)($1)
-; 64R6-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
-; 64R6-DAG: ld $[[D3:[0-9]+]], %got_disp(d3)($1)
-; 64R6-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
-; 64R6: cmp.lt.d $[[CC:f[0-9]+]], $[[TMP1]], $[[TMP]]
-; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
-; 64R6: andi $[[CCGPR]], $[[CCGPR]], 1
-; 64R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; 64R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
-; 64R6: or $2, $[[NE]], $[[EQ]]
-
%tmp = load double, double* @d2, align 8
%tmp1 = load double, double* @d3, align 8
%cmp = fcmp ogt double %tmp, %tmp1
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