diff options
Diffstat (limited to 'llvm/test/CodeGen/MIR/AMDGPU')
| -rw-r--r-- | llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir | 24 |
1 files changed, 16 insertions, 8 deletions
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir b/llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir index 67bf92b6081..36d8425e7eb 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir +++ b/llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir @@ -1,18 +1,26 @@ -# RUN: llc -o - -march=amdgcn -run-pass mir-canonicalizer -x mir %s | FileCheck %s +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -o - -march=amdgcn -run-pass mir-canonicalizer %s | FileCheck %s -# CHECK: %namedVReg4354:vgpr_32 = COPY $vgpr0 -# CHECK: %namedVReg1352:vgpr_32 = COPY %namedVReg4353 -# CHECK-NEXT: %namedVReg1358:vgpr_32 = COPY %namedVReg1361 -# CHECK-NEXT: %namedVReg1359:vgpr_32 = COPY %namedVReg1362 -# CHECK-NEXT: %namedVReg1353:vreg_64 = REG_SEQUENCE %namedVReg4354, %subreg.sub0, %namedVReg1352, %subreg.sub1 -# CHECK-NEXT: %namedVReg1354:sgpr_128 = REG_SEQUENCE %namedVReg4354, %subreg.sub0, %namedVReg1352, %subreg.sub1, %namedVReg1358, %subreg.sub2, %namedVReg1359, %subreg.sub3 # This tests for the itereator invalidation fix (reviews.llvm.org/D62713) -# CHECK-NEXT: BUFFER_STORE_DWORD_ADDR64 %namedVReg1352, %namedVReg1353, %namedVReg1354, 0, 0, 0, 0, 0, 0, 0, implicit $exec ... --- name: foo body: | bb.0: + ; CHECK-LABEL: name: foo + ; CHECK: %bb0_43693__1:sreg_32_xm0 = S_MOV_B32 61440 + ; CHECK: %bb0_13829__1:sreg_32_xm0 = S_MOV_B32 0 + ; CHECK: %bb0_14481__1:vgpr_32 = COPY $vgpr0 + ; CHECK: %bb0_18142__1:sgpr_64 = COPY $sgpr0_sgpr1 + ; CHECK: %bb0_16462__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %bb0_18142__1, 9, 0, 0 + ; CHECK: %bb0_89962__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %bb0_18142__1, 11, 0, 0 + ; CHECK: %bb0_10035__1:vgpr_32 = COPY %bb0_13829__1 + ; CHECK: %bb0_18361__1:vgpr_32 = COPY %bb0_16462__1 + ; CHECK: %bb0_18361__2:vgpr_32 = COPY %bb0_89962__1 + ; CHECK: %bb0_16181__1:vreg_64 = REG_SEQUENCE %bb0_14481__1, %subreg.sub0, %bb0_10035__1, %subreg.sub1 + ; CHECK: %bb0_71315__1:sgpr_128 = REG_SEQUENCE %bb0_14481__1, %subreg.sub0, %bb0_10035__1, %subreg.sub1, %bb0_18361__1, %subreg.sub2, %bb0_18361__2, %subreg.sub3 + ; CHECK: BUFFER_STORE_DWORD_ADDR64 %bb0_10035__1, %bb0_16181__1, %bb0_71315__1, 0, 0, 0, 0, 0, 0, 0, implicit $exec + ; CHECK: S_ENDPGM 0 %10:sreg_32_xm0 = S_MOV_B32 61440 %11:sreg_32_xm0 = S_MOV_B32 0 %3:vgpr_32 = COPY $vgpr0 |
