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-rw-r--r--llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir2
-rw-r--r--llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir2
-rw-r--r--llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir2
-rw-r--r--llvm/test/CodeGen/MIR/AMDGPU/stack-id.mir2
-rw-r--r--llvm/test/CodeGen/MIR/AMDGPU/syncscopes.mir2
-rw-r--r--llvm/test/CodeGen/MIR/AMDGPU/target-flags.mir4
-rw-r--r--llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir4
7 files changed, 9 insertions, 9 deletions
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir b/llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir
index 6d8bfcb79fb..a93af1d54d3 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir
@@ -45,5 +45,5 @@ body: |
$sgpr6 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec
BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec
- S_ENDPGM
+ S_ENDPGM 0
...
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir b/llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
index f8de6a6e1a9..31efedd3796 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
@@ -45,5 +45,5 @@ body: |
$sgpr6 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec
BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec
- S_ENDPGM
+ S_ENDPGM 0
...
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir b/llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir
index 832a61612eb..141e26abd4f 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir
@@ -23,6 +23,6 @@ body: |
%16:sgpr_128 = REG_SEQUENCE killed %vreg123_0, %subreg.sub0, %vreg123_1, %subreg.sub1, %vreg123_2, %subreg.sub2, %vreg123_3, %subreg.sub3
BUFFER_STORE_DWORD_ADDR64 %vreg123_1, %27, killed %16, 0, 0, 0, 0, 0, implicit $exec
- S_ENDPGM
+ S_ENDPGM 0
...
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/stack-id.mir b/llvm/test/CodeGen/MIR/AMDGPU/stack-id.mir
index c07c0790a1e..acceda391f1 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/stack-id.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/stack-id.mir
@@ -31,5 +31,5 @@ stack:
body: |
bb.0:
- S_ENDPGM
+ S_ENDPGM 0
...
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/syncscopes.mir b/llvm/test/CodeGen/MIR/AMDGPU/syncscopes.mir
index 4102519f961..41caf70e04a 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/syncscopes.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/syncscopes.mir
@@ -95,6 +95,6 @@ body: |
$vgpr1 = V_MOV_B32_e32 killed $sgpr5, implicit $exec, implicit killed $sgpr4_sgpr5, implicit $sgpr4_sgpr5, implicit $exec
$vgpr2 = V_MOV_B32_e32 killed $sgpr8, implicit $exec, implicit $exec
FLAT_STORE_DWORD killed $vgpr0_vgpr1, killed $vgpr2, 0, -1, 0, implicit $exec, implicit $flat_scr :: (volatile non-temporal store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out)
- S_ENDPGM
+ S_ENDPGM 0
...
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/target-flags.mir b/llvm/test/CodeGen/MIR/AMDGPU/target-flags.mir
index 569a9cf80d0..7b7eb6bc681 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/target-flags.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/target-flags.mir
@@ -24,9 +24,9 @@ body: |
; CHECK-LABEL: name: flags
; CHECK: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel32-hi) @foo + 4, implicit-def dead $scc
; CHECK: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 target-flags(amdgpu-gotprel) @foo
- ; CHECK: S_ENDPGM
+ ; CHECK: S_ENDPGM 0
%0 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel32-hi) @foo + 4, implicit-def dead $scc
%1 = S_MOV_B64 target-flags(amdgpu-gotprel) @foo
- S_ENDPGM
+ S_ENDPGM 0
...
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir b/llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir
index 713d6b69ec5..f9e5157c6d2 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir
@@ -53,7 +53,7 @@ body: |
$sgpr6 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec
BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec
- S_ENDPGM
+ S_ENDPGM 0
...
---
name: float2
@@ -83,5 +83,5 @@ body: |
$sgpr6 = S_MOV_B32 -1
$vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec
BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec
- S_ENDPGM
+ S_ENDPGM 0
...
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