diff options
Diffstat (limited to 'llvm/test/CodeGen/ARM')
| -rw-r--r-- | llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/atomic-op.ll | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/atomic-ops-v8.ll | 35 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/cmpxchg-weak.ll | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/machine-cse-cmp.ll | 2 |
5 files changed, 25 insertions, 30 deletions
diff --git a/llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll b/llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll index 2fb0d231825..9bd2077e4d0 100644 --- a/llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll +++ b/llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll @@ -49,9 +49,9 @@ tailrecurse.switch: ; preds = %tailrecurse ; V8-NEXT: beq ; V8-NEXT: %tailrecurse.switch ; V8: cmp -; V8-NEXT: beq -; V8-NEXT: %sw.epilog -; V8-NEXT: bx lr +; V8-NEXT: bne +; V8-NEXT: b +; The trailing space in the last line checks that the branch is unconditional switch i32 %and, label %sw.epilog [ i32 1, label %sw.bb i32 3, label %sw.bb6 diff --git a/llvm/test/CodeGen/ARM/atomic-op.ll b/llvm/test/CodeGen/ARM/atomic-op.ll index 23c4ccea460..e6a4949d53c 100644 --- a/llvm/test/CodeGen/ARM/atomic-op.ll +++ b/llvm/test/CodeGen/ARM/atomic-op.ll @@ -320,10 +320,10 @@ define i32 @test_cmpxchg_fail_order1(i32 *%addr, i32 %desired, i32 %new) { ; CHECK: strex [[SUCCESS:r[0-9]+]], r2, [r[[ADDR]]] ; CHECK: cmp [[SUCCESS]], #0 ; CHECK: bne [[LOOP_BB]] -; CHECK: dmb ish -; CHECK: bx lr +; CHECK: b [[END_BB:\.?LBB[0-9]+_[0-9]+]] ; CHECK: [[FAIL_BB]]: ; CHECK-NEXT: clrex +; CHECK-NEXT: [[END_BB]]: ; CHECK: dmb ish ; CHECK: bx lr diff --git a/llvm/test/CodeGen/ARM/atomic-ops-v8.ll b/llvm/test/CodeGen/ARM/atomic-ops-v8.ll index d1575ed12e4..77b850bd617 100644 --- a/llvm/test/CodeGen/ARM/atomic-ops-v8.ll +++ b/llvm/test/CodeGen/ARM/atomic-ops-v8.ll @@ -1045,21 +1045,20 @@ define i8 @test_atomic_cmpxchg_i8(i8 zeroext %wanted, i8 zeroext %new) nounwind ; function there. ; CHECK-ARM-NEXT: cmp r[[OLD]], r0 ; CHECK-THUMB-NEXT: cmp r[[OLD]], r[[WANTED]] -; CHECK-NEXT: bne .LBB{{[0-9]+}}_4 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_3 ; CHECK-NEXT: BB#2: ; As above, r1 is a reasonable guess. ; CHECK: strexb [[STATUS:r[0-9]+]], r1, [r[[ADDR]]] ; CHECK-NEXT: cmp [[STATUS]], #0 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 -; CHECK-ARM: mov r0, r[[OLD]] -; CHECK: bx lr -; CHECK-NEXT: .LBB{{[0-9]+}}_4: +; CHECK-NEXT: b .LBB{{[0-9]+}}_4 +; CHECK-NEXT: .LBB{{[0-9]+}}_3: ; CHECK-NEXT: clrex +; CHECK-NEXT: .LBB{{[0-9]+}}_4: ; CHECK-NOT: dmb ; CHECK-NOT: mcr ; CHECK-ARM: mov r0, r[[OLD]] -; CHECK-ARM-NEXT: bx lr ret i8 %old } @@ -1079,21 +1078,20 @@ define i16 @test_atomic_cmpxchg_i16(i16 zeroext %wanted, i16 zeroext %new) nounw ; function there. ; CHECK-ARM-NEXT: cmp r[[OLD]], r0 ; CHECK-THUMB-NEXT: cmp r[[OLD]], r[[WANTED]] -; CHECK-NEXT: bne .LBB{{[0-9]+}}_4 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_3 ; CHECK-NEXT: BB#2: ; As above, r1 is a reasonable guess. ; CHECK: stlexh [[STATUS:r[0-9]+]], r1, [r[[ADDR]]] ; CHECK-NEXT: cmp [[STATUS]], #0 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 -; CHECK-ARM: mov r0, r[[OLD]] -; CHECK: bx lr -; CHECK-NEXT: .LBB{{[0-9]+}}_4: +; CHECK-NEXT: b .LBB{{[0-9]+}}_4 +; CHECK-NEXT: .LBB{{[0-9]+}}_3: ; CHECK-NEXT: clrex +; CHECK-NEXT: .LBB{{[0-9]+}}_4: ; CHECK-NOT: dmb ; CHECK-NOT: mcr ; CHECK-ARM: mov r0, r[[OLD]] -; CHECK-ARM-NEXT: bx lr ret i16 %old } @@ -1112,21 +1110,20 @@ define void @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind { ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: cmp r[[OLD]], r0 -; CHECK-NEXT: bne .LBB{{[0-9]+}}_4 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_3 ; CHECK-NEXT: BB#2: ; As above, r1 is a reasonable guess. ; CHECK: stlex [[STATUS:r[0-9]+]], r1, [r[[ADDR]]] ; CHECK-NEXT: cmp [[STATUS]], #0 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 -; CHECK: str{{(.w)?}} r[[OLD]], -; CHECK-NEXT: bx lr -; CHECK-NEXT: .LBB{{[0-9]+}}_4: +; CHECK-NEXT: b .LBB{{[0-9]+}}_4 +; CHECK-NEXT: .LBB{{[0-9]+}}_3: ; CHECK-NEXT: clrex +; CHECK-NEXT: .LBB{{[0-9]+}}_4: ; CHECK-NOT: dmb ; CHECK-NOT: mcr ; CHECK: str{{(.w)?}} r[[OLD]], -; CHECK-ARM-NEXT: bx lr ret void } @@ -1151,16 +1148,16 @@ define void @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind { ; CHECK-BE-DAG: eor{{(\.w)?}} [[MISMATCH_LO:r[0-9]+|lr]], [[OLD1]], r0 ; CHECK-ARM-BE: orrs{{(\.w)?}} {{r[0-9]+}}, [[MISMATCH_HI]], [[MISMATCH_LO]] ; CHECK-THUMB-BE: orrs{{(\.w)?}} {{(r[0-9]+, )?}}[[MISMATCH_LO]], [[MISMATCH_HI]] -; CHECK-NEXT: bne .LBB{{[0-9]+}}_4 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_3 ; CHECK-NEXT: BB#2: ; As above, r2, r3 is a reasonable guess. ; CHECK: strexd [[STATUS:r[0-9]+]], r2, r3, [r[[ADDR]]] ; CHECK-NEXT: cmp [[STATUS]], #0 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 -; CHECK: strd [[OLD1]], [[OLD2]], [r[[ADDR]]] -; CHECK-NEXT: pop -; CHECK-NEXT: .LBB{{[0-9]+}}_4: +; CHECK-NEXT: b .LBB{{[0-9]+}}_4 +; CHECK-NEXT: .LBB{{[0-9]+}}_3: ; CHECK-NEXT: clrex +; CHECK-NEXT: .LBB{{[0-9]+}}_4: ; CHECK-NOT: dmb ; CHECK-NOT: mcr diff --git a/llvm/test/CodeGen/ARM/cmpxchg-weak.ll b/llvm/test/CodeGen/ARM/cmpxchg-weak.ll index 0d5681aafbc..4038528c91b 100644 --- a/llvm/test/CodeGen/ARM/cmpxchg-weak.ll +++ b/llvm/test/CodeGen/ARM/cmpxchg-weak.ll @@ -13,16 +13,14 @@ define void @test_cmpxchg_weak(i32 *%addr, i32 %desired, i32 %new) { ; CHECK-NEXT: dmb ish ; CHECK-NEXT: strex [[SUCCESS:r[0-9]+]], r2, [r0] ; CHECK-NEXT: cmp [[SUCCESS]], #0 -; CHECK-NEXT: beq [[SUCCESSBB:LBB[0-9]+_[0-9]+]] +; CHECK-NEXT: bne [[FAILBB:LBB[0-9]+_[0-9]+]] ; CHECK-NEXT: BB#2: +; CHECK-NEXT: dmb ish ; CHECK-NEXT: str r3, [r0] ; CHECK-NEXT: bx lr ; CHECK-NEXT: [[LDFAILBB]]: ; CHECK-NEXT: clrex -; CHECK-NEXT: str r3, [r0] -; CHECK-NEXT: bx lr -; CHECK-NEXT: [[SUCCESSBB]]: -; CHECK-NEXT: dmb ish +; CHECK-NEXT: [[FAILBB]]: ; CHECK-NEXT: str r3, [r0] ; CHECK-NEXT: bx lr diff --git a/llvm/test/CodeGen/ARM/machine-cse-cmp.ll b/llvm/test/CodeGen/ARM/machine-cse-cmp.ll index 259ebbd345e..611cba6ed1f 100644 --- a/llvm/test/CodeGen/ARM/machine-cse-cmp.ll +++ b/llvm/test/CodeGen/ARM/machine-cse-cmp.ll @@ -52,7 +52,7 @@ entry: ; CHECK-LABEL: f3: ; CHECK-NOT: sub ; CHECK: cmp -; CHECK: bge +; CHECK: blt %0 = load i32, i32* %offset, align 4 %cmp = icmp slt i32 %0, %size %s = sub nsw i32 %0, %size |
