summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/ARM
diff options
context:
space:
mode:
Diffstat (limited to 'llvm/test/CodeGen/ARM')
-rw-r--r--llvm/test/CodeGen/ARM/call-tc.ll10
-rw-r--r--llvm/test/CodeGen/ARM/call.ll2
-rw-r--r--llvm/test/CodeGen/ARM/emutls.ll30
-rw-r--r--llvm/test/CodeGen/ARM/pic.ll4
4 files changed, 23 insertions, 23 deletions
diff --git a/llvm/test/CodeGen/ARM/call-tc.ll b/llvm/test/CodeGen/ARM/call-tc.ll
index 3f93239dca5..53fa8920ec0 100644
--- a/llvm/test/CodeGen/ARM/call-tc.ll
+++ b/llvm/test/CodeGen/ARM/call-tc.ll
@@ -12,7 +12,7 @@ declare void @g(i32, i32, i32, i32)
define void @t1() {
; CHECKELF-LABEL: t1:
-; CHECKELF: bl g(PLT)
+; CHECKELF: bl g
call void @g( i32 1, i32 2, i32 3, i32 4 )
ret void
}
@@ -33,7 +33,7 @@ define void @t3() {
; CHECKV6-LABEL: t3:
; CHECKV6: b _t2
; CHECKELF-LABEL: t3:
-; CHECKELF: b t2(PLT)
+; CHECKELF: b t2
; CHECKT2D-LABEL: t3:
; CHECKT2D: b.w _t2
@@ -47,7 +47,7 @@ entry:
; CHECKV6-LABEL: t4:
; CHECKV6: b _sin
; CHECKELF-LABEL: t4:
-; CHECKELF: b sin(PLT)
+; CHECKELF: b sin
%0 = tail call double @sin(double %a) nounwind readonly ; <double> [#uses=1]
ret double %0
}
@@ -57,7 +57,7 @@ entry:
; CHECKV6-LABEL: t5:
; CHECKV6: b _sinf
; CHECKELF-LABEL: t5:
-; CHECKELF: b sinf(PLT)
+; CHECKELF: b sinf
%0 = tail call float @sinf(float %a) nounwind readonly ; <float> [#uses=1]
ret float %0
}
@@ -71,7 +71,7 @@ entry:
; CHECKV6-LABEL: t6:
; CHECKV6: b ___divsi3
; CHECKELF-LABEL: t6:
-; CHECKELF: b __aeabi_idiv(PLT)
+; CHECKELF: b __aeabi_idiv
%0 = sdiv i32 %a, %b
ret i32 %0
}
diff --git a/llvm/test/CodeGen/ARM/call.ll b/llvm/test/CodeGen/ARM/call.ll
index 87252a91e1b..05ea556e234 100644
--- a/llvm/test/CodeGen/ARM/call.ll
+++ b/llvm/test/CodeGen/ARM/call.ll
@@ -12,7 +12,7 @@
declare void @g(i32, i32, i32, i32)
define void @f() {
-; CHECKELF: PLT
+; CHECKELF: bl g
call void @g( i32 1, i32 2, i32 3, i32 4 )
ret void
}
diff --git a/llvm/test/CodeGen/ARM/emutls.ll b/llvm/test/CodeGen/ARM/emutls.ll
index 40f75b88756..e66d93ebcb8 100644
--- a/llvm/test/CodeGen/ARM/emutls.ll
+++ b/llvm/test/CodeGen/ARM/emutls.ll
@@ -11,7 +11,7 @@ define i32 @my_get_xyz() {
; ARM32-LABEL: my_get_xyz:
; ARM32: ldr r0,
; ARM32: ldr r0, [pc, r0]
-; ARM32-NEXT: bl my_emutls_get_address(PLT)
+; ARM32-NEXT: bl my_emutls_get_address
; ARM32-NEXT: ldr r0, [r0]
; ARM32: .long my_emutls_v_xyz(GOT_PREL)
@@ -34,7 +34,7 @@ define i32 @f1() {
; ARM32-LABEL: f1:
; ARM32: ldr r0,
; ARM32: ldr r0, [pc, r0]
-; ARM32-NEXT: bl __emutls_get_address(PLT)
+; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: ldr r0, [r0]
; ARM32: .long __emutls_v.i1(GOT_PREL)
@@ -47,7 +47,7 @@ define i32* @f2() {
; ARM32-LABEL: f2:
; ARM32: ldr r0,
; ARM32: ldr r0, [pc, r0]
-; ARM32-NEXT: bl __emutls_get_address(PLT)
+; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: pop
; ARM32: .long __emutls_v.i1(GOT_PREL)
@@ -59,7 +59,7 @@ define i32 @f3() nounwind {
; ARM32-LABEL: f3:
; ARM32: ldr r0,
; ARM32: ldr r0, [pc, r0]
-; ARM32-NEXT: bl __emutls_get_address(PLT)
+; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: ldr r0, [r0]
; ARM32: .long __emutls_v.i2(GOT_PREL)
@@ -72,7 +72,7 @@ define i32* @f4() {
; ARM32-LABEL: f4:
; ARM32: ldr r0,
; ARM32: ldr r0, [pc, r0]
-; ARM32-NEXT: bl __emutls_get_address(PLT)
+; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: pop
; ARM32: .long __emutls_v.i2(GOT_PREL)
@@ -84,7 +84,7 @@ define i32 @f5() nounwind {
; ARM32-LABEL: f5:
; ARM32: ldr r0,
; ARM32: add r0, pc, r0
-; ARM32-NEXT: bl __emutls_get_address(PLT)
+; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: ldr r0, [r0]
; ARM32: .long __emutls_v.i3-
@@ -97,7 +97,7 @@ define i32* @f6() {
; ARM32-LABEL: f6:
; ARM32: ldr r0,
; ARM32: add r0, pc, r0
-; ARM32-NEXT: bl __emutls_get_address(PLT)
+; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: pop
; ARM32: .long __emutls_v.i3-
@@ -109,7 +109,7 @@ define i32 @f7() {
; ARM32-LABEL: f7:
; ARM32: ldr r0,
; ARM32: add r0, pc, r0
-; ARM32-NEXT: bl __emutls_get_address(PLT)
+; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: ldr r0, [r0]
; ARM32: .long __emutls_v.i4-(.LPC
@@ -122,7 +122,7 @@ define i32* @f8() {
; ARM32-LABEL: f8:
; ARM32: ldr r0,
; ARM32: add r0, pc, r0
-; ARM32-NEXT: bl __emutls_get_address(PLT)
+; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: pop
; ARM32: .long __emutls_v.i4-(.LPC
@@ -134,7 +134,7 @@ define i32 @f9() {
; ARM32-LABEL: f9:
; ARM32: ldr r0,
; ARM32: add r0, pc, r0
-; ARM32-NEXT: bl __emutls_get_address(PLT)
+; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: ldr r0, [r0]
entry:
@@ -146,7 +146,7 @@ define i32* @f10() {
; ARM32-LABEL: f10:
; ARM32: ldr r0,
; ARM32: add r0, pc, r0
-; ARM32-NEXT: bl __emutls_get_address(PLT)
+; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: pop
entry:
@@ -157,7 +157,7 @@ define i16 @f11() {
; ARM32-LABEL: f11:
; ARM32: ldr r0,
; ARM32: ldr r0, [pc, r0]
-; ARM32-NEXT: bl __emutls_get_address(PLT)
+; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: ldrh r0, [r0]
entry:
@@ -169,7 +169,7 @@ define i32 @f12() {
; ARM32-LABEL: f12:
; ARM32: ldr r0,
; ARM32: ldr r0, [pc, r0]
-; ARM32-NEXT: bl __emutls_get_address(PLT)
+; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: ldrsh r0, [r0]
entry:
@@ -182,7 +182,7 @@ define i8 @f13() {
; ARM32-LABEL: f13:
; ARM32: ldr r0,
; ARM32: ldr r0, [pc, r0]
-; ARM32-NEXT: bl __emutls_get_address(PLT)
+; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: ldrb r0, [r0]
; ARM32-NEXT: pop
@@ -195,7 +195,7 @@ define i32 @f14() {
; ARM32-LABEL: f14:
; ARM32: ldr r0,
; ARM32: ldr r0, [pc, r0]
-; ARM32-NEXT: bl __emutls_get_address(PLT)
+; ARM32-NEXT: bl __emutls_get_address
; ARM32-NEXT: ldrsb r0, [r0]
; ARM32-NEXT: pop
diff --git a/llvm/test/CodeGen/ARM/pic.ll b/llvm/test/CodeGen/ARM/pic.ll
index 9fc7a63bd68..d12addb69d7 100644
--- a/llvm/test/CodeGen/ARM/pic.ll
+++ b/llvm/test/CodeGen/ARM/pic.ll
@@ -11,10 +11,10 @@ define void @test() {
entry:
%0 = call i32 @get()
-; CHECK: bl get(PLT)
+; CHECK: bl get
call void @put(i32 %0)
-; CHECK: bl put(PLT)
+; CHECK: bl put
ret void
}
OpenPOWER on IntegriCloud