diff options
Diffstat (limited to 'llvm/test/CodeGen/ARM/atomic-ops-v8.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/atomic-ops-v8.ll | 420 |
1 files changed, 229 insertions, 191 deletions
diff --git a/llvm/test/CodeGen/ARM/atomic-ops-v8.ll b/llvm/test/CodeGen/ARM/atomic-ops-v8.ll index 87e76a48c5e..1ca78bfd1e3 100644 --- a/llvm/test/CodeGen/ARM/atomic-ops-v8.ll +++ b/llvm/test/CodeGen/ARM/atomic-ops-v8.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=armv8-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=thumbv8-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=armv8-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM +; RUN: llc -mtriple=thumbv8-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-THUMB @var8 = global i8 0 @var16 = global i16 0 @@ -15,7 +15,7 @@ define i8 @test_atomic_load_add_i8(i8 %offset) nounwind { ; CHECK: movt r[[ADDR]], :upper16:var8 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]] ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: add{{s?}} [[NEW:r[0-9]+]], r[[OLD]], r0 @@ -38,7 +38,7 @@ define i16 @test_atomic_load_add_i16(i16 %offset) nounwind { ; CHECK: movt r[[ADDR]], :upper16:var16 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaexh r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK: ldaexh r[[OLD:[0-9]+]], [r[[ADDR]]] ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: add{{s?}} [[NEW:r[0-9]+]], r[[OLD]], r0 @@ -61,7 +61,7 @@ define i32 @test_atomic_load_add_i32(i32 %offset) nounwind { ; CHECK: movt r[[ADDR]], :upper16:var32 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldrex r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK: ldrex r[[OLD:[0-9]+]], [r[[ADDR]]] ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: add{{s?}} [[NEW:r[0-9]+]], r[[OLD]], r0 @@ -75,7 +75,7 @@ define i32 @test_atomic_load_add_i32(i32 %offset) nounwind { ret i32 %old } -define i64 @test_atomic_load_add_i64(i64 %offset) nounwind { +define void @test_atomic_load_add_i64(i64 %offset) nounwind { ; CHECK-LABEL: test_atomic_load_add_i64: %old = atomicrmw add i64* @var64, i64 %offset monotonic ; CHECK-NOT: dmb @@ -84,10 +84,10 @@ define i64 @test_atomic_load_add_i64(i64 %offset) nounwind { ; CHECK: movt r[[ADDR]], :upper16:var64 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldrexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]] +; CHECK: ldrexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]] ; r0, r1 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: adds [[NEW1:r[0-9]+]], r[[OLD1]], r0 +; CHECK-NEXT: adds{{(\.w)?}} [[NEW1:r[0-9]+|lr]], r[[OLD1]], r0 ; CHECK-NEXT: adc{{(\.w)?}} [[NEW2:r[0-9]+]], r[[OLD2]], r1 ; CHECK-NEXT: strexd [[STATUS:r[0-9]+]], [[NEW1]], [[NEW2]], [r[[ADDR]]] ; CHECK-NEXT: cmp [[STATUS]], #0 @@ -95,9 +95,9 @@ define i64 @test_atomic_load_add_i64(i64 %offset) nounwind { ; CHECK-NOT: dmb ; CHECK-NOT: mcr -; CHECK: mov r0, r[[OLD1]] -; CHECK-NEXT: mov r1, r[[OLD2]] - ret i64 %old +; CHECK: strd r[[OLD1]], r[[OLD2]], [r[[ADDR]]] + store i64 %old, i64* @var64 + ret void } define i8 @test_atomic_load_sub_i8(i8 %offset) nounwind { @@ -109,7 +109,7 @@ define i8 @test_atomic_load_sub_i8(i8 %offset) nounwind { ; CHECK: movt r[[ADDR]], :upper16:var8 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldrexb r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK: ldrexb r[[OLD:[0-9]+]], [r[[ADDR]]] ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: sub{{s?}} [[NEW:r[0-9]+]], r[[OLD]], r0 @@ -132,7 +132,7 @@ define i16 @test_atomic_load_sub_i16(i16 %offset) nounwind { ; CHECK: movt r[[ADDR]], :upper16:var16 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldrexh r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK: ldrexh r[[OLD:[0-9]+]], [r[[ADDR]]] ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: sub{{s?}} [[NEW:r[0-9]+]], r[[OLD]], r0 @@ -155,7 +155,7 @@ define i32 @test_atomic_load_sub_i32(i32 %offset) nounwind { ; CHECK: movt r[[ADDR]], :upper16:var32 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaex r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK: ldaex r[[OLD:[0-9]+]], [r[[ADDR]]] ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: sub{{s?}} [[NEW:r[0-9]+]], r[[OLD]], r0 @@ -169,7 +169,7 @@ define i32 @test_atomic_load_sub_i32(i32 %offset) nounwind { ret i32 %old } -define i64 @test_atomic_load_sub_i64(i64 %offset) nounwind { +define void @test_atomic_load_sub_i64(i64 %offset) nounwind { ; CHECK-LABEL: test_atomic_load_sub_i64: %old = atomicrmw sub i64* @var64, i64 %offset seq_cst ; CHECK-NOT: dmb @@ -178,10 +178,10 @@ define i64 @test_atomic_load_sub_i64(i64 %offset) nounwind { ; CHECK: movt r[[ADDR]], :upper16:var64 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]] +; CHECK: ldaexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]] ; r0, r1 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: subs [[NEW1:r[0-9]+]], r[[OLD1]], r0 +; CHECK-NEXT: subs{{(\.w)?}} [[NEW1:r[0-9]+|lr]], r[[OLD1]], r0 ; CHECK-NEXT: sbc{{(\.w)?}} [[NEW2:r[0-9]+]], r[[OLD2]], r1 ; CHECK-NEXT: stlexd [[STATUS:r[0-9]+]], [[NEW1]], [[NEW2]], [r[[ADDR]]] ; CHECK-NEXT: cmp [[STATUS]], #0 @@ -189,9 +189,9 @@ define i64 @test_atomic_load_sub_i64(i64 %offset) nounwind { ; CHECK-NOT: dmb ; CHECK-NOT: mcr -; CHECK: mov r0, r[[OLD1]] -; CHECK-NEXT: mov r1, r[[OLD2]] - ret i64 %old +; CHECK: strd r[[OLD1]], r[[OLD2]], [r[[ADDR]]] + store i64 %old, i64* @var64 + ret void } define i8 @test_atomic_load_and_i8(i8 %offset) nounwind { @@ -203,7 +203,7 @@ define i8 @test_atomic_load_and_i8(i8 %offset) nounwind { ; CHECK: movt r[[ADDR]], :upper16:var8 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldrexb r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK: ldrexb r[[OLD:[0-9]+]], [r[[ADDR]]] ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: and{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0 @@ -226,7 +226,7 @@ define i16 @test_atomic_load_and_i16(i16 %offset) nounwind { ; CHECK: movt r[[ADDR]], :upper16:var16 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldrexh r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK: ldrexh r[[OLD:[0-9]+]], [r[[ADDR]]] ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: and{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0 @@ -249,7 +249,7 @@ define i32 @test_atomic_load_and_i32(i32 %offset) nounwind { ; CHECK: movt r[[ADDR]], :upper16:var32 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaex r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK: ldaex r[[OLD:[0-9]+]], [r[[ADDR]]] ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: and{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0 @@ -263,7 +263,7 @@ define i32 @test_atomic_load_and_i32(i32 %offset) nounwind { ret i32 %old } -define i64 @test_atomic_load_and_i64(i64 %offset) nounwind { +define void @test_atomic_load_and_i64(i64 %offset) nounwind { ; CHECK-LABEL: test_atomic_load_and_i64: %old = atomicrmw and i64* @var64, i64 %offset acquire ; CHECK-NOT: dmb @@ -272,20 +272,20 @@ define i64 @test_atomic_load_and_i64(i64 %offset) nounwind { ; CHECK: movt r[[ADDR]], :upper16:var64 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]] +; CHECK: ldaexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]] ; r0, r1 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: and{{(\.w)?}} [[NEW1:r[0-9]+]], r[[OLD1]], r0 -; CHECK-NEXT: and{{(\.w)?}} [[NEW2:r[0-9]+]], r[[OLD2]], r1 -; CHECK-NEXT: strexd [[STATUS:r[0-9]+]], [[NEW1]], [[NEW2]], [r[[ADDR]]] +; CHECK-DAG: and{{(\.w)?}} [[NEW1:r[0-9]+]], r[[OLD1]], r0 +; CHECK-DAG: and{{(\.w)?}} [[NEW2:r[0-9]+|lr]], r[[OLD2]], r1 +; CHECK: strexd [[STATUS:r[0-9]+]], [[NEW1]], [[NEW2]], [r[[ADDR]]] ; CHECK-NEXT: cmp [[STATUS]], #0 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb ; CHECK-NOT: mcr -; CHECK: mov r0, r[[OLD1]] -; CHECK-NEXT: mov r1, r[[OLD2]] - ret i64 %old +; CHECK: strd r[[OLD1]], r[[OLD2]], [r[[ADDR]]] + store i64 %old, i64* @var64 + ret void } define i8 @test_atomic_load_or_i8(i8 %offset) nounwind { @@ -297,7 +297,7 @@ define i8 @test_atomic_load_or_i8(i8 %offset) nounwind { ; CHECK: movt r[[ADDR]], :upper16:var8 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]] ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: orr{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0 @@ -320,7 +320,7 @@ define i16 @test_atomic_load_or_i16(i16 %offset) nounwind { ; CHECK: movt r[[ADDR]], :upper16:var16 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldrexh r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK: ldrexh r[[OLD:[0-9]+]], [r[[ADDR]]] ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: orr{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0 @@ -343,7 +343,7 @@ define i32 @test_atomic_load_or_i32(i32 %offset) nounwind { ; CHECK: movt r[[ADDR]], :upper16:var32 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaex r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK: ldaex r[[OLD:[0-9]+]], [r[[ADDR]]] ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: orr{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0 @@ -357,7 +357,7 @@ define i32 @test_atomic_load_or_i32(i32 %offset) nounwind { ret i32 %old } -define i64 @test_atomic_load_or_i64(i64 %offset) nounwind { +define void @test_atomic_load_or_i64(i64 %offset) nounwind { ; CHECK-LABEL: test_atomic_load_or_i64: %old = atomicrmw or i64* @var64, i64 %offset release ; CHECK-NOT: dmb @@ -366,20 +366,20 @@ define i64 @test_atomic_load_or_i64(i64 %offset) nounwind { ; CHECK: movt r[[ADDR]], :upper16:var64 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldrexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]] +; CHECK: ldrexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]] ; r0, r1 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: orr{{(\.w)?}} [[NEW1:r[0-9]+]], r[[OLD1]], r0 -; CHECK-NEXT: orr{{(\.w)?}} [[NEW2:r[0-9]+]], r[[OLD2]], r1 -; CHECK-NEXT: stlexd [[STATUS:r[0-9]+]], [[NEW1]], [[NEW2]], [r[[ADDR]]] +; CHECK-DAG: orr{{(\.w)?}} [[NEW1:r[0-9]+]], r[[OLD1]], r0 +; CHECK-DAG: orr{{(\.w)?}} [[NEW2:r[0-9]+|lr]], r[[OLD2]], r1 +; CHECK: stlexd [[STATUS:r[0-9]+]], [[NEW1]], [[NEW2]], [r[[ADDR]]] ; CHECK-NEXT: cmp [[STATUS]], #0 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb ; CHECK-NOT: mcr -; CHECK: mov r0, r[[OLD1]] -; CHECK-NEXT: mov r1, r[[OLD2]] - ret i64 %old +; CHECK: strd r[[OLD1]], r[[OLD2]], [r[[ADDR]]] + store i64 %old, i64* @var64 + ret void } define i8 @test_atomic_load_xor_i8(i8 %offset) nounwind { @@ -391,7 +391,7 @@ define i8 @test_atomic_load_xor_i8(i8 %offset) nounwind { ; CHECK: movt r[[ADDR]], :upper16:var8 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]] ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: eor{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0 @@ -414,7 +414,7 @@ define i16 @test_atomic_load_xor_i16(i16 %offset) nounwind { ; CHECK: movt r[[ADDR]], :upper16:var16 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldrexh r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK: ldrexh r[[OLD:[0-9]+]], [r[[ADDR]]] ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: eor{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0 @@ -437,7 +437,7 @@ define i32 @test_atomic_load_xor_i32(i32 %offset) nounwind { ; CHECK: movt r[[ADDR]], :upper16:var32 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaex r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK: ldaex r[[OLD:[0-9]+]], [r[[ADDR]]] ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: eor{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0 @@ -451,7 +451,7 @@ define i32 @test_atomic_load_xor_i32(i32 %offset) nounwind { ret i32 %old } -define i64 @test_atomic_load_xor_i64(i64 %offset) nounwind { +define void @test_atomic_load_xor_i64(i64 %offset) nounwind { ; CHECK-LABEL: test_atomic_load_xor_i64: %old = atomicrmw xor i64* @var64, i64 %offset monotonic ; CHECK-NOT: dmb @@ -460,20 +460,20 @@ define i64 @test_atomic_load_xor_i64(i64 %offset) nounwind { ; CHECK: movt r[[ADDR]], :upper16:var64 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldrexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]] +; CHECK: ldrexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]] ; r0, r1 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: eor{{(\.w)?}} [[NEW1:r[0-9]+]], r[[OLD1]], r0 -; CHECK-NEXT: eor{{(\.w)?}} [[NEW2:r[0-9]+]], r[[OLD2]], r1 -; CHECK-NEXT: strexd [[STATUS:r[0-9]+]], [[NEW1]], [[NEW2]], [r[[ADDR]]] +; CHECK-DAG: eor{{(\.w)?}} [[NEW1:r[0-9]+]], r[[OLD1]], r0 +; CHECK-DAG: eor{{(\.w)?}} [[NEW2:r[0-9]+|lr]], r[[OLD2]], r1 +; CHECK: strexd [[STATUS:r[0-9]+]], [[NEW1]], [[NEW2]], [r[[ADDR]]] ; CHECK-NEXT: cmp [[STATUS]], #0 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb ; CHECK-NOT: mcr -; CHECK: mov r0, r[[OLD1]] -; CHECK-NEXT: mov r1, r[[OLD2]] - ret i64 %old +; CHECK: strd r[[OLD1]], r[[OLD2]], [r[[ADDR]]] + store i64 %old, i64* @var64 + ret void } define i8 @test_atomic_load_xchg_i8(i8 %offset) nounwind { @@ -485,7 +485,7 @@ define i8 @test_atomic_load_xchg_i8(i8 %offset) nounwind { ; CHECK: movt r[[ADDR]], :upper16:var8 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldrexb r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK: ldrexb r[[OLD:[0-9]+]], [r[[ADDR]]] ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: strexb [[STATUS:r[0-9]+]], r0, [r[[ADDR]]] @@ -507,7 +507,7 @@ define i16 @test_atomic_load_xchg_i16(i16 %offset) nounwind { ; CHECK: movt r[[ADDR]], :upper16:var16 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaexh r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK: ldaexh r[[OLD:[0-9]+]], [r[[ADDR]]] ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: stlexh [[STATUS:r[0-9]+]], r0, [r[[ADDR]]] @@ -529,7 +529,7 @@ define i32 @test_atomic_load_xchg_i32(i32 %offset) nounwind { ; CHECK: movt r[[ADDR]], :upper16:var32 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldrex r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK: ldrex r[[OLD:[0-9]+]], [r[[ADDR]]] ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: stlex [[STATUS:r[0-9]+]], r0, [r[[ADDR]]] @@ -542,7 +542,7 @@ define i32 @test_atomic_load_xchg_i32(i32 %offset) nounwind { ret i32 %old } -define i64 @test_atomic_load_xchg_i64(i64 %offset) nounwind { +define void @test_atomic_load_xchg_i64(i64 %offset) nounwind { ; CHECK-LABEL: test_atomic_load_xchg_i64: %old = atomicrmw xchg i64* @var64, i64 %offset acquire ; CHECK-NOT: dmb @@ -551,7 +551,7 @@ define i64 @test_atomic_load_xchg_i64(i64 %offset) nounwind { ; CHECK: movt r[[ADDR]], :upper16:var64 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]] +; CHECK: ldaexd [[OLD1:r[0-9]+]], [[OLD2:r[0-9]+|lr]], [r[[ADDR]]] ; r0, r1 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: strexd [[STATUS:r[0-9]+]], r0, r1, [r[[ADDR]]] @@ -560,28 +560,28 @@ define i64 @test_atomic_load_xchg_i64(i64 %offset) nounwind { ; CHECK-NOT: dmb ; CHECK-NOT: mcr -; CHECK: mov r0, r[[OLD1]] -; CHECK-NEXT: mov r1, r[[OLD2]] - ret i64 %old +; CHECK: strd [[OLD1]], [[OLD2]], [r[[ADDR]]] + store i64 %old, i64* @var64 + ret void } -define i8 @test_atomic_load_min_i8(i8 %offset) nounwind { +define i8 @test_atomic_load_min_i8(i8 signext %offset) nounwind { ; CHECK-LABEL: test_atomic_load_min_i8: %old = atomicrmw min i8* @var8, i8 %offset acquire ; CHECK-NOT: dmb ; CHECK-NOT: mcr -; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8 -; CHECK: movt r[[ADDR]], :upper16:var8 +; CHECK-DAG: movw [[ADDR:r[0-9]+|lr]], :lower16:var8 +; CHECK-DAG: movt [[ADDR]], :upper16:var8 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK: ldaexb r[[OLD:[0-9]+]], {{.*}}[[ADDR]] ; CHECK-NEXT: sxtb r[[OLDX:[0-9]+]], r[[OLD]] ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: cmp r[[OLDX]], r0 -; Thumb mode: it ge -; CHECK: movge r[[OLDX]], r0 -; CHECK-NEXT: strexb [[STATUS:r[0-9]+]], r[[OLDX]], [r[[ADDR]]] +; Thumb mode: it le +; CHECK: movle r[[OLDX]], r[[OLD]] +; CHECK-NEXT: strexb [[STATUS:r[0-9]+]], r[[OLDX]], {{.*}}[[ADDR]]] ; CHECK-NEXT: cmp [[STATUS]], #0 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb @@ -591,23 +591,23 @@ define i8 @test_atomic_load_min_i8(i8 %offset) nounwind { ret i8 %old } -define i16 @test_atomic_load_min_i16(i16 %offset) nounwind { +define i16 @test_atomic_load_min_i16(i16 signext %offset) nounwind { ; CHECK-LABEL: test_atomic_load_min_i16: %old = atomicrmw min i16* @var16, i16 %offset release ; CHECK-NOT: dmb ; CHECK-NOT: mcr -; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16 -; CHECK: movt r[[ADDR]], :upper16:var16 +; CHECK: movw [[ADDR:r[0-9]+|lr]], :lower16:var16 +; CHECK: movt [[ADDR]], :upper16:var16 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldrexh r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK: ldrexh r[[OLD:[0-9]+]], {{.*}}[[ADDR]] ; CHECK-NEXT: sxth r[[OLDX:[0-9]+]], r[[OLD]] ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: cmp r[[OLDX]], r0 -; Thumb mode: it ge -; CHECK: movge r[[OLDX]], r0 -; CHECK-NEXT: stlexh [[STATUS:r[0-9]+]], r[[OLDX]], [r[[ADDR]]] +; Thumb mode: it le +; CHECK: movle r[[OLDX]], r[[OLD]] +; CHECK-NEXT: stlexh [[STATUS:r[0-9]+]], r[[OLDX]], {{.*}}[[ADDR]] ; CHECK-NEXT: cmp [[STATUS]], #0 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb @@ -626,13 +626,13 @@ define i32 @test_atomic_load_min_i32(i32 %offset) nounwind { ; CHECK: movt r[[ADDR]], :upper16:var32 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldrex r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK: ldrex r[[OLD:[0-9]+]], [r[[ADDR]]] ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: mov r[[NEW:[0-9]+]], r0 ; CHECK-NEXT: cmp r[[OLD]], r0 -; Thumb mode: it lt -; CHECK: movlt r[[NEW]], r[[OLD]] +; Thumb mode: it le +; CHECK: movle r[[NEW]], r[[OLD]] ; CHECK-NEXT: strex [[STATUS:r[0-9]+]], r[[NEW]], [r[[ADDR]]] ; CHECK-NEXT: cmp [[STATUS]], #0 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 @@ -643,7 +643,7 @@ define i32 @test_atomic_load_min_i32(i32 %offset) nounwind { ret i32 %old } -define i64 @test_atomic_load_min_i64(i64 %offset) nounwind { +define void @test_atomic_load_min_i64(i64 %offset) nounwind { ; CHECK-LABEL: test_atomic_load_min_i64: %old = atomicrmw min i64* @var64, i64 %offset seq_cst ; CHECK-NOT: dmb @@ -652,41 +652,50 @@ define i64 @test_atomic_load_min_i64(i64 %offset) nounwind { ; CHECK: movt r[[ADDR]], :upper16:var64 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]] +; CHECK: ldaexd [[OLD1:r[0-9]+]], [[OLD2:r[0-9]+]], [r[[ADDR]]] ; r0, r1 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: subs [[NEW:r[0-9]+]], r[[OLD1]], r0 -; CHECK-NEXT: sbcs{{(\.w)?}} [[NEW]], r[[OLD2]], r1 -; CHECK-NEXT: blt .LBB{{[0-9]+}}_3 -; CHECK-NEXT: BB#2: -; CHECK-NEXT: stlexd [[STATUS:r[0-9]+]], r0, r1, [r[[ADDR]]] +; CHECK-ARM: mov [[LOCARRY:r[0-9]+|lr]], #0 +; CHECK-ARM: mov [[HICARRY:r[0-9]+|lr]], #0 +; CHECK-ARM: cmp [[OLD1]], r0 +; CHECK-ARM: movwls [[LOCARRY]], #1 +; CHECK-ARM: cmp [[OLD2]], r1 +; CHECK-ARM: movwle [[HICARRY]], #1 +; CHECK-ARM: moveq [[HICARRY]], [[LOCARRY]] +; CHECK-ARM: cmp [[HICARRY]], #0 +; CHECK-ARM: mov [[MINHI:r[0-9]+]], r1 +; CHECK-ARM: movne [[MINHI]], [[OLD2]] +; CHECK-ARM: mov [[MINLO:r[0-9]+]], r0 +; CHECK-ARM: movne [[MINLO]], [[OLD1]] +; CHECK-ARM: stlexd [[STATUS:r[0-9]+]], [[MINLO]], [[MINHI]], [r[[ADDR]]] +; CHECK-THUMB: stlexd [[STATUS:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]] ; CHECK-NEXT: cmp [[STATUS]], #0 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb ; CHECK-NOT: mcr -; CHECK: mov r0, r[[OLD1]] -; CHECK-NEXT: mov r1, r[[OLD2]] - ret i64 %old +; CHECK-ARM: strd [[OLD1]], [[OLD2]], [r[[ADDR]]] + store i64 %old, i64* @var64 + ret void } -define i8 @test_atomic_load_max_i8(i8 %offset) nounwind { +define i8 @test_atomic_load_max_i8(i8 signext %offset) nounwind { ; CHECK-LABEL: test_atomic_load_max_i8: %old = atomicrmw max i8* @var8, i8 %offset seq_cst ; CHECK-NOT: dmb ; CHECK-NOT: mcr -; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8 -; CHECK: movt r[[ADDR]], :upper16:var8 +; CHECK: movw [[ADDR:r[0-9]+|lr]], :lower16:var8 +; CHECK: movt [[ADDR]], :upper16:var8 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK: ldaexb r[[OLD:[0-9]+]], {{.*}}[[ADDR]] ; CHECK-NEXT: sxtb r[[OLDX:[0-9]+]], r[[OLD]] ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: cmp r[[OLDX]], r0 -; Thumb mode: it le -; CHECK: movle r[[OLDX]], r0 -; CHECK-NEXT: stlexb [[STATUS:r[0-9]+]], r[[OLDX]], [r[[ADDR]]] +; Thumb mode: it gt +; CHECK: movgt r[[OLDX]], r[[OLD]] +; CHECK-NEXT: stlexb [[STATUS:r[0-9]+]], r[[OLDX]], {{.*}}[[ADDR]] ; CHECK-NEXT: cmp [[STATUS]], #0 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb @@ -696,7 +705,7 @@ define i8 @test_atomic_load_max_i8(i8 %offset) nounwind { ret i8 %old } -define i16 @test_atomic_load_max_i16(i16 %offset) nounwind { +define i16 @test_atomic_load_max_i16(i16 signext %offset) nounwind { ; CHECK-LABEL: test_atomic_load_max_i16: %old = atomicrmw max i16* @var16, i16 %offset acquire ; CHECK-NOT: dmb @@ -705,13 +714,13 @@ define i16 @test_atomic_load_max_i16(i16 %offset) nounwind { ; CHECK: movt r[[ADDR]], :upper16:var16 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaexh r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK: ldaexh r[[OLD:[0-9]+]], [r[[ADDR]]] ; CHECK-NEXT: sxth r[[OLDX:[0-9]+]], r[[OLD]] ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: cmp r[[OLDX]], r0 -; Thumb mode: it le -; CHECK: movle r[[OLDX]], r0 +; Thumb mode: it gt +; CHECK: movgt r[[OLDX]], r[[OLD]] ; CHECK-NEXT: strexh [[STATUS:r[0-9]+]], r[[OLDX]], [r[[ADDR]]] ; CHECK-NEXT: cmp [[STATUS]], #0 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 @@ -731,7 +740,7 @@ define i32 @test_atomic_load_max_i32(i32 %offset) nounwind { ; CHECK: movt r[[ADDR]], :upper16:var32 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldrex r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK: ldrex r[[OLD:[0-9]+]], [r[[ADDR]]] ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: mov r[[NEW:[0-9]+]], r0 @@ -748,7 +757,7 @@ define i32 @test_atomic_load_max_i32(i32 %offset) nounwind { ret i32 %old } -define i64 @test_atomic_load_max_i64(i64 %offset) nounwind { +define void @test_atomic_load_max_i64(i64 %offset) nounwind { ; CHECK-LABEL: test_atomic_load_max_i64: %old = atomicrmw max i64* @var64, i64 %offset monotonic ; CHECK-NOT: dmb @@ -757,41 +766,50 @@ define i64 @test_atomic_load_max_i64(i64 %offset) nounwind { ; CHECK: movt r[[ADDR]], :upper16:var64 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldrexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]] +; CHECK: ldrexd [[OLD1:r[0-9]+]], [[OLD2:r[0-9]+]], [r[[ADDR]]] ; r0, r1 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: subs [[NEW:r[0-9]+]], r[[OLD1]], r0 -; CHECK-NEXT: sbcs{{(\.w)?}} [[NEW]], r[[OLD2]], r1 -; CHECK-NEXT: bge .LBB{{[0-9]+}}_3 -; CHECK-NEXT: BB#2: -; CHECK-NEXT: strexd [[STATUS:r[0-9]+]], r0, r1, [r[[ADDR]]] +; CHECK-ARM: mov [[LOCARRY:r[0-9]+|lr]], #0 +; CHECK-ARM: mov [[HICARRY:r[0-9]+|lr]], #0 +; CHECK-ARM: cmp [[OLD1]], r0 +; CHECK-ARM: movwhi [[LOCARRY]], #1 +; CHECK-ARM: cmp [[OLD2]], r1 +; CHECK-ARM: movwgt [[HICARRY]], #1 +; CHECK-ARM: moveq [[HICARRY]], [[LOCARRY]] +; CHECK-ARM: cmp [[HICARRY]], #0 +; CHECK-ARM: mov [[MINHI:r[0-9]+]], r1 +; CHECK-ARM: movne [[MINHI]], [[OLD2]] +; CHECK-ARM: mov [[MINLO:r[0-9]+]], r0 +; CHECK-ARM: movne [[MINLO]], [[OLD1]] +; CHECK-ARM: strexd [[STATUS:r[0-9]+]], [[MINLO]], [[MINHI]], [r[[ADDR]]] +; CHECK-THUMB: strexd [[STATUS:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]] ; CHECK-NEXT: cmp [[STATUS]], #0 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb ; CHECK-NOT: mcr -; CHECK: mov r0, r[[OLD1]] -; CHECK-NEXT: mov r1, r[[OLD2]] - ret i64 %old +; CHECK-ARM: strd [[OLD1]], [[OLD2]], [r[[ADDR]]] + store i64 %old, i64* @var64 + ret void } -define i8 @test_atomic_load_umin_i8(i8 %offset) nounwind { +define i8 @test_atomic_load_umin_i8(i8 zeroext %offset) nounwind { ; CHECK-LABEL: test_atomic_load_umin_i8: %old = atomicrmw umin i8* @var8, i8 %offset monotonic ; CHECK-NOT: dmb ; CHECK-NOT: mcr -; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8 -; CHECK: movt r[[ADDR]], :upper16:var8 +; CHECK: movw [[ADDR:r[0-9]+|lr]], :lower16:var8 +; CHECK: movt [[ADDR]], :upper16:var8 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldrexb r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK: ldrexb r[[OLD:[0-9]+]], {{.*}}[[ADDR]] ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: mov r[[NEW:[0-9]+]], r0 -; CHECK-NEXT: cmp r[[OLD]], r0 -; Thumb mode: it lo -; CHECK: movlo r[[NEW]], r[[OLD]] -; CHECK-NEXT: strexb [[STATUS:r[0-9]+]], r[[NEW]], [r[[ADDR]]] +; CHECK-NEXT: uxtb r[[OLDX]], r[[OLD]] +; CHECK-NEXT: cmp r[[OLDX]], r0 +; Thumb mode: it ls +; CHECK: movls r[[NEW]], r[[OLD]] +; CHECK-NEXT: strexb [[STATUS:r[0-9]+]], r[[NEW]], {{.*}}[[ADDR]] ; CHECK-NEXT: cmp [[STATUS]], #0 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb @@ -801,23 +819,23 @@ define i8 @test_atomic_load_umin_i8(i8 %offset) nounwind { ret i8 %old } -define i16 @test_atomic_load_umin_i16(i16 %offset) nounwind { +define i16 @test_atomic_load_umin_i16(i16 zeroext %offset) nounwind { ; CHECK-LABEL: test_atomic_load_umin_i16: %old = atomicrmw umin i16* @var16, i16 %offset acquire ; CHECK-NOT: dmb ; CHECK-NOT: mcr -; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16 -; CHECK: movt r[[ADDR]], :upper16:var16 +; CHECK: movw [[ADDR:r[0-9]+|lr]], :lower16:var16 +; CHECK: movt [[ADDR]], :upper16:var16 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaexh r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK: ldaexh r[[OLD:[0-9]+]], {{.*}}[[ADDR]] ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: mov r[[NEW:[0-9]+]], r0 -; CHECK-NEXT: cmp r[[OLD]], r0 -; Thumb mode: it lo -; CHECK: movlo r[[NEW]], r[[OLD]] -; CHECK-NEXT: strexh [[STATUS:r[0-9]+]], r[[NEW]], [r[[ADDR]]] +; CHECK-NEXT: uxth r[[OLDX]], r[[OLD]] +; CHECK-NEXT: cmp r[[OLDX]], r0 +; Thumb mode: it ls +; CHECK: movls r[[NEW]], r[[OLD]] +; CHECK-NEXT: strexh [[STATUS:r[0-9]+]], r[[NEW]], {{.*}}[[ADDR]] ; CHECK-NEXT: cmp [[STATUS]], #0 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb @@ -836,13 +854,13 @@ define i32 @test_atomic_load_umin_i32(i32 %offset) nounwind { ; CHECK: movt r[[ADDR]], :upper16:var32 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaex r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK: ldaex r[[OLD:[0-9]+]], [r[[ADDR]]] ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: mov r[[NEW:[0-9]+]], r0 ; CHECK-NEXT: cmp r[[OLD]], r0 -; Thumb mode: it lo -; CHECK: movlo r[[NEW]], r[[OLD]] +; Thumb mode: it ls +; CHECK: movls r[[NEW]], r[[OLD]] ; CHECK-NEXT: stlex [[STATUS:r[0-9]+]], r[[NEW]], [r[[ADDR]]] ; CHECK-NEXT: cmp [[STATUS]], #0 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 @@ -853,50 +871,59 @@ define i32 @test_atomic_load_umin_i32(i32 %offset) nounwind { ret i32 %old } -define i64 @test_atomic_load_umin_i64(i64 %offset) nounwind { +define void @test_atomic_load_umin_i64(i64 %offset) nounwind { ; CHECK-LABEL: test_atomic_load_umin_i64: - %old = atomicrmw umin i64* @var64, i64 %offset acq_rel + %old = atomicrmw umin i64* @var64, i64 %offset seq_cst ; CHECK-NOT: dmb ; CHECK-NOT: mcr ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64 ; CHECK: movt r[[ADDR]], :upper16:var64 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]] +; CHECK: ldaexd [[OLD1:r[0-9]+]], [[OLD2:r[0-9]+]], [r[[ADDR]]] ; r0, r1 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: subs [[NEW:r[0-9]+]], r[[OLD1]], r0 -; CHECK-NEXT: sbcs{{(\.w)?}} [[NEW]], r[[OLD2]], r1 -; CHECK-NEXT: blo .LBB{{[0-9]+}}_3 -; CHECK-NEXT: BB#2: -; CHECK-NEXT: stlexd [[STATUS:r[0-9]+]], r0, r1, [r[[ADDR]]] +; CHECK-ARM: mov [[LOCARRY:r[0-9]+|lr]], #0 +; CHECK-ARM: mov [[HICARRY:r[0-9]+|lr]], #0 +; CHECK-ARM: cmp [[OLD1]], r0 +; CHECK-ARM: movwls [[LOCARRY]], #1 +; CHECK-ARM: cmp [[OLD2]], r1 +; CHECK-ARM: movwls [[HICARRY]], #1 +; CHECK-ARM: moveq [[HICARRY]], [[LOCARRY]] +; CHECK-ARM: cmp [[HICARRY]], #0 +; CHECK-ARM: mov [[MINHI:r[0-9]+]], r1 +; CHECK-ARM: movne [[MINHI]], [[OLD2]] +; CHECK-ARM: mov [[MINLO:r[0-9]+]], r0 +; CHECK-ARM: movne [[MINLO]], [[OLD1]] +; CHECK-ARM: stlexd [[STATUS:r[0-9]+]], [[MINLO]], [[MINHI]], [r[[ADDR]]] +; CHECK-THUMB: stlexd [[STATUS:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]] ; CHECK-NEXT: cmp [[STATUS]], #0 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb ; CHECK-NOT: mcr -; CHECK: mov r0, r[[OLD1]] -; CHECK-NEXT: mov r1, r[[OLD2]] - ret i64 %old +; CHECK-ARM: strd [[OLD1]], [[OLD2]], [r[[ADDR]]] + store i64 %old, i64* @var64 + ret void } -define i8 @test_atomic_load_umax_i8(i8 %offset) nounwind { +define i8 @test_atomic_load_umax_i8(i8 zeroext %offset) nounwind { ; CHECK-LABEL: test_atomic_load_umax_i8: %old = atomicrmw umax i8* @var8, i8 %offset acq_rel ; CHECK-NOT: dmb ; CHECK-NOT: mcr -; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8 -; CHECK: movt r[[ADDR]], :upper16:var8 +; CHECK: movw [[ADDR:r[0-9]+|lr]], :lower16:var8 +; CHECK: movt [[ADDR]], :upper16:var8 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK: ldaexb r[[OLD:[0-9]+]], {{.*}}[[ADDR]] ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: mov r[[NEW:[0-9]+]], r0 -; CHECK-NEXT: cmp r[[OLD]], r0 +; CHECK-NEXT: uxtb r[[OLDX:[0-9]+]], r[[OLD]] +; CHECK-NEXT: cmp r[[OLDX]], r0 ; Thumb mode: it hi ; CHECK: movhi r[[NEW]], r[[OLD]] -; CHECK-NEXT: stlexb [[STATUS:r[0-9]+]], r[[NEW]], [r[[ADDR]]] +; CHECK-NEXT: stlexb [[STATUS:r[0-9]+]], r[[NEW]], {{.*}}[[ADDR]] ; CHECK-NEXT: cmp [[STATUS]], #0 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb @@ -906,23 +933,23 @@ define i8 @test_atomic_load_umax_i8(i8 %offset) nounwind { ret i8 %old } -define i16 @test_atomic_load_umax_i16(i16 %offset) nounwind { +define i16 @test_atomic_load_umax_i16(i16 zeroext %offset) nounwind { ; CHECK-LABEL: test_atomic_load_umax_i16: %old = atomicrmw umax i16* @var16, i16 %offset monotonic ; CHECK-NOT: dmb ; CHECK-NOT: mcr -; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16 -; CHECK: movt r[[ADDR]], :upper16:var16 +; CHECK: movw [[ADDR:r[0-9]+|lr]], :lower16:var16 +; CHECK: movt [[ADDR]], :upper16:var16 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldrexh r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK: ldrexh r[[OLD:[0-9]+]], {{.*}}[[ADDR]] ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: mov r[[NEW:[0-9]+]], r0 -; CHECK-NEXT: cmp r[[OLD]], r0 +; CHECK-NEXT: uxth r[[OLDX:[0-9]+]], r[[OLD]] +; CHECK-NEXT: cmp r[[OLDX]], r0 ; Thumb mode: it hi ; CHECK: movhi r[[NEW]], r[[OLD]] -; CHECK-NEXT: strexh [[STATUS:r[0-9]+]], r[[NEW]], [r[[ADDR]]] +; CHECK-NEXT: strexh [[STATUS:r[0-9]+]], r[[NEW]], {{.*}}[[ADDR]] ; CHECK-NEXT: cmp [[STATUS]], #0 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb @@ -941,7 +968,7 @@ define i32 @test_atomic_load_umax_i32(i32 %offset) nounwind { ; CHECK: movt r[[ADDR]], :upper16:var32 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaex r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK: ldaex r[[OLD:[0-9]+]], [r[[ADDR]]] ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: mov r[[NEW:[0-9]+]], r0 @@ -958,34 +985,43 @@ define i32 @test_atomic_load_umax_i32(i32 %offset) nounwind { ret i32 %old } -define i64 @test_atomic_load_umax_i64(i64 %offset) nounwind { +define void @test_atomic_load_umax_i64(i64 %offset) nounwind { ; CHECK-LABEL: test_atomic_load_umax_i64: - %old = atomicrmw umax i64* @var64, i64 %offset release + %old = atomicrmw umax i64* @var64, i64 %offset seq_cst ; CHECK-NOT: dmb ; CHECK-NOT: mcr ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64 ; CHECK: movt r[[ADDR]], :upper16:var64 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldrexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]] +; CHECK: ldaexd [[OLD1:r[0-9]+]], [[OLD2:r[0-9]+]], [r[[ADDR]]] ; r0, r1 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: subs [[NEW:r[0-9]+]], r[[OLD1]], r0 -; CHECK-NEXT: sbcs{{(\.w)?}} [[NEW]], r[[OLD2]], r1 -; CHECK-NEXT: bhs .LBB{{[0-9]+}}_3 -; CHECK-NEXT: BB#2: -; CHECK-NEXT: stlexd [[STATUS:r[0-9]+]], r0, r1, [r[[ADDR]]] +; CHECK-ARM: mov [[LOCARRY:r[0-9]+|lr]], #0 +; CHECK-ARM: mov [[HICARRY:r[0-9]+|lr]], #0 +; CHECK-ARM: cmp [[OLD1]], r0 +; CHECK-ARM: movwhi [[LOCARRY]], #1 +; CHECK-ARM: cmp [[OLD2]], r1 +; CHECK-ARM: movwhi [[HICARRY]], #1 +; CHECK-ARM: moveq [[HICARRY]], [[LOCARRY]] +; CHECK-ARM: cmp [[HICARRY]], #0 +; CHECK-ARM: mov [[MINHI:r[0-9]+]], r1 +; CHECK-ARM: movne [[MINHI]], [[OLD2]] +; CHECK-ARM: mov [[MINLO:r[0-9]+]], r0 +; CHECK-ARM: movne [[MINLO]], [[OLD1]] +; CHECK-ARM: stlexd [[STATUS:r[0-9]+]], [[MINLO]], [[MINHI]], [r[[ADDR]]] +; CHECK-THUMB: stlexd [[STATUS:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]] ; CHECK-NEXT: cmp [[STATUS]], #0 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb ; CHECK-NOT: mcr -; CHECK: mov r0, r[[OLD1]] -; CHECK-NEXT: mov r1, r[[OLD2]] - ret i64 %old +; CHECK-ARM: strd [[OLD1]], [[OLD2]], [r[[ADDR]]] + store i64 %old, i64* @var64 + ret void } -define i8 @test_atomic_cmpxchg_i8(i8 %wanted, i8 %new) nounwind { +define i8 @test_atomic_cmpxchg_i8(i8 zeroext %wanted, i8 zeroext %new) nounwind { ; CHECK-LABEL: test_atomic_cmpxchg_i8: %old = cmpxchg i8* @var8, i8 %wanted, i8 %new acquire acquire ; CHECK-NOT: dmb @@ -994,14 +1030,15 @@ define i8 @test_atomic_cmpxchg_i8(i8 %wanted, i8 %new) nounwind { ; CHECK: movt r[[ADDR]], :upper16:var8 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]] ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: cmp r[[OLD]], r0 +; CHECK-NEXT: uxtb r[[OLDX:[0-9]+]], r[[OLD]] +; CHECK-NEXT: cmp r[[OLDX]], r0 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_3 ; CHECK-NEXT: BB#2: ; As above, r1 is a reasonable guess. -; CHECK-NEXT: strexb [[STATUS:r[0-9]+]], r1, [r[[ADDR]]] +; CHECK: strexb [[STATUS:r[0-9]+]], r1, {{.*}}[[ADDR]] ; CHECK-NEXT: cmp [[STATUS]], #0 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb @@ -1011,7 +1048,7 @@ define i8 @test_atomic_cmpxchg_i8(i8 %wanted, i8 %new) nounwind { ret i8 %old } -define i16 @test_atomic_cmpxchg_i16(i16 %wanted, i16 %new) nounwind { +define i16 @test_atomic_cmpxchg_i16(i16 zeroext %wanted, i16 zeroext %new) nounwind { ; CHECK-LABEL: test_atomic_cmpxchg_i16: %old = cmpxchg i16* @var16, i16 %wanted, i16 %new seq_cst seq_cst ; CHECK-NOT: dmb @@ -1020,14 +1057,15 @@ define i16 @test_atomic_cmpxchg_i16(i16 %wanted, i16 %new) nounwind { ; CHECK: movt r[[ADDR]], :upper16:var16 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaexh r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK: ldaexh r[[OLD:[0-9]+]], [r[[ADDR]]] ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: cmp r[[OLD]], r0 +; CHECK-NEXT: uxth r[[OLDX:[0-9]+]], r[[OLD]] +; CHECK-NEXT: cmp r[[OLDX]], r0 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_3 ; CHECK-NEXT: BB#2: ; As above, r1 is a reasonable guess. -; CHECK-NEXT: stlexh [[STATUS:r[0-9]+]], r1, [r[[ADDR]]] +; CHECK: stlexh [[STATUS:r[0-9]+]], r1, [r[[ADDR]]] ; CHECK-NEXT: cmp [[STATUS]], #0 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb @@ -1046,14 +1084,14 @@ define i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind { ; CHECK: movt r[[ADDR]], :upper16:var32 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldrex r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK: ldrex r[[OLD:[0-9]+]], [r[[ADDR]]] ; r0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: cmp r[[OLD]], r0 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_3 ; CHECK-NEXT: BB#2: ; As above, r1 is a reasonable guess. -; CHECK-NEXT: stlex [[STATUS:r[0-9]+]], r1, [r[[ADDR]]] +; CHECK: stlex [[STATUS:r[0-9]+]], r1, [r[[ADDR]]] ; CHECK-NEXT: cmp [[STATUS]], #0 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb @@ -1063,7 +1101,7 @@ define i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind { ret i32 %old } -define i64 @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind { +define void @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind { ; CHECK-LABEL: test_atomic_cmpxchg_i64: %old = cmpxchg i64* @var64, i64 %wanted, i64 %new monotonic monotonic ; CHECK-NOT: dmb @@ -1072,24 +1110,24 @@ define i64 @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind { ; CHECK: movt r[[ADDR]], :upper16:var64 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldrexd [[OLD1:r[0-9]+|lr]], [[OLD2:r[0-9]+|lr]], [r[[ADDR]]] +; CHECK: ldrexd [[OLD1:r[0-9]+|lr]], [[OLD2:r[0-9]+|lr]], [r[[ADDR]]] ; r0, r1 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: cmp [[OLD1]], r0 -; Thumb mode: it eq -; CHECK: cmpeq [[OLD2]], r1 +; CHECK-DAG: eor{{(\.w)?}} [[MISMATCH_LO:r[0-9]+|lr]], [[OLD1]], r0 +; CHECK-DAG: eor{{(\.w)?}} [[MISMATCH_HI:r[0-9]+|lr]], [[OLD2]], r1 +; CHECK: orrs{{(\.w)?}} {{r[0-9]+}}, [[MISMATCH_LO]], [[MISMATCH_HI]] ; CHECK-NEXT: bne .LBB{{[0-9]+}}_3 ; CHECK-NEXT: BB#2: ; As above, r2, r3 is a reasonable guess. -; CHECK-NEXT: strexd [[STATUS:r[0-9]+]], r2, r3, [r[[ADDR]]] +; CHECK: strexd [[STATUS:r[0-9]+]], r2, r3, [r[[ADDR]]] ; CHECK-NEXT: cmp [[STATUS]], #0 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb ; CHECK-NOT: mcr -; CHECK: mov r0, [[OLD1]] -; CHECK-NEXT: mov r1, [[OLD2]] - ret i64 %old +; CHECK-ARM: strd [[OLD1]], [[OLD2]], [r[[ADDR]]] + store i64 %old, i64* @var64 + ret void } define i8 @test_atomic_load_monotonic_i8() nounwind { @@ -1303,13 +1341,13 @@ define void @test_atomic_store_release_i64(i64 %val) nounwind { store atomic i64 %val, i64* @var64 release, align 8 ; CHECK-NOT: dmb ; CHECK-NOT: mcr -; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64 -; CHECK: movt r[[ADDR]], :upper16:var64 +; CHECK: movw [[ADDR:r[0-9]+|lr]], :lower16:var64 +; CHECK: movt [[ADDR]], :upper16:var64 ; CHECK: .LBB{{[0-9]+}}_1: ; r0, r1 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK: stlexd [[STATUS:r[0-9]+]], r0, r1, [r[[ADDR]]] +; CHECK: stlexd [[STATUS:r[0-9]+]], r0, r1, {{.*}}[[ADDR]] ; CHECK-NEXT: cmp [[STATUS]], #0 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb @@ -1337,7 +1375,7 @@ atomic_ver: ; The key point here is that the second dmb isn't immediately followed by the ; simple_ver basic block, which LLVM attempted to do when DMB had been marked ; with isBarrier. For now, look for something that looks like "somewhere". -; CHECK-NEXT: mov +; CHECK-NEXT: {{mov|bx}} somewhere: %combined = phi i32 [ %val, %atomic_ver ], [ %newval, %simple_ver] ret i32 %combined |
