diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/branch-relaxation.ll | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/skip-if-dead.ll | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/wqm.ll | 2 |
5 files changed, 15 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/branch-relaxation.ll b/llvm/test/CodeGen/AMDGPU/branch-relaxation.ll index c298911504a..e12a0b798ee 100644 --- a/llvm/test/CodeGen/AMDGPU/branch-relaxation.ll +++ b/llvm/test/CodeGen/AMDGPU/branch-relaxation.ll @@ -171,6 +171,7 @@ bb3: ; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-NEXT: v_add_i32_e32 [[INC:v[0-9]+]], vcc, 1, [[LOOPIDX]] ; GCN-NEXT: v_cmp_gt_i32_e32 vcc, 10, [[INC]] +; GCN-NEXT: s_and_b64 vcc, exec, vcc ; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: v_nop_e64 @@ -178,7 +179,6 @@ bb3: ; GCN-NEXT: v_nop_e64 ; GCN-NEXT: ;;#ASMEND -; GCN-NEXT: s_and_b64 vcc, exec, vcc ; GCN-NEXT: s_cbranch_vccz [[ENDBB:BB[0-9]+_[0-9]+]] ; GCN-NEXT: [[LONG_JUMP:BB[0-9]+_[0-9]+]]: ; %bb2 @@ -426,6 +426,8 @@ endif: ; GCN-NEXT: s_setpc_b64 vcc ; GCN-NEXT: [[LOOP_BODY]]: ; %loop_body +; GCN: s_mov_b64 vcc, -1{{$}} +; GCN: ;;#ASMSTART ; GCN: v_nop_e64 ; GCN: v_nop_e64 ; GCN: v_nop_e64 @@ -433,7 +435,6 @@ endif: ; GCN: v_nop_e64 ; GCN: v_nop_e64 ; GCN: ;;#ASMEND -; GCN-NEXT: s_mov_b64 vcc, -1{{$}} ; GCN-NEXT: s_cbranch_vccz [[RET]] ; GCN-NEXT: [[LONGBB:BB[0-9]+_[0-9]+]]: ; %loop_body @@ -493,6 +494,7 @@ ret: ; GCN: [[LONG_BR_DEST0]] ; GCN: s_cmp_eq_u32 +; GCN-NEXT: ; implicit-def ; GCN-NEXT: s_cbranch_scc0 ; GCN: s_setpc_b64 diff --git a/llvm/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll b/llvm/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll index bea565e9fb4..9b4b61cf728 100644 --- a/llvm/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll +++ b/llvm/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll @@ -7,7 +7,7 @@ declare i1 @llvm.amdgcn.class.f32(float, i32) ; GCN-LABEL: {{^}}vcc_shrink_vcc_def: ; GCN: v_cmp_eq_u32_e64 vcc, s{{[0-9]+}}, 0{{$}} ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, vcc -; GCN: v_cndmask_b32_e64 v1, 0, 1, s{{\[[0-9]+:[0-9]+\]}} +; GCN: v_cndmask_b32_e64 v0, 0, 1, s{{\[[0-9]+:[0-9]+\]}} define void @vcc_shrink_vcc_def(float %arg, i32 %arg1, float %arg2, i32 %arg3) { bb0: %tmp = icmp sgt i32 %arg1, 4 @@ -34,7 +34,7 @@ bb2: ; GCN-LABEL: {{^}}preserve_condition_undef_flag: ; GCN-NOT: vcc ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, vcc -; GCN: v_cndmask_b32_e64 v1, 0, 1, s{{\[[0-9]+:[0-9]+\]}} +; GCN: v_cndmask_b32_e64 v0, 0, 1, s{{\[[0-9]+:[0-9]+\]}} define void @preserve_condition_undef_flag(float %arg, i32 %arg1, float %arg2) { bb0: %tmp = icmp sgt i32 %arg1, 4 diff --git a/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll b/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll index dd7c9d35820..3a933306c64 100644 --- a/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll +++ b/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll @@ -78,6 +78,8 @@ entry: ; MOVREL: v_movrels_b32_e32 v{{[0-9]}}, v0 ; IDXMODE: s_addk_i32 [[ADD_IDX:s[0-9]+]], 0xfe00{{$}} +; IDXMODE: v_mov_b32_e32 v2, 2 +; IDXMODE: v_mov_b32_e32 v3, 3 ; IDXMODE-NEXT: s_set_gpr_idx_on [[ADD_IDX]], src0{{$}} ; IDXMODE-NEXT: v_mov_b32_e32 v{{[0-9]+}}, v{{[0-9]+}} ; IDXMODE-NEXT: s_set_gpr_idx_off @@ -95,6 +97,10 @@ entry: ; MOVREL: v_movrels_b32_e32 v{{[0-9]}}, v0 ; IDXMODE: s_addk_i32 [[ADD_IDX:s[0-9]+]], 0xfe00{{$}} +; IDXMODE: v_mov_b32_e32 v0, +; IDXMODE: v_mov_b32_e32 v1, +; IDXMODE: v_mov_b32_e32 v2, +; IDXMODE: v_mov_b32_e32 v3, ; IDXMODE-NEXT: s_set_gpr_idx_on [[ADD_IDX]], src0{{$}} ; IDXMODE-NEXT: v_mov_b32_e32 v{{[0-9]+}}, v{{[0-9]+}} ; IDXMODE-NEXT: s_set_gpr_idx_off @@ -572,12 +578,12 @@ bb7: ; preds = %bb4, %bb1 ; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41a80000 ; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41b00000 ; GCN-DAG: s_load_dword [[ARG:s[0-9]+]] +; IDXMODE-DAG: s_add_i32 [[ARG_ADD:s[0-9]+]], [[ARG]], -16 ; MOVREL-DAG: s_add_i32 m0, [[ARG]], -16 ; MOVREL: v_movreld_b32_e32 v[[VEC0_ELT0]], 4.0 ; GCN-NOT: m0 -; IDXMODE-DAG: s_add_i32 [[ARG_ADD:s[0-9]+]], [[ARG]], -16 ; IDXMODE: s_set_gpr_idx_on [[ARG_ADD]], dst ; IDXMODE: v_mov_b32_e32 v[[VEC0_ELT0]], 4.0 ; IDXMODE: s_set_gpr_idx_off diff --git a/llvm/test/CodeGen/AMDGPU/skip-if-dead.ll b/llvm/test/CodeGen/AMDGPU/skip-if-dead.ll index 3ab0ee15e3d..ee344b277c0 100644 --- a/llvm/test/CodeGen/AMDGPU/skip-if-dead.ll +++ b/llvm/test/CodeGen/AMDGPU/skip-if-dead.ll @@ -138,6 +138,7 @@ exit: ; CHECK-LABEL: {{^}}test_kill_control_flow_remainder: ; CHECK: s_cmp_lg_u32 s{{[0-9]+}}, 0 +; CHECK-NEXT: v_mov_b32_e32 v{{[0-9]+}}, 0 ; CHECK-NEXT: s_cbranch_scc1 [[RETURN_BB:BB[0-9]+_[0-9]+]] ; CHECK-NEXT: ; BB#1: ; %bb diff --git a/llvm/test/CodeGen/AMDGPU/wqm.ll b/llvm/test/CodeGen/AMDGPU/wqm.ll index 4def7357efe..3f7b2b284c5 100644 --- a/llvm/test/CodeGen/AMDGPU/wqm.ll +++ b/llvm/test/CodeGen/AMDGPU/wqm.ll @@ -213,8 +213,8 @@ END: ;CHECK: image_sample ;CHECK: s_and_b64 exec, exec, [[ORIG]] ;CHECK: image_sample -;CHECK: store ;CHECK: v_cmp +;CHECK: store define amdgpu_ps float @test_control_flow_3(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, i32 %idx, i32 %coord) { main_body: %tex = call <4 x float> @llvm.SI.image.sample.i32(i32 %coord, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) |
