summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/AArch64
diff options
context:
space:
mode:
Diffstat (limited to 'llvm/test/CodeGen/AArch64')
-rw-r--r--llvm/test/CodeGen/AArch64/unfold-masked-merge-vector-variablemask-const.ll33
-rw-r--r--llvm/test/CodeGen/AArch64/unfold-masked-merge-vector-variablemask.ll70
2 files changed, 42 insertions, 61 deletions
diff --git a/llvm/test/CodeGen/AArch64/unfold-masked-merge-vector-variablemask-const.ll b/llvm/test/CodeGen/AArch64/unfold-masked-merge-vector-variablemask-const.ll
index 0646e62433b..ee150f1e5bd 100644
--- a/llvm/test/CodeGen/AArch64/unfold-masked-merge-vector-variablemask-const.ll
+++ b/llvm/test/CodeGen/AArch64/unfold-masked-merge-vector-variablemask-const.ll
@@ -77,9 +77,8 @@ define <4 x i32> @in_constant_varx_42(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mas
; CHECK-LABEL: in_constant_varx_42:
; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.4s, #42
-; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
-; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b
+; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: ret
%n0 = xor <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42> ; %x
%n1 = and <4 x i32> %n0, %mask
@@ -107,9 +106,8 @@ define <4 x i32> @in_constant_varx_42_invmask(<4 x i32> %x, <4 x i32> %y, <4 x i
; CHECK-LABEL: in_constant_varx_42_invmask:
; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.4s, #42
-; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: bic v0.16b, v0.16b, v2.16b
-; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: bsl v2.16b, v1.16b, v0.16b
+; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: ret
%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
%n0 = xor <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42> ; %x
@@ -134,8 +132,8 @@ define <4 x i32> @out_constant_mone_vary(<4 x i32> %x, <4 x i32> %y, <4 x i32> %
define <4 x i32> @in_constant_mone_vary(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) {
; CHECK-LABEL: in_constant_mone_vary:
; CHECK: // %bb.0:
-; CHECK-NEXT: bic v0.16b, v2.16b, v1.16b
-; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: bic v0.16b, v1.16b, v2.16b
+; CHECK-NEXT: orr v0.16b, v2.16b, v0.16b
; CHECK-NEXT: ret
%n0 = xor <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, %y ; %x
%n1 = and <4 x i32> %n0, %mask
@@ -161,9 +159,8 @@ define <4 x i32> @out_constant_mone_vary_invmask(<4 x i32> %x, <4 x i32> %y, <4
define <4 x i32> @in_constant_mone_vary_invmask(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) {
; CHECK-LABEL: in_constant_mone_vary_invmask:
; CHECK: // %bb.0:
-; CHECK-NEXT: mvn v0.16b, v1.16b
-; CHECK-NEXT: bic v0.16b, v0.16b, v2.16b
-; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: and v0.16b, v1.16b, v2.16b
+; CHECK-NEXT: orn v0.16b, v0.16b, v2.16b
; CHECK-NEXT: ret
%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
%n0 = xor <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, %y ; %x
@@ -189,10 +186,9 @@ define <4 x i32> @out_constant_42_vary(<4 x i32> %x, <4 x i32> %y, <4 x i32> %ma
define <4 x i32> @in_constant_42_vary(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) {
; CHECK-LABEL: in_constant_42_vary:
; CHECK: // %bb.0:
-; CHECK-NEXT: movi v0.4s, #42
-; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
-; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
-; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: mov v0.16b, v2.16b
+; CHECK-NEXT: movi v2.4s, #42
+; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b
; CHECK-NEXT: ret
%n0 = xor <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %y ; %x
%n1 = and <4 x i32> %n0, %mask
@@ -219,10 +215,9 @@ define <4 x i32> @out_constant_42_vary_invmask(<4 x i32> %x, <4 x i32> %y, <4 x
define <4 x i32> @in_constant_42_vary_invmask(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) {
; CHECK-LABEL: in_constant_42_vary_invmask:
; CHECK: // %bb.0:
-; CHECK-NEXT: movi v0.4s, #42
-; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
-; CHECK-NEXT: bic v0.16b, v0.16b, v2.16b
-; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: mov v0.16b, v2.16b
+; CHECK-NEXT: movi v2.4s, #42
+; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
; CHECK-NEXT: ret
%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
%n0 = xor <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %y ; %x
diff --git a/llvm/test/CodeGen/AArch64/unfold-masked-merge-vector-variablemask.ll b/llvm/test/CodeGen/AArch64/unfold-masked-merge-vector-variablemask.ll
index c3199cc3bee..df86540fdd9 100644
--- a/llvm/test/CodeGen/AArch64/unfold-masked-merge-vector-variablemask.ll
+++ b/llvm/test/CodeGen/AArch64/unfold-masked-merge-vector-variablemask.ll
@@ -270,9 +270,8 @@ define <2 x i64> @out_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %mask) nounwin
define <1 x i8> @in_v1i8(<1 x i8> %x, <1 x i8> %y, <1 x i8> %mask) nounwind {
; CHECK-LABEL: in_v1i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
-; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b
+; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: ret
%n0 = xor <1 x i8> %x, %y
%n1 = and <1 x i8> %n0, %mask
@@ -287,9 +286,8 @@ define <1 x i8> @in_v1i8(<1 x i8> %x, <1 x i8> %y, <1 x i8> %mask) nounwind {
define <2 x i8> @in_v2i8(<2 x i8> %x, <2 x i8> %y, <2 x i8> %mask) nounwind {
; CHECK-LABEL: in_v2i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
-; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b
+; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: ret
%n0 = xor <2 x i8> %x, %y
%n1 = and <2 x i8> %n0, %mask
@@ -300,9 +298,8 @@ define <2 x i8> @in_v2i8(<2 x i8> %x, <2 x i8> %y, <2 x i8> %mask) nounwind {
define <1 x i16> @in_v1i16(<1 x i16> %x, <1 x i16> %y, <1 x i16> %mask) nounwind {
; CHECK-LABEL: in_v1i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
-; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b
+; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: ret
%n0 = xor <1 x i16> %x, %y
%n1 = and <1 x i16> %n0, %mask
@@ -317,9 +314,8 @@ define <1 x i16> @in_v1i16(<1 x i16> %x, <1 x i16> %y, <1 x i16> %mask) nounwind
define <4 x i8> @in_v4i8(<4 x i8> %x, <4 x i8> %y, <4 x i8> %mask) nounwind {
; CHECK-LABEL: in_v4i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
-; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b
+; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: ret
%n0 = xor <4 x i8> %x, %y
%n1 = and <4 x i8> %n0, %mask
@@ -330,9 +326,8 @@ define <4 x i8> @in_v4i8(<4 x i8> %x, <4 x i8> %y, <4 x i8> %mask) nounwind {
define <2 x i16> @in_v2i16(<2 x i16> %x, <2 x i16> %y, <2 x i16> %mask) nounwind {
; CHECK-LABEL: in_v2i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
-; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b
+; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: ret
%n0 = xor <2 x i16> %x, %y
%n1 = and <2 x i16> %n0, %mask
@@ -343,9 +338,8 @@ define <2 x i16> @in_v2i16(<2 x i16> %x, <2 x i16> %y, <2 x i16> %mask) nounwind
define <1 x i32> @in_v1i32(<1 x i32> %x, <1 x i32> %y, <1 x i32> %mask) nounwind {
; CHECK-LABEL: in_v1i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
-; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b
+; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: ret
%n0 = xor <1 x i32> %x, %y
%n1 = and <1 x i32> %n0, %mask
@@ -360,9 +354,8 @@ define <1 x i32> @in_v1i32(<1 x i32> %x, <1 x i32> %y, <1 x i32> %mask) nounwind
define <8 x i8> @in_v8i8(<8 x i8> %x, <8 x i8> %y, <8 x i8> %mask) nounwind {
; CHECK-LABEL: in_v8i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
-; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b
+; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: ret
%n0 = xor <8 x i8> %x, %y
%n1 = and <8 x i8> %n0, %mask
@@ -373,9 +366,8 @@ define <8 x i8> @in_v8i8(<8 x i8> %x, <8 x i8> %y, <8 x i8> %mask) nounwind {
define <4 x i16> @in_v4i16(<4 x i16> %x, <4 x i16> %y, <4 x i16> %mask) nounwind {
; CHECK-LABEL: in_v4i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
-; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b
+; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: ret
%n0 = xor <4 x i16> %x, %y
%n1 = and <4 x i16> %n0, %mask
@@ -386,9 +378,8 @@ define <4 x i16> @in_v4i16(<4 x i16> %x, <4 x i16> %y, <4 x i16> %mask) nounwind
define <2 x i32> @in_v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %mask) nounwind {
; CHECK-LABEL: in_v2i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
-; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b
+; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: ret
%n0 = xor <2 x i32> %x, %y
%n1 = and <2 x i32> %n0, %mask
@@ -399,9 +390,8 @@ define <2 x i32> @in_v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %mask) nounwind
define <1 x i64> @in_v1i64(<1 x i64> %x, <1 x i64> %y, <1 x i64> %mask) nounwind {
; CHECK-LABEL: in_v1i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
-; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b
+; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: ret
%n0 = xor <1 x i64> %x, %y
%n1 = and <1 x i64> %n0, %mask
@@ -416,9 +406,8 @@ define <1 x i64> @in_v1i64(<1 x i64> %x, <1 x i64> %y, <1 x i64> %mask) nounwind
define <16 x i8> @in_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %mask) nounwind {
; CHECK-LABEL: in_v16i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
-; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b
+; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: ret
%n0 = xor <16 x i8> %x, %y
%n1 = and <16 x i8> %n0, %mask
@@ -429,9 +418,8 @@ define <16 x i8> @in_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %mask) nounwind
define <8 x i16> @in_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %mask) nounwind {
; CHECK-LABEL: in_v8i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
-; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b
+; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: ret
%n0 = xor <8 x i16> %x, %y
%n1 = and <8 x i16> %n0, %mask
@@ -442,9 +430,8 @@ define <8 x i16> @in_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %mask) nounwind
define <4 x i32> @in_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) nounwind {
; CHECK-LABEL: in_v4i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
-; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b
+; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: ret
%n0 = xor <4 x i32> %x, %y
%n1 = and <4 x i32> %n0, %mask
@@ -455,9 +442,8 @@ define <4 x i32> @in_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) nounwind
define <2 x i64> @in_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %mask) nounwind {
; CHECK-LABEL: in_v2i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
-; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b
+; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: ret
%n0 = xor <2 x i64> %x, %y
%n1 = and <2 x i64> %n0, %mask
OpenPOWER on IntegriCloud