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-rw-r--r--llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir634
-rw-r--r--llvm/test/CodeGen/AArch64/addsub_ext.ll53
2 files changed, 682 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir
new file mode 100644
index 00000000000..31077507614
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir
@@ -0,0 +1,634 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: add_sext_s32_to_s64
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $w1, $x2
+ ; CHECK-LABEL: name: add_sext_s32_to_s64
+ ; CHECK: liveins: $w1, $x2
+ ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK: %add_lhs:gpr64sp = COPY $x2
+ ; CHECK: %res:gpr64sp = ADDXrx %add_lhs, [[COPY]], 48
+ ; CHECK: $x3 = COPY %res
+ ; CHECK: RET_ReallyLR implicit $x3
+ %1:gpr(s32) = COPY $w1
+ %ext:gpr(s64) = G_SEXT %1(s32)
+ %add_lhs:gpr(s64) = COPY $x2
+ %res:gpr(s64) = G_ADD %add_lhs, %ext
+ $x3 = COPY %res(s64)
+ RET_ReallyLR implicit $x3
+...
+---
+name: add_and_s32_to_s64
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $x1, $x2
+ ; CHECK-LABEL: name: add_and_s32_to_s64
+ ; CHECK: liveins: $x1, $x2
+ ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY $x1
+ ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]].sub_32
+ ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]]
+ ; CHECK: %add_lhs:gpr64sp = COPY $x2
+ ; CHECK: %res:gpr64sp = ADDXrx %add_lhs, [[COPY2]], 16
+ ; CHECK: $x3 = COPY %res
+ ; CHECK: RET_ReallyLR implicit $x3
+ %1:gpr(s64) = COPY $x1
+ %mask:gpr(s64) = G_CONSTANT i64 4294967295 ; 0xffff
+ %ext:gpr(s64) = G_AND %1(s64), %mask
+ %add_lhs:gpr(s64) = COPY $x2
+ %res:gpr(s64) = G_ADD %add_lhs, %ext
+ $x3 = COPY %res(s64)
+ RET_ReallyLR implicit $x3
+...
+---
+name: add_sext_s16_to_s32
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $w1, $w2, $x2
+ ; CHECK-LABEL: name: add_sext_s16_to_s32
+ ; CHECK: liveins: $w1, $w2, $x2
+ ; CHECK: %wide_1:gpr32 = COPY $w1
+ ; CHECK: %add_lhs:gpr32sp = COPY $w2
+ ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 40
+ ; CHECK: $w3 = COPY %res
+ ; CHECK: RET_ReallyLR implicit $w3
+ %wide_1:gpr(s32) = COPY $w1
+ %1:gpr(s16) = G_TRUNC %wide_1
+ %ext:gpr(s32) = G_SEXT %1(s16)
+ %add_lhs:gpr(s32) = COPY $w2
+ %res:gpr(s32) = G_ADD %add_lhs, %ext
+ $w3 = COPY %res(s32)
+ RET_ReallyLR implicit $w3
+...
+---
+name: add_zext_s16_to_s32
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $w1, $w2, $x2
+ ; CHECK-LABEL: name: add_zext_s16_to_s32
+ ; CHECK: liveins: $w1, $w2, $x2
+ ; CHECK: %wide_1:gpr32 = COPY $w1
+ ; CHECK: %add_lhs:gpr32sp = COPY $w2
+ ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 8
+ ; CHECK: $w3 = COPY %res
+ ; CHECK: RET_ReallyLR implicit $w3
+ %wide_1:gpr(s32) = COPY $w1
+ %1:gpr(s16) = G_TRUNC %wide_1
+ %ext:gpr(s32) = G_ZEXT %1(s16)
+ %add_lhs:gpr(s32) = COPY $w2
+ %res:gpr(s32) = G_ADD %add_lhs, %ext
+ $w3 = COPY %res(s32)
+ RET_ReallyLR implicit $w3
+...
+---
+name: add_anyext_s16_to_s32
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $w1, $w2, $x2
+ ; CHECK-LABEL: name: add_anyext_s16_to_s32
+ ; CHECK: liveins: $w1, $w2, $x2
+ ; CHECK: %wide_1:gpr32 = COPY $w1
+ ; CHECK: %add_lhs:gpr32sp = COPY $w2
+ ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 8
+ ; CHECK: $w3 = COPY %res
+ ; CHECK: RET_ReallyLR implicit $w3
+ %wide_1:gpr(s32) = COPY $w1
+ %1:gpr(s16) = G_TRUNC %wide_1
+ %ext:gpr(s32) = G_ANYEXT %1(s16)
+ %add_lhs:gpr(s32) = COPY $w2
+ %res:gpr(s32) = G_ADD %add_lhs, %ext
+ $w3 = COPY %res(s32)
+ RET_ReallyLR implicit $w3
+...
+---
+name: add_and_s16_to_s32_uxtb
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $w1, $w2, $x2
+ ; CHECK-LABEL: name: add_and_s16_to_s32_uxtb
+ ; CHECK: liveins: $w1, $w2, $x2
+ ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK: %add_lhs:gpr32sp = COPY $w2
+ ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, [[COPY]], 0
+ ; CHECK: $w3 = COPY %res
+ ; CHECK: RET_ReallyLR implicit $w3
+ %1:gpr(s32) = COPY $w1
+ %mask:gpr(s32) = G_CONSTANT i32 255 ; 0xff
+ %ext:gpr(s32) = G_AND %1(s32), %mask
+ %add_lhs:gpr(s32) = COPY $w2
+ %res:gpr(s32) = G_ADD %add_lhs, %ext
+ $w3 = COPY %res(s32)
+ RET_ReallyLR implicit $w3
+...
+---
+name: add_and_s16_to_s32_uxth
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $w1, $w2, $x2
+ ; CHECK-LABEL: name: add_and_s16_to_s32_uxth
+ ; CHECK: liveins: $w1, $w2, $x2
+ ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK: %add_lhs:gpr32sp = COPY $w2
+ ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, [[COPY]], 8
+ ; CHECK: $w3 = COPY %res
+ ; CHECK: RET_ReallyLR implicit $w3
+ %1:gpr(s32) = COPY $w1
+ %mask:gpr(s32) = G_CONSTANT i32 65535 ; 0xffff
+ %ext:gpr(s32) = G_AND %1(s32), %mask
+ %add_lhs:gpr(s32) = COPY $w2
+ %res:gpr(s32) = G_ADD %add_lhs, %ext
+ $w3 = COPY %res(s32)
+ RET_ReallyLR implicit $w3
+...
+---
+name: add_sext_s8_to_s32
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $w1, $w2, $x2
+ ; CHECK-LABEL: name: add_sext_s8_to_s32
+ ; CHECK: liveins: $w1, $w2, $x2
+ ; CHECK: %wide_1:gpr32 = COPY $w1
+ ; CHECK: %add_lhs:gpr32sp = COPY $w2
+ ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 32
+ ; CHECK: $w3 = COPY %res
+ ; CHECK: RET_ReallyLR implicit $w3
+ %wide_1:gpr(s32) = COPY $w1
+ %1:gpr(s8) = G_TRUNC %wide_1
+ %ext:gpr(s32) = G_SEXT %1(s8)
+ %add_lhs:gpr(s32) = COPY $w2
+ %res:gpr(s32) = G_ADD %add_lhs, %ext
+ $w3 = COPY %res(s32)
+ RET_ReallyLR implicit $w3
+...
+---
+name: add_zext_s8_to_s32
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $w1, $w2, $x2
+ ; CHECK-LABEL: name: add_zext_s8_to_s32
+ ; CHECK: liveins: $w1, $w2, $x2
+ ; CHECK: %wide_1:gpr32 = COPY $w1
+ ; CHECK: %add_lhs:gpr32sp = COPY $w2
+ ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 0
+ ; CHECK: $w3 = COPY %res
+ ; CHECK: RET_ReallyLR implicit $w3
+ %wide_1:gpr(s32) = COPY $w1
+ %1:gpr(s8) = G_TRUNC %wide_1
+ %ext:gpr(s32) = G_ZEXT %1(s8)
+ %add_lhs:gpr(s32) = COPY $w2
+ %res:gpr(s32) = G_ADD %add_lhs, %ext
+ $w3 = COPY %res(s32)
+ RET_ReallyLR implicit $w3
+...
+---
+name: add_anyext_s8_to_s32
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $w1, $w2, $x2
+ ; CHECK-LABEL: name: add_anyext_s8_to_s32
+ ; CHECK: liveins: $w1, $w2, $x2
+ ; CHECK: %wide_1:gpr32 = COPY $w1
+ ; CHECK: %add_lhs:gpr32sp = COPY $w2
+ ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 0
+ ; CHECK: $w3 = COPY %res
+ ; CHECK: RET_ReallyLR implicit $w3
+ %wide_1:gpr(s32) = COPY $w1
+ %1:gpr(s8) = G_TRUNC %wide_1
+ %ext:gpr(s32) = G_ANYEXT %1(s8)
+ %add_lhs:gpr(s32) = COPY $w2
+ %res:gpr(s32) = G_ADD %add_lhs, %ext
+ $w3 = COPY %res(s32)
+ RET_ReallyLR implicit $w3
+...
+---
+name: add_sext_with_shl
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $w1, $w2, $x2
+ ; CHECK-LABEL: name: add_sext_with_shl
+ ; CHECK: liveins: $w1, $w2, $x2
+ ; CHECK: %wide_1:gpr32 = COPY $w1
+ ; CHECK: %add_lhs:gpr32sp = COPY $w2
+ ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 43
+ ; CHECK: $w3 = COPY %res
+ ; CHECK: RET_ReallyLR implicit $w3
+ %wide_1:gpr(s32) = COPY $w1
+ %1:gpr(s16) = G_TRUNC %wide_1
+ %ext:gpr(s32) = G_SEXT %1(s16)
+ %imm:gpr(s32) = G_CONSTANT i32 3
+ %shl:gpr(s32) = G_SHL %ext, %imm
+ %add_lhs:gpr(s32) = COPY $w2
+ %res:gpr(s32) = G_ADD %add_lhs, %shl
+ $w3 = COPY %res(s32)
+ RET_ReallyLR implicit $w3
+...
+---
+name: add_and_with_shl
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $w1, $w2, $x2
+ ; CHECK-LABEL: name: add_and_with_shl
+ ; CHECK: liveins: $w1, $w2, $x2
+ ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK: %add_lhs:gpr32sp = COPY $w2
+ ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, [[COPY]], 3
+ ; CHECK: $w3 = COPY %res
+ ; CHECK: RET_ReallyLR implicit $w3
+ %1:gpr(s32) = COPY $w1
+ %mask:gpr(s32) = G_CONSTANT i32 255 ; 0xff
+ %ext:gpr(s32) = G_AND %1(s32), %mask
+ %imm:gpr(s32) = G_CONSTANT i32 3
+ %shl:gpr(s32) = G_SHL %ext, %imm
+ %add_lhs:gpr(s32) = COPY $w2
+ %res:gpr(s32) = G_ADD %add_lhs, %shl
+ $w3 = COPY %res(s32)
+ RET_ReallyLR implicit $w3
+...
+---
+name: dont_fold_invalid_mask
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ ; Check that we only fold when we have a supported AND mask.
+ liveins: $w1, $w2, $x2
+ ; CHECK-LABEL: name: dont_fold_invalid_mask
+ ; CHECK: liveins: $w1, $w2, $x2
+ ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK: %mask:gpr32 = MOVi32imm 42
+ ; CHECK: %ext:gpr32 = ANDWrr [[COPY]], %mask
+ ; CHECK: %add_lhs:gpr32 = COPY $w2
+ ; CHECK: %res:gpr32 = ADDWrr %add_lhs, %ext
+ ; CHECK: $w3 = COPY %res
+ ; CHECK: RET_ReallyLR implicit $w3
+ %1:gpr(s32) = COPY $w1
+ %mask:gpr(s32) = G_CONSTANT i32 42
+ %ext:gpr(s32) = G_AND %1(s32), %mask
+ %add_lhs:gpr(s32) = COPY $w2
+ %res:gpr(s32) = G_ADD %add_lhs, %ext
+ $w3 = COPY %res(s32)
+ RET_ReallyLR implicit $w3
+...
+---
+name: dont_fold_invalid_shl
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $w1, $w2, $x2
+ ; CHECK-LABEL: name: dont_fold_invalid_shl
+ ; CHECK: liveins: $w1, $w2, $x2
+ ; CHECK: %wide_1:gpr32 = COPY $w1
+ ; CHECK: %ext:gpr32 = SBFMWri %wide_1, 0, 15
+ ; CHECK: %add_lhs:gpr32 = COPY $w2
+ ; CHECK: %res:gpr32 = ADDWrs %add_lhs, %ext, 5
+ ; CHECK: $w3 = COPY %res
+ ; CHECK: RET_ReallyLR implicit $w3
+ %wide_1:gpr(s32) = COPY $w1
+ %1:gpr(s16) = G_TRUNC %wide_1
+ %ext:gpr(s32) = G_SEXT %1(s16)
+ %imm:gpr(s32) = G_CONSTANT i32 5
+ %shl:gpr(s32) = G_SHL %ext, %imm
+ %add_lhs:gpr(s32) = COPY $w2
+ %res:gpr(s32) = G_ADD %add_lhs, %shl
+ $w3 = COPY %res(s32)
+ RET_ReallyLR implicit $w3
+...
+---
+name: sub_sext_s32_to_s64
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $w1, $x2
+ ; CHECK-LABEL: name: sub_sext_s32_to_s64
+ ; CHECK: liveins: $w1, $x2
+ ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK: %sub_lhs:gpr64sp = COPY $x2
+ ; CHECK: %res:gpr64 = SUBSXrx %sub_lhs, [[COPY]], 48, implicit-def $nzcv
+ ; CHECK: $x3 = COPY %res
+ ; CHECK: RET_ReallyLR implicit $x3
+ %1:gpr(s32) = COPY $w1
+ %ext:gpr(s64) = G_SEXT %1(s32)
+ %sub_lhs:gpr(s64) = COPY $x2
+ %res:gpr(s64) = G_SUB %sub_lhs, %ext
+ $x3 = COPY %res(s64)
+ RET_ReallyLR implicit $x3
+...
+---
+name: sub_sext_s16_to_s32
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $w1, $w2, $x2
+ ; CHECK-LABEL: name: sub_sext_s16_to_s32
+ ; CHECK: liveins: $w1, $w2, $x2
+ ; CHECK: %wide_1:gpr32 = COPY $w1
+ ; CHECK: %sub_lhs:gpr32sp = COPY $w2
+ ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 40, implicit-def $nzcv
+ ; CHECK: $w3 = COPY %res
+ ; CHECK: RET_ReallyLR implicit $w3
+ %wide_1:gpr(s32) = COPY $w1
+ %1:gpr(s16) = G_TRUNC %wide_1
+ %ext:gpr(s32) = G_SEXT %1(s16)
+ %sub_lhs:gpr(s32) = COPY $w2
+ %res:gpr(s32) = G_SUB %sub_lhs, %ext
+ $w3 = COPY %res(s32)
+ RET_ReallyLR implicit $w3
+...
+---
+name: sub_zext_s16_to_s32
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $w1, $w2, $x2
+ ; CHECK-LABEL: name: sub_zext_s16_to_s32
+ ; CHECK: liveins: $w1, $w2, $x2
+ ; CHECK: %wide_1:gpr32 = COPY $w1
+ ; CHECK: %sub_lhs:gpr32sp = COPY $w2
+ ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 8, implicit-def $nzcv
+ ; CHECK: $w3 = COPY %res
+ ; CHECK: RET_ReallyLR implicit $w3
+ %wide_1:gpr(s32) = COPY $w1
+ %1:gpr(s16) = G_TRUNC %wide_1
+ %ext:gpr(s32) = G_ZEXT %1(s16)
+ %sub_lhs:gpr(s32) = COPY $w2
+ %res:gpr(s32) = G_SUB %sub_lhs, %ext
+ $w3 = COPY %res(s32)
+ RET_ReallyLR implicit $w3
+...
+---
+name: sub_anyext_s16_to_s32
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $w1, $w2, $x2
+ ; CHECK-LABEL: name: sub_anyext_s16_to_s32
+ ; CHECK: liveins: $w1, $w2, $x2
+ ; CHECK: %wide_1:gpr32 = COPY $w1
+ ; CHECK: %sub_lhs:gpr32sp = COPY $w2
+ ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 8, implicit-def $nzcv
+ ; CHECK: $w3 = COPY %res
+ ; CHECK: RET_ReallyLR implicit $w3
+ %wide_1:gpr(s32) = COPY $w1
+ %1:gpr(s16) = G_TRUNC %wide_1
+ %ext:gpr(s32) = G_ANYEXT %1(s16)
+ %sub_lhs:gpr(s32) = COPY $w2
+ %res:gpr(s32) = G_SUB %sub_lhs, %ext
+ $w3 = COPY %res(s32)
+ RET_ReallyLR implicit $w3
+...
+---
+name: sub_and_s16_to_s32_uxtb
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $w1, $w2, $x2
+ ; CHECK-LABEL: name: sub_and_s16_to_s32_uxtb
+ ; CHECK: liveins: $w1, $w2, $x2
+ ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK: %sub_lhs:gpr32sp = COPY $w2
+ ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, [[COPY]], 0, implicit-def $nzcv
+ ; CHECK: $w3 = COPY %res
+ ; CHECK: RET_ReallyLR implicit $w3
+ %1:gpr(s32) = COPY $w1
+ %mask:gpr(s32) = G_CONSTANT i32 255 ; 0xff
+ %ext:gpr(s32) = G_AND %1(s32), %mask
+ %sub_lhs:gpr(s32) = COPY $w2
+ %res:gpr(s32) = G_SUB %sub_lhs, %ext
+ $w3 = COPY %res(s32)
+ RET_ReallyLR implicit $w3
+...
+---
+name: sub_and_s16_to_s32_uxth
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $w1, $w2, $x2
+ ; CHECK-LABEL: name: sub_and_s16_to_s32_uxth
+ ; CHECK: liveins: $w1, $w2, $x2
+ ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK: %sub_lhs:gpr32sp = COPY $w2
+ ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, [[COPY]], 8, implicit-def $nzcv
+ ; CHECK: $w3 = COPY %res
+ ; CHECK: RET_ReallyLR implicit $w3
+ %1:gpr(s32) = COPY $w1
+ %mask:gpr(s32) = G_CONSTANT i32 65535 ; 0xffff
+ %ext:gpr(s32) = G_AND %1(s32), %mask
+ %sub_lhs:gpr(s32) = COPY $w2
+ %res:gpr(s32) = G_SUB %sub_lhs, %ext
+ $w3 = COPY %res(s32)
+ RET_ReallyLR implicit $w3
+---
+name: sub_sext_s8_to_s32
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $w1, $w2, $x2
+ %wide_1:gpr(s32) = COPY $w1
+ %1:gpr(s8) = G_TRUNC %wide_1
+ %ext:gpr(s32) = G_SEXT %1(s8)
+ %sub_lhs:gpr(s32) = COPY $w2
+ %res:gpr(s32) = G_SUB %sub_lhs, %ext
+ $w3 = COPY %res(s32)
+ RET_ReallyLR implicit $w3
+...
+---
+name: sub_zext_s8_to_s32
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $w1, $w2, $x2
+ ; CHECK-LABEL: name: sub_zext_s8_to_s32
+ ; CHECK: liveins: $w1, $w2, $x2
+ ; CHECK: %wide_1:gpr32 = COPY $w1
+ ; CHECK: %sub_lhs:gpr32sp = COPY $w2
+ ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 0, implicit-def $nzcv
+ ; CHECK: $w3 = COPY %res
+ ; CHECK: RET_ReallyLR implicit $w3
+ %wide_1:gpr(s32) = COPY $w1
+ %1:gpr(s8) = G_TRUNC %wide_1
+ %ext:gpr(s32) = G_ZEXT %1(s8)
+ %sub_lhs:gpr(s32) = COPY $w2
+ %res:gpr(s32) = G_SUB %sub_lhs, %ext
+ $w3 = COPY %res(s32)
+ RET_ReallyLR implicit $w3
+...
+---
+name: sub_anyext_s8_to_s32
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $w1, $w2, $x2
+ ; CHECK-LABEL: name: sub_anyext_s8_to_s32
+ ; CHECK: liveins: $w1, $w2, $x2
+ ; CHECK: %wide_1:gpr32 = COPY $w1
+ ; CHECK: %sub_lhs:gpr32sp = COPY $w2
+ ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 0, implicit-def $nzcv
+ ; CHECK: $w3 = COPY %res
+ ; CHECK: RET_ReallyLR implicit $w3
+ %wide_1:gpr(s32) = COPY $w1
+ %1:gpr(s8) = G_TRUNC %wide_1
+ %ext:gpr(s32) = G_ANYEXT %1(s8)
+ %sub_lhs:gpr(s32) = COPY $w2
+ %res:gpr(s32) = G_SUB %sub_lhs, %ext
+ $w3 = COPY %res(s32)
+ RET_ReallyLR implicit $w3
+---
+...
+---
+name: sub_sext_with_shl
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $w1, $w2, $x2
+ ; CHECK-LABEL: name: sub_sext_with_shl
+ ; CHECK: liveins: $w1, $w2, $x2
+ ; CHECK: %wide_1:gpr32 = COPY $w1
+ ; CHECK: %sub_lhs:gpr32sp = COPY $w2
+ ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 43, implicit-def $nzcv
+ ; CHECK: $w3 = COPY %res
+ ; CHECK: RET_ReallyLR implicit $w3
+ %wide_1:gpr(s32) = COPY $w1
+ %1:gpr(s16) = G_TRUNC %wide_1
+ %ext:gpr(s32) = G_SEXT %1(s16)
+ %imm:gpr(s32) = G_CONSTANT i32 3
+ %shl:gpr(s32) = G_SHL %ext, %imm
+ %sub_lhs:gpr(s32) = COPY $w2
+ %res:gpr(s32) = G_SUB %sub_lhs, %shl
+ $w3 = COPY %res(s32)
+ RET_ReallyLR implicit $w3
+...
+---
+name: sub_and_with_shl
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body: |
+ bb.0:
+ liveins: $w1, $w2, $x2
+ ; CHECK-LABEL: name: sub_and_with_shl
+ ; CHECK: liveins: $w1, $w2, $x2
+ ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
+ ; CHECK: %sub_lhs:gpr32sp = COPY $w2
+ ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, [[COPY]], 3, implicit-def $nzcv
+ ; CHECK: $w3 = COPY %res
+ ; CHECK: RET_ReallyLR implicit $w3
+ %1:gpr(s32) = COPY $w1
+ %mask:gpr(s32) = G_CONSTANT i32 255 ; 0xff
+ %ext:gpr(s32) = G_AND %1(s32), %mask
+ %imm:gpr(s32) = G_CONSTANT i32 3
+ %shl:gpr(s32) = G_SHL %ext, %imm
+ %sub_lhs:gpr(s32) = COPY $w2
+ %res:gpr(s32) = G_SUB %sub_lhs, %shl
+ $w3 = COPY %res(s32)
+ RET_ReallyLR implicit $w3
diff --git a/llvm/test/CodeGen/AArch64/addsub_ext.ll b/llvm/test/CodeGen/AArch64/addsub_ext.ll
index df1b9fe7855..573ce9b6f33 100644
--- a/llvm/test/CodeGen/AArch64/addsub_ext.ll
+++ b/llvm/test/CodeGen/AArch64/addsub_ext.ll
@@ -1,4 +1,9 @@
-; RUN: llc -verify-machineinstrs %s -o - -mtriple=aarch64-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s
+; RUN: llc -enable-machine-outliner=never -verify-machineinstrs %s -o - -mtriple=aarch64-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s
+; RUN: llc -global-isel -enable-machine-outliner=never -verify-machineinstrs %s -o - -mtriple=aarch64-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s --check-prefix=GISEL
+
+; FIXME: GISel only knows how to handle explicit G_SEXT instructions. So when
+; G_SEXT is lowered to anything else, it won't fold in a stx*.
+; FIXME: GISel doesn't currently handle folding the addressing mode into a cmp.
@var8 = global i8 0
@var16 = global i16 0
@@ -7,6 +12,7 @@
define void @addsub_i8rhs() minsize {
; CHECK-LABEL: addsub_i8rhs:
+; GISEL-LABEL: addsub_i8rhs:
%val8_tmp = load i8, i8* @var8
%lhs32 = load i32, i32* @var32
%lhs64 = load i64, i64* @var64
@@ -20,23 +26,26 @@ define void @addsub_i8rhs() minsize {
%res32_zext = add i32 %lhs32, %rhs32_zext
store volatile i32 %res32_zext, i32* @var32
; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb
+; GISEL: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb
%rhs32_zext_shift = shl i32 %rhs32_zext, 3
%res32_zext_shift = add i32 %lhs32, %rhs32_zext_shift
store volatile i32 %res32_zext_shift, i32* @var32
; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb #3
-
+; GISEL: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb #3
; Zero-extending to 64-bits
%rhs64_zext = zext i8 %val8 to i64
%res64_zext = add i64 %lhs64, %rhs64_zext
store volatile i64 %res64_zext, i64* @var64
; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb
+; GISEL: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb
%rhs64_zext_shift = shl i64 %rhs64_zext, 1
%res64_zext_shift = add i64 %lhs64, %rhs64_zext_shift
store volatile i64 %res64_zext_shift, i64* @var64
; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb #1
+; GISEL: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb #1
; Sign-extending to 32-bits
%rhs32_sext = sext i8 %val8 to i32
@@ -95,23 +104,26 @@ define void @sub_i8rhs() minsize {
%res32_zext = sub i32 %lhs32, %rhs32_zext
store volatile i32 %res32_zext, i32* @var32
; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb
+; GISEL: subs {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb
%rhs32_zext_shift = shl i32 %rhs32_zext, 3
%res32_zext_shift = sub i32 %lhs32, %rhs32_zext_shift
store volatile i32 %res32_zext_shift, i32* @var32
; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb #3
-
+; GISEL: subs {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb #3
; Zero-extending to 64-bits
%rhs64_zext = zext i8 %val8 to i64
%res64_zext = sub i64 %lhs64, %rhs64_zext
store volatile i64 %res64_zext, i64* @var64
; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb
+; GISEL: subs {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb
%rhs64_zext_shift = shl i64 %rhs64_zext, 1
%res64_zext_shift = sub i64 %lhs64, %rhs64_zext_shift
store volatile i64 %res64_zext_shift, i64* @var64
; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb #1
+; GISEL: subs {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb #1
; Sign-extending to 32-bits
%rhs32_sext = sext i8 %val8 to i32
@@ -140,6 +152,7 @@ define void @sub_i8rhs() minsize {
define void @addsub_i16rhs() minsize {
; CHECK-LABEL: addsub_i16rhs:
+; GISEL-LABEL: addsub_i16rhs:
%val16_tmp = load i16, i16* @var16
%lhs32 = load i32, i32* @var32
%lhs64 = load i64, i64* @var64
@@ -153,23 +166,26 @@ define void @addsub_i16rhs() minsize {
%res32_zext = add i32 %lhs32, %rhs32_zext
store volatile i32 %res32_zext, i32* @var32
; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth
+; GISEL: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth
%rhs32_zext_shift = shl i32 %rhs32_zext, 3
%res32_zext_shift = add i32 %lhs32, %rhs32_zext_shift
store volatile i32 %res32_zext_shift, i32* @var32
; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth #3
-
+; GISEL: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth #3
; Zero-extending to 64-bits
%rhs64_zext = zext i16 %val16 to i64
%res64_zext = add i64 %lhs64, %rhs64_zext
store volatile i64 %res64_zext, i64* @var64
; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth
+; GISEL: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth
%rhs64_zext_shift = shl i64 %rhs64_zext, 1
%res64_zext_shift = add i64 %lhs64, %rhs64_zext_shift
store volatile i64 %res64_zext_shift, i64* @var64
; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth #1
+; GISEL: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth #1
; Sign-extending to 32-bits
%rhs32_sext = sext i16 %val16 to i32
@@ -215,6 +231,7 @@ end:
define void @sub_i16rhs() minsize {
; CHECK-LABEL: sub_i16rhs:
+; GISEL-LABEL: sub_i16rhs:
%val16_tmp = load i16, i16* @var16
%lhs32 = load i32, i32* @var32
%lhs64 = load i64, i64* @var64
@@ -228,23 +245,26 @@ define void @sub_i16rhs() minsize {
%res32_zext = sub i32 %lhs32, %rhs32_zext
store volatile i32 %res32_zext, i32* @var32
; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth
+; GISEL: subs {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth
%rhs32_zext_shift = shl i32 %rhs32_zext, 3
%res32_zext_shift = sub i32 %lhs32, %rhs32_zext_shift
store volatile i32 %res32_zext_shift, i32* @var32
; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth #3
-
+; GISEL: subs {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth #3
; Zero-extending to 64-bits
%rhs64_zext = zext i16 %val16 to i64
%res64_zext = sub i64 %lhs64, %rhs64_zext
store volatile i64 %res64_zext, i64* @var64
; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth
+; GISEL: subs {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth
%rhs64_zext_shift = shl i64 %rhs64_zext, 1
%res64_zext_shift = sub i64 %lhs64, %rhs64_zext_shift
store volatile i64 %res64_zext_shift, i64* @var64
; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth #1
+; GISEL: subs {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth #1
; Sign-extending to 32-bits
%rhs32_sext = sext i16 %val16 to i32
@@ -276,6 +296,7 @@ define void @sub_i16rhs() minsize {
; in the face of "add/sub (shifted register)" so I don't intend to.
define void @addsub_i32rhs(i32 %in32) minsize {
; CHECK-LABEL: addsub_i32rhs:
+; GISEL-LABEL: addsub_i32rhs:
%val32_tmp = load i32, i32* @var32
%lhs64 = load i64, i64* @var64
@@ -285,22 +306,26 @@ define void @addsub_i32rhs(i32 %in32) minsize {
%res64_zext = add i64 %lhs64, %rhs64_zext
store volatile i64 %res64_zext, i64* @var64
; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw
+; GISEL: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw
%rhs64_zext2 = zext i32 %val32 to i64
%rhs64_zext_shift = shl i64 %rhs64_zext2, 2
%res64_zext_shift = add i64 %lhs64, %rhs64_zext_shift
store volatile i64 %res64_zext_shift, i64* @var64
; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw #2
+; GISEL: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw #2
%rhs64_sext = sext i32 %val32 to i64
%res64_sext = add i64 %lhs64, %rhs64_sext
store volatile i64 %res64_sext, i64* @var64
; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw
+; GISEL: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw
%rhs64_sext_shift = shl i64 %rhs64_sext, 2
%res64_sext_shift = add i64 %lhs64, %rhs64_sext_shift
store volatile i64 %res64_sext_shift, i64* @var64
; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw #2
+; GISEL: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw #2
ret void
}
@@ -316,12 +341,14 @@ define void @sub_i32rhs(i32 %in32) minsize {
%res64_zext = sub i64 %lhs64, %rhs64_zext
store volatile i64 %res64_zext, i64* @var64
; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw
+; GISEL: subs {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw
%rhs64_zext2 = zext i32 %val32 to i64
%rhs64_zext_shift = shl i64 %rhs64_zext2, 2
%res64_zext_shift = sub i64 %lhs64, %rhs64_zext_shift
store volatile i64 %res64_zext_shift, i64* @var64
; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw #2
+; GISEL: subs {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw #2
%rhs64_sext = sext i32 %val32 to i64
%res64_sext = sub i64 %lhs64, %rhs64_sext
@@ -339,11 +366,15 @@ define void @sub_i32rhs(i32 %in32) minsize {
; Check that implicit zext from w reg write is used instead of uxtw form of add.
define i64 @add_fold_uxtw(i32 %x, i64 %y) {
; CHECK-LABEL: add_fold_uxtw:
+; GISEL-LABEL: add_fold_uxtw:
entry:
; CHECK: and w[[TMP:[0-9]+]], w0, #0x3
+; GISEL: and w[[TMP:[0-9]+]], w0, #0x3
+; FIXME: Global ISel produces an unncessary ubfx here.
%m = and i32 %x, 3
%ext = zext i32 %m to i64
; CHECK-NEXT: add x0, x1, x[[TMP]]
+; GISEL: add x0, x1, x[[TMP]]
%ret = add i64 %y, %ext
ret i64 %ret
}
@@ -352,11 +383,14 @@ entry:
; form of sub and that mov WZR is folded to form a neg instruction.
define i64 @sub_fold_uxtw_xzr(i32 %x) {
; CHECK-LABEL: sub_fold_uxtw_xzr:
+; GISEL-LABEL: sub_fold_uxtw_xzr:
entry:
; CHECK: and w[[TMP:[0-9]+]], w0, #0x3
+; GISEL: and w[[TMP:[0-9]+]], w0, #0x3
%m = and i32 %x, 3
%ext = zext i32 %m to i64
; CHECK-NEXT: neg x0, x[[TMP]]
+; GISEL: negs x0, x[[TMP]]
%ret = sub i64 0, %ext
ret i64 %ret
}
@@ -378,10 +412,13 @@ entry:
; form of add, leading to madd selection.
define i64 @madd_fold_uxtw(i32 %x, i64 %y) {
; CHECK-LABEL: madd_fold_uxtw:
+; GISEL-LABEL: madd_fold_uxtw:
entry:
; CHECK: and w[[TMP:[0-9]+]], w0, #0x3
+; GISEL: and w[[TMP:[0-9]+]], w0, #0x3
%m = and i32 %x, 3
%ext = zext i32 %m to i64
+; GISEL: madd x0, x1, x1, x[[TMP]]
; CHECK-NEXT: madd x0, x1, x1, x[[TMP]]
%mul = mul i64 %y, %y
%ret = add i64 %mul, %ext
@@ -408,11 +445,14 @@ entry:
; form of add and add of -1 gets selected as sub.
define i64 @add_imm_fold_uxtw(i32 %x) {
; CHECK-LABEL: add_imm_fold_uxtw:
+; GISEL-LABEL: add_imm_fold_uxtw:
entry:
; CHECK: and w[[TMP:[0-9]+]], w0, #0x3
+; GISEL: and w[[TMP:[0-9]+]], w0, #0x3
%m = and i32 %x, 3
%ext = zext i32 %m to i64
; CHECK-NEXT: sub x0, x[[TMP]], #1
+; GISEL: subs x0, x[[TMP]], #1
%ret = add i64 %ext, -1
ret i64 %ret
}
@@ -421,12 +461,15 @@ entry:
; form of add and add lsl form gets selected.
define i64 @add_lsl_fold_uxtw(i32 %x, i64 %y) {
; CHECK-LABEL: add_lsl_fold_uxtw:
+; GISEL-LABEL: add_lsl_fold_uxtw:
entry:
; CHECK: orr w[[TMP:[0-9]+]], w0, #0x3
+; GISEL: orr w[[TMP:[0-9]+]], w0, #0x3
%m = or i32 %x, 3
%ext = zext i32 %m to i64
%shift = shl i64 %y, 3
; CHECK-NEXT: add x0, x[[TMP]], x1, lsl #3
+; GISEL: add x0, x[[TMP]], x1, lsl #3
%ret = add i64 %ext, %shift
ret i64 %ret
}
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