1 files changed, 19 insertions, 19 deletions
diff --git a/llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll b/llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
index 2f70f3635d1..1b25841650a 100644
--- a/llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
@@ -181,7 +181,7 @@ define <8 x half> @s_to_h(<8 x float> %a) {
 ; CHECK-LABEL: s_to_h:
 ; CHECK-DAG: fcvtn v0.4h, v0.4s
 ; CHECK-DAG: fcvtn [[REG:v[0-9+]]].4h, v1.4s
-; CHECK: ins v0.d[1], [[REG]].d[0]
+; CHECK: mov v0.d[1], [[REG]].d[0]
   %1 = fptrunc <8 x float> %a to <8 x half>
   ret <8 x half> %1
 }
@@ -200,14 +200,14 @@ define <8 x half> @d_to_h(<8 x double> %a) {
 ; CHECK-DAG: fcvt h
 ; CHECK-DAG: fcvt h
 ; CHECK-DAG: fcvt h
-; CHECK-DAG: ins v{{[0-9]+}}.h
-; CHECK-DAG: ins v{{[0-9]+}}.h
-; CHECK-DAG: ins v{{[0-9]+}}.h
-; CHECK-DAG: ins v{{[0-9]+}}.h
-; CHECK-DAG: ins v{{[0-9]+}}.h
-; CHECK-DAG: ins v{{[0-9]+}}.h
-; CHECK-DAG: ins v{{[0-9]+}}.h
-; CHECK-DAG: ins v{{[0-9]+}}.h
+; CHECK-DAG: mov v{{[0-9]+}}.h
+; CHECK-DAG: mov v{{[0-9]+}}.h
+; CHECK-DAG: mov v{{[0-9]+}}.h
+; CHECK-DAG: mov v{{[0-9]+}}.h
+; CHECK-DAG: mov v{{[0-9]+}}.h
+; CHECK-DAG: mov v{{[0-9]+}}.h
+; CHECK-DAG: mov v{{[0-9]+}}.h
+; CHECK-DAG: mov v{{[0-9]+}}.h
   %1 = fptrunc <8 x double> %a to <8 x half>
   ret <8 x half> %1
 }
@@ -230,10 +230,10 @@ define <8 x double> @h_to_d(<8 x half> %a) {
 ; CHECK-DAG: fcvt d
 ; CHECK-DAG: fcvt d
 ; CHECK-DAG: fcvt d
-; CHECK-DAG: ins
-; CHECK-DAG: ins
-; CHECK-DAG: ins
-; CHECK-DAG: ins
+; CHECK-DAG: mov
+; CHECK-DAG: mov
+; CHECK-DAG: mov
+; CHECK-DAG: mov
   %1 = fpext <8 x half> %a to <8 x double>
   ret <8 x double> %1
 }
@@ -263,7 +263,7 @@ define <8 x half> @sitofp_i8(<8 x i8> %a) #0 {
 ; CHECK-DAG: scvtf [[LOF:v[0-9]+\.4s]], [[LO]]
 ; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
 ; CHECK-DAG: fcvtn v0.4h, [[HIF]]
-; CHECK: ins v0.d[1], v[[LOREG]].d[0]
+; CHECK: mov v0.d[1], v[[LOREG]].d[0]
   %1 = sitofp <8 x i8> %a to <8 x half>
   ret <8 x half> %1
 }
@@ -277,7 +277,7 @@ define <8 x half> @sitofp_i16(<8 x i16> %a) #0 {
 ; CHECK-DAG: scvtf [[LOF:v[0-9]+\.4s]], [[LO]]
 ; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
 ; CHECK-DAG: fcvtn v0.4h, [[HIF]]
-; CHECK: ins v0.d[1], v[[LOREG]].d[0]
+; CHECK: mov v0.d[1], v[[LOREG]].d[0]
   %1 = sitofp <8 x i16> %a to <8 x half>
   ret <8 x half> %1
 }
@@ -289,7 +289,7 @@ define <8 x half> @sitofp_i32(<8 x i32> %a) #0 {
 ; CHECK-DAG: scvtf [[OP2:v[0-9]+\.4s]], v1.4s
 ; CHECK-DAG: fcvtn v[[REG:[0-9]+]].4h, [[OP2]]
 ; CHECK-DAG: fcvtn v0.4h, [[OP1]]
-; CHECK: ins v0.d[1], v[[REG]].d[0]
+; CHECK: mov v0.d[1], v[[REG]].d[0]
   %1 = sitofp <8 x i32> %a to <8 x half>
   ret <8 x half> %1
 }
@@ -315,7 +315,7 @@ define <8 x half> @uitofp_i8(<8 x i8> %a) #0 {
 ; CHECK-DAG: ucvtf [[LOF:v[0-9]+\.4s]], [[LO]]
 ; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
 ; CHECK-DAG: fcvtn v0.4h, [[HIF]]
-; CHECK: ins v0.d[1], v[[LOREG]].d[0]
+; CHECK: mov v0.d[1], v[[LOREG]].d[0]
   %1 = uitofp <8 x i8> %a to <8 x half>
   ret <8 x half> %1
 }
@@ -329,7 +329,7 @@ define <8 x half> @uitofp_i16(<8 x i16> %a) #0 {
 ; CHECK-DAG: ucvtf [[LOF:v[0-9]+\.4s]], [[LO]]
 ; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
 ; CHECK-DAG: fcvtn v0.4h, [[HIF]]
-; CHECK: ins v0.d[1], v[[LOREG]].d[0]
+; CHECK: mov v0.d[1], v[[LOREG]].d[0]
   %1 = uitofp <8 x i16> %a to <8 x half>
   ret <8 x half> %1
 }
@@ -341,7 +341,7 @@ define <8 x half> @uitofp_i32(<8 x i32> %a) #0 {
 ; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.4s]], v1.4s
 ; CHECK-DAG: fcvtn v[[REG:[0-9]+]].4h, [[OP2]]
 ; CHECK-DAG: fcvtn v0.4h, [[OP1]]
-; CHECK: ins v0.d[1], v[[REG]].d[0]
+; CHECK: mov v0.d[1], v[[REG]].d[0]
   %1 = uitofp <8 x i32> %a to <8 x half>
   ret <8 x half> %1
 }