diff options
Diffstat (limited to 'llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll b/llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll index b63e739f577..8b6a4cae7ed 100644 --- a/llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll +++ b/llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll @@ -413,7 +413,7 @@ define i8* @test_v16i8_post_imm_st1_lane(<16 x i8> %in, i8* %addr) { define i8* @test_v16i8_post_reg_st1_lane(<16 x i8> %in, i8* %addr) { ; CHECK-LABEL: test_v16i8_post_reg_st1_lane: -; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x2 +; CHECK: mov w[[OFFSET:[0-9]+]], #2 ; CHECK: st1.b { v0 }[3], [x0], x[[OFFSET]] %elt = extractelement <16 x i8> %in, i32 3 store i8 %elt, i8* %addr @@ -435,7 +435,7 @@ define i16* @test_v8i16_post_imm_st1_lane(<8 x i16> %in, i16* %addr) { define i16* @test_v8i16_post_reg_st1_lane(<8 x i16> %in, i16* %addr) { ; CHECK-LABEL: test_v8i16_post_reg_st1_lane: -; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x4 +; CHECK: mov w[[OFFSET:[0-9]+]], #4 ; CHECK: st1.h { v0 }[3], [x0], x[[OFFSET]] %elt = extractelement <8 x i16> %in, i32 3 store i16 %elt, i16* %addr @@ -456,7 +456,7 @@ define i32* @test_v4i32_post_imm_st1_lane(<4 x i32> %in, i32* %addr) { define i32* @test_v4i32_post_reg_st1_lane(<4 x i32> %in, i32* %addr) { ; CHECK-LABEL: test_v4i32_post_reg_st1_lane: -; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x8 +; CHECK: mov w[[OFFSET:[0-9]+]], #8 ; CHECK: st1.s { v0 }[3], [x0], x[[OFFSET]] %elt = extractelement <4 x i32> %in, i32 3 store i32 %elt, i32* %addr @@ -477,7 +477,7 @@ define float* @test_v4f32_post_imm_st1_lane(<4 x float> %in, float* %addr) { define float* @test_v4f32_post_reg_st1_lane(<4 x float> %in, float* %addr) { ; CHECK-LABEL: test_v4f32_post_reg_st1_lane: -; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x8 +; CHECK: mov w[[OFFSET:[0-9]+]], #8 ; CHECK: st1.s { v0 }[3], [x0], x[[OFFSET]] %elt = extractelement <4 x float> %in, i32 3 store float %elt, float* %addr @@ -498,7 +498,7 @@ define i64* @test_v2i64_post_imm_st1_lane(<2 x i64> %in, i64* %addr) { define i64* @test_v2i64_post_reg_st1_lane(<2 x i64> %in, i64* %addr) { ; CHECK-LABEL: test_v2i64_post_reg_st1_lane: -; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x10 +; CHECK: mov w[[OFFSET:[0-9]+]], #16 ; CHECK: st1.d { v0 }[1], [x0], x[[OFFSET]] %elt = extractelement <2 x i64> %in, i64 1 store i64 %elt, i64* %addr @@ -519,7 +519,7 @@ define double* @test_v2f64_post_imm_st1_lane(<2 x double> %in, double* %addr) { define double* @test_v2f64_post_reg_st1_lane(<2 x double> %in, double* %addr) { ; CHECK-LABEL: test_v2f64_post_reg_st1_lane: -; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x10 +; CHECK: mov w[[OFFSET:[0-9]+]], #16 ; CHECK: st1.d { v0 }[1], [x0], x[[OFFSET]] %elt = extractelement <2 x double> %in, i32 1 store double %elt, double* %addr @@ -540,7 +540,7 @@ define i8* @test_v8i8_post_imm_st1_lane(<8 x i8> %in, i8* %addr) { define i8* @test_v8i8_post_reg_st1_lane(<8 x i8> %in, i8* %addr) { ; CHECK-LABEL: test_v8i8_post_reg_st1_lane: -; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x2 +; CHECK: mov w[[OFFSET:[0-9]+]], #2 ; CHECK: st1.b { v0 }[3], [x0], x[[OFFSET]] %elt = extractelement <8 x i8> %in, i32 3 store i8 %elt, i8* %addr @@ -561,7 +561,7 @@ define i16* @test_v4i16_post_imm_st1_lane(<4 x i16> %in, i16* %addr) { define i16* @test_v4i16_post_reg_st1_lane(<4 x i16> %in, i16* %addr) { ; CHECK-LABEL: test_v4i16_post_reg_st1_lane: -; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x4 +; CHECK: mov w[[OFFSET:[0-9]+]], #4 ; CHECK: st1.h { v0 }[3], [x0], x[[OFFSET]] %elt = extractelement <4 x i16> %in, i32 3 store i16 %elt, i16* %addr @@ -582,7 +582,7 @@ define i32* @test_v2i32_post_imm_st1_lane(<2 x i32> %in, i32* %addr) { define i32* @test_v2i32_post_reg_st1_lane(<2 x i32> %in, i32* %addr) { ; CHECK-LABEL: test_v2i32_post_reg_st1_lane: -; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x8 +; CHECK: mov w[[OFFSET:[0-9]+]], #8 ; CHECK: st1.s { v0 }[1], [x0], x[[OFFSET]] %elt = extractelement <2 x i32> %in, i32 1 store i32 %elt, i32* %addr @@ -603,7 +603,7 @@ define float* @test_v2f32_post_imm_st1_lane(<2 x float> %in, float* %addr) { define float* @test_v2f32_post_reg_st1_lane(<2 x float> %in, float* %addr) { ; CHECK-LABEL: test_v2f32_post_reg_st1_lane: -; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x8 +; CHECK: mov w[[OFFSET:[0-9]+]], #8 ; CHECK: st1.s { v0 }[1], [x0], x[[OFFSET]] %elt = extractelement <2 x float> %in, i32 1 store float %elt, float* %addr |
